fix vga colours
[fpga-games] / galaxian / src / mc_vga_if.v
CommitLineData
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1//===============================================================================\r
2// FPGA VGA INTERFACE FOR ALTERA CYCLONE & XILINX SPARTAN2E\r
3//\r
4// Version : 2.00\r
5//\r
6// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// based on a design by Tatsuyuki Satoh\r
9//\r
10// Important !\r
11//\r
12// This program is freeware for non-commercial use. \r
13// An author does no guarantee about this program.\r
14// You can use this under your own risk.\r
15//\r
16// 2004- 9-18 added SPARTAN2E DEVIDE . K.DEGAWA\r
17//================================================================================\r
18`include "src/mc_conf.v"\r
19\r
20module mc_vga_if(\r
21\r
22I_CLK_1,\r
23I_CLK_2,\r
24I_R,\r
25I_G,\r
26I_B,\r
27I_H_SYNC,\r
28I_V_SYNC,\r
29\r
30O_R,\r
31O_G,\r
32O_B,\r
33O_H_SYNCn,\r
34O_V_SYNCn\r
35\r
36);\r
37\r
38// input signals\r
39input I_CLK_1; // 6.144MHz input pixel clock\r
40input I_CLK_2; // 12.288Mhz output pixel clock\r
41input [2:0]I_R; // R in\r
42input [2:0]I_G; // G in\r
43input [1:0]I_B; // B in\r
44input I_H_SYNC; // HSYNC input (16KHz)\r
45input I_V_SYNC; // VSYNC input (60Hz)\r
46\r
47// output signals\r
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48output [2:0]O_R; // R out\r
49output [2:0]O_G; // G out\r
50output [1:0]O_B; // B out\r
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51output O_H_SYNCn; // HSYNC output\r
52output O_V_SYNCn; // VSYNC output\r
53\r
54//---------------------------------------------------------------------------\r
55// setup parameter\r
56//---------------------------------------------------------------------------\r
57\r
58parameter H_COUNT = 384; // number of pixels in H-SCAN\r
59parameter HS_POS = 16; // HSYNC position \r
60parameter HS_WIDTH = HS_POS+8; // HSYNC width / pixel\r
61parameter VS_WIDTH = 8; // VSYNC width / HSYNC_OUT\r
62\r
63//---------------------------------------------------------------------------\r
64// input timming\r
65//---------------------------------------------------------------------------\r
66reg [8:0]Hpos_in; // input capture postion\r
67reg L_Hsync_i;\r
68wire HP_in = ~L_Hsync_i & I_H_SYNC;\r
69always@(posedge I_CLK_1)\r
70begin\r
71 Hpos_in <= HP_in ? 0: Hpos_in + 1;\r
72 L_Hsync_i <= I_H_SYNC;\r
73end\r
74\r
75//---------------------------------------------------------------------------\r
76//output timming\r
77//---------------------------------------------------------------------------\r
78reg [8:0]Hpos_out;\r
79reg L_Hsync_o;\r
80wire HP_out = ~L_Hsync_o & I_H_SYNC;\r
81wire HP_ret = HP_out | (Hpos_out == H_COUNT-1);\r
82\r
83always@(posedge I_CLK_2)\r
84begin\r
85 Hpos_out <= HP_ret ? 0:Hpos_out + 1;\r
86 L_Hsync_o <= I_H_SYNC;\r
87end\r
88\r
89reg O_Hsync;\r
90always@(posedge I_CLK_2)\r
91begin\r
92 case(Hpos_out)\r
93 HS_POS :O_Hsync <= 1'b1;\r
94 HS_WIDTH:O_Hsync <= 1'b0;\r
95 default :;\r
96 endcase\r
97end\r
98\r
99//---------------------------------------------------------------------------\r
100// RGB capture(portA) & output(portB)\r
101//---------------------------------------------------------------------------\r
102wire [7:0]rgb_in = {I_R,I_G,I_B}; // RGB input\r
103wire [7:0]rgb_out; // RGB output\r
104\r
105`ifdef DEVICE_CYCLONE\r
106alt_ram_512_8_d double_scan_ram(\r
107\r
108.clock_a(I_CLK_1),\r
109.address_a(Hpos_in),\r
110.q_a(),\r
111.data_a(rgb_in),\r
112.wren_a(1'b1),\r
113.enable_a(1'b1),\r
114.aclr_a(1'b0),\r
115\r
116.clock_b(I_CLK_2),\r
117.address_b(Hpos_out),\r
118.q_b(rgb_out),\r
119.data_b(4'h0),\r
120.wren_b(1'b0),\r
121.enable_b(1'b1),\r
122.aclr_b(1'b0)\r
123\r
124);\r
125`endif\r
126`ifdef DEVICE_SPARTAN2E\r
127RAMB4_S8_S8 double_scan_ram (\r
128\r
129.CLKA(I_CLK_1),\r
130.ADDRA(Hpos_in),\r
131.DOA(),\r
132.DIA(rgb_in),\r
133.WEA(1'b1),\r
134.ENA(1'b1),\r
135.RSTA(1'b0),\r
136\r
137.CLKB(I_CLK_2),\r
138.ADDRB(Hpos_out),\r
139.DOB(rgb_out),\r
140.DIB(4'h0),\r
141.WEB(1'b0),\r
142.ENB(1'b1),\r
143.RSTB(1'b0)\r
144\r
145);\r
146`endif\r
147//---------------------------------------------------------------------------\r
148// vsync remake\r
149//\r
150// 1 HSYNC_IN delay & HSYNC pulse width = 4xHSYNC(in)\r
151//---------------------------------------------------------------------------\r
152\r
153reg [2:0]vs_cnt;\r
154reg O_Vsync;\r
155\r
156always @(posedge O_Hsync)\r
157begin\r
158 if(~I_V_SYNC)begin\r
159 vs_cnt <= VS_WIDTH-1;\r
160 end\r
161 else begin\r
162 if(vs_cnt==0) vs_cnt <= vs_cnt;\r
163 else vs_cnt <= vs_cnt-1;\r
164 end\r
165end\r
166always @(posedge O_Hsync)\r
167begin\r
168 case(vs_cnt)\r
169 VS_WIDTH-2 :O_Vsync <= 1;\r
170 0 :O_Vsync <= 0;\r
171 endcase\r
172end\r
173//---------------------------------------------------------------------------\r
174// output\r
175//---------------------------------------------------------------------------\r
176\r
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177assign O_R = rgb_out[7:5]; \r
178assign O_G = rgb_out[4:2];\r
179assign O_B = rgb_out[1:0]; \r
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180\r
181// converted H V SYNC\r
182assign O_H_SYNCn = ~O_Hsync;\r
183assign O_V_SYNCn = ~O_Vsync;\r
184\r
185endmodule\r
186\r
187`ifdef DEVICE_CYCLONE\r
188module alt_ram_512_8_d (\r
189 data_a,\r
190 wren_a,\r
191 address_a,\r
192 data_b,\r
193 address_b,\r
194 wren_b,\r
195 clock_a,\r
196 enable_a,\r
197 clock_b,\r
198 enable_b,\r
199 aclr_a,\r
200 aclr_b,\r
201 q_a,\r
202 q_b);\r
203\r
204 input [7:0] data_a;\r
205 input wren_a;\r
206 input [8:0] address_a;\r
207 input [7:0] data_b;\r
208 input [8:0] address_b;\r
209 input wren_b;\r
210 input clock_a;\r
211 input enable_a;\r
212 input clock_b;\r
213 input enable_b;\r
214 input aclr_a;\r
215 input aclr_b;\r
216 output [7:0] q_a;\r
217 output [7:0] q_b;\r
218\r
219 wire [7:0] sub_wire0;\r
220 wire [7:0] sub_wire1;\r
221 wire [7:0] q_a = sub_wire0[7:0];\r
222 wire [7:0] q_b = sub_wire1[7:0];\r
223\r
224 altsyncram altsyncram_component (\r
225 .clocken0 (enable_a),\r
226 .clocken1 (enable_b),\r
227 .wren_a (wren_a),\r
228 .aclr0 (aclr_a),\r
229 .clock0 (clock_a),\r
230 .wren_b (wren_b),\r
231 .aclr1 (aclr_b),\r
232 .clock1 (clock_b),\r
233 .address_a (address_a),\r
234 .address_b (address_b),\r
235 .data_a (data_a),\r
236 .data_b (data_b),\r
237 .q_a (sub_wire0),\r
238 .q_b (sub_wire1));\r
239 defparam\r
240 altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",\r
241 altsyncram_component.width_a = 8,\r
242 altsyncram_component.widthad_a = 9,\r
243 altsyncram_component.numwords_a = 512,\r
244 altsyncram_component.width_b = 8,\r
245 altsyncram_component.widthad_b = 9,\r
246 altsyncram_component.numwords_b = 512,\r
247 altsyncram_component.lpm_type = "altsyncram",\r
248 altsyncram_component.width_byteena_a = 1,\r
249 altsyncram_component.width_byteena_b = 1,\r
250 altsyncram_component.outdata_reg_a = "UNREGISTERED",\r
251 altsyncram_component.outdata_aclr_a = "NONE",\r
252 altsyncram_component.outdata_reg_b = "UNREGISTERED",\r
253 altsyncram_component.indata_aclr_a = "CLEAR0",\r
254 altsyncram_component.wrcontrol_aclr_a = "CLEAR0",\r
255 altsyncram_component.address_aclr_a = "CLEAR0",\r
256 altsyncram_component.indata_reg_b = "CLOCK1",\r
257 altsyncram_component.address_reg_b = "CLOCK1",\r
258 altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1",\r
259 altsyncram_component.indata_aclr_b = "CLEAR1",\r
260 altsyncram_component.wrcontrol_aclr_b = "CLEAR1",\r
261 altsyncram_component.address_aclr_b = "CLEAR1",\r
262 altsyncram_component.outdata_aclr_b = "NONE",\r
263 altsyncram_component.ram_block_type = "M4K",\r
264 altsyncram_component.intended_device_family = "Stratix";\r
265\r
266\r
267endmodule\r
268`endif\r
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