cleanup rom usage
[fpga-games] / galaxian / src / roms.v
CommitLineData
782690d0 1module galaxian_roms(
556154d1 2I_ROM_CLK,
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MG
3I_ADDR,
4O_DATA
5);
6
556154d1 7input I_ROM_CLK;
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8input [18:0]I_ADDR;
9output [7:0]O_DATA;
10
11//CPU-Roms
12wire [7:0]U_ROM_D;
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13
14GALAXIAN_U U_ROM(
556154d1 15.CLK(I_ROM_CLK),
b884ab49 16.ADDR(I_ADDR[10:0]),
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17.DATA(U_ROM_D),
18.ENA(1'b1)
19);
20
21wire [7:0]V_ROM_D;
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MG
22
23GALAXIAN_V V_ROM(
556154d1 24.CLK(I_ROM_CLK),
b884ab49 25.ADDR(I_ADDR[10:0]),
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26.DATA(V_ROM_D),
27.ENA(1'b1)
28);
29
30wire [7:0]W_ROM_D;
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31
32GALAXIAN_W W_ROM(
556154d1 33.CLK(I_ROM_CLK),
b884ab49 34.ADDR(I_ADDR[10:0]),
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35.DATA(W_ROM_D),
36.ENA(1'b1)
37);
38
39wire [7:0]Y_ROM_D;
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MG
40
41GALAXIAN_Y Y_ROM(
556154d1 42.CLK(I_ROM_CLK),
b884ab49 43.ADDR(I_ADDR[10:0]),
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44.DATA(Y_ROM_D),
45.ENA(1'b1)
46);
47
48//7L CPU-Rom
49wire [7:0]L_ROM_D;
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MG
50
51GALAXIAN_7L L_ROM(
556154d1 52.CLK(I_ROM_CLK),
b884ab49 53.ADDR(I_ADDR[10:0]),
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54.DATA(L_ROM_D),
55.ENA(1'b1)
56);
57
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58reg [7:0]DATA_OUT;
59
60// address map
61//--------------------------------------------------
62// 0x00000 - 0x007FF galmidw.u CPU-ROM
63// 0x00800 - 0x00FFF galmidw.v CPU-ROM
64// 0x01000 - 0x017FF galmidw.w CPU-ROM
65// 0x01800 - 0x01FFF galmidw.y CPU-ROM
66// 0x02000 - 0x027FF 7l CPU-ROM
67// 0x04000 - 0x047FF 1k.bin VID-ROM
68// 0x05000 - 0x057FF 1h.bin VID-ROM
69// 0x10000 - 0x3FFFF mc_wav_2.bin Sound(Wav)Data
556154d1 70always@(posedge I_ROM_CLK)
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71begin
72 if (I_ADDR <= 18'h7ff) begin
73 //u
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74 DATA_OUT <= U_ROM_D;
75 end
b884ab49 76 else if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
782690d0 77 //v
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78 DATA_OUT <= V_ROM_D;
79 end
b884ab49 80 else if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
782690d0 81 //w
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82 DATA_OUT <= W_ROM_D;
83 end
b884ab49 84 else if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
782690d0 85 //y
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86 DATA_OUT <= Y_ROM_D;
87 end
b884ab49 88 else if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
782690d0 89 //7l
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90 DATA_OUT <= L_ROM_D;
91 end
b884ab49 92 else begin
475bf7e7 93 DATA_OUT <= DATA_OUT;
b884ab49 94 end
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95end
96
556154d1 97assign O_DATA = DATA_OUT;
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98
99endmodule
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