change timing for rom access

[fpga-games] / galaxian / src / mc_top.v

//===============================================================================\r
// FPGA GALAXIAN TOP\r
//\r
// Version : 2.50\r
//\r
// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
//\r
// Important !\r
//\r
// This program is freeware for non-commercial use. \r
// An author does no guarantee about this program.\r
// You can use this under your own risk.\r
//\r
// 2004- 4-30  galaxian modify by K.DEGAWA\r
// 2004- 5- 6  first release.\r
// 2004- 8-23  Improvement with T80-IP.\r
// 2004- 9-18  The description of ALTERA(CYCLONE) and XILINX(SPARTAN2E) was made one.\r
// 2004- 9-22  The problem which missile didn't sometimes come out from was improved.\r
//================================================================================\r
\r
`include "src/mc_conf.v"	     \r
					     \r
module mc_top(\r
\r
//    FPGA_USE\r
I_CLK_125M,\r
\r
`ifdef PSPAD_USE\r
// PS_PAD interface\r
psCLK,\r
psSEL,\r
psTXD,\r
psRXD,\r
`endif\r
\r
//    ROM IF\r
//O_ROM_AB,\r
//I_ROM_DB,\r
//O_ROM_OEn,\r
//O_ROM_CSn,\r
//O_ROM_WEn,\r
\r
//    INPORT SW IF\r
I_PSW,\r
\r
//    SOUND OUT\r
O_SOUND_OUT_L,\r
O_SOUND_OUT_R,\r
\r
//    VGA (VIDEO) IF\r
O_VGA_R,\r
O_VGA_G,\r
O_VGA_B,\r
O_VGA_H_SYNCn,\r
O_VGA_V_SYNCn\r
\r
);\r
\r
//    FPGA_USE\r
input  I_CLK_125M;\r
\r
//    CPU ADDRESS BUS\r
wire   [15:0]W_A;\r
//    CPU IF\r
wire   W_CPU_RDn;\r
wire   W_CPU_WRn;\r
wire   W_CPU_MREQn;\r
wire   W_CPU_RFSHn;\r
wire   W_CPU_BUSAKn;\r
wire   W_CPU_IORQn;\r
wire   W_CPU_M1n;\r
wire   W_CPU_CLK;\r
wire   W_CPU_HRDWR_RESETn;\r
wire   W_CPU_WAITn;\r
wire   W_CPU_NMIn;\r
\r
`ifdef PSPAD_USE\r
// PS_PAD interface\r
input	psRXD;\r
output	psTXD,psCLK,psSEL;\r
`endif\r
\r
//    ROM IF\r
//output [18:0]O_ROM_AB;\r
//input  [7:0]I_ROM_DB;\r
//output O_ROM_OEn;\r
//output O_ROM_CSn;\r
//output O_ROM_WEn;\r
\r
//    INPORT SW IF\r
input  [8:0]I_PSW;\r
\r
//    SOUND OUT \r
output  O_SOUND_OUT_L;\r
output  O_SOUND_OUT_R;\r
\r
//    VGA (VIDEO) IF\r
output [3:0]O_VGA_R;\r
output [3:0]O_VGA_G;\r
output [3:0]O_VGA_B;\r
output O_VGA_H_SYNCn;\r
output O_VGA_V_SYNCn;\r
\r
wire   W_RESETn = |(~I_PSW[8:5]);\r
//------ CLOCK GEN ---------------------------\r
wire   I_CLK_18432M;\r
wire   W_CLK_12M,WB_CLK_12M;\r
wire   W_CLK_6M,WB_CLK_6M;\r
wire   W_STARS_CLK;\r
wire   W_ROM_CLK;\r
\r
mc_dcm clockgen(\r
.CLKIN_IN(I_CLK_125M),\r
.RST_IN(! W_RESETn),\r
.CLKFX_OUT(I_CLK_18432M),\r
.CLK0_OUT(W_ROM_CLK)\r
);\r
\r
//------ H&V COUNTER -------------------------\r
wire   [8:0]W_H_CNT;\r
wire   [7:0]W_V_CNT;\r
wire   W_H_BL;\r
wire   W_V_BLn;\r
wire   W_C_BLn;\r
wire   W_H_SYNC;\r
wire   W_V_SYNC;\r
\r
//------ CPU RAM  ----------------------------\r
wire   [7:0]W_CPU_RAM_DO;\r
\r
//------ ADDRESS DECDER ----------------------\r
wire   W_CPU_ROM_CSn;\r
wire   W_CPU_RAM_RDn;\r
wire   W_CPU_RAM_WRn;\r
wire   W_CPU_RAM_CSn;\r
wire   W_OBJ_RAM_RDn;\r
wire   W_OBJ_RAM_WRn;\r
wire   W_OBJ_RAM_RQn;\r
wire   W_VID_RAM_RDn;\r
wire   W_VID_RAM_WRn;\r
wire   W_SW0_OEn;\r
wire   W_SW1_OEn;\r
wire   W_DIP_OEn;\r
wire   W_WDR_OEn;\r
wire   W_LAMP_WEn;\r
wire   W_SOUND_WEn;\r
wire   W_PITCHn;\r
wire   W_H_FLIP;\r
wire   W_V_FLIP;\r
wire   W_BD_G;\r
wire   W_STARS_ON;\r
\r
wire   W_VID_RDn = W_OBJ_RAM_RDn & W_VID_RAM_RDn ;\r
wire   W_SW_OEn = W_SW0_OEn & W_SW1_OEn & W_DIP_OEn ;\r
//------- INPORT -----------------------------\r
wire   [7:0]W_SW_DO;\r
//------- VIDEO  -----------------------------\r
wire   [7:0]W_VID_DO;\r
//--------------------------------------------\r
\r
mc_clock MC_CLK(\r
\r
.I_CLK_18M(I_CLK_18432M),\r
.O_CLK_12M(WB_CLK_12M),\r
.O_CLK_06M(WB_CLK_6M)\r
\r
);\r
\r
`ifdef DEVICE_CYCLONE\r
assign W_CLK_12M = WB_CLK_12M;\r
assign W_CLK_6M  = WB_CLK_6M;\r
`endif\r
`ifdef DEVICE_SPARTAN2E\r
BUFG	BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) );\r
BUFG	BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) );\r
`endif\r
//---  DATA I/F -------------------------------------\r
reg    [7:0]W_CPU_ROM_DO;\r
wire   [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;\r
\r
wire   [7:0]W_BDO = W_SW_DO | W_VID_DO | W_CPU_RAM_DO | W_CPU_ROM_DOB ;\r
wire   [7:0]W_BDI;\r
\r
//---  CPU I/F  -------------------------------------\r
reg  [3:0]rst_count;\r
always@(posedge W_H_CNT[0] or negedge W_RESETn)\r
begin\r
   if(! W_RESETn) rst_count <= 0;\r
   else begin\r
      if( rst_count == 15) \r
         rst_count <= rst_count;\r
      else\r
         rst_count <= rst_count+1;\r
   end\r
end\r
\r
assign W_CPU_RESETn = W_RESETn;\r
assign W_CPU_CLK = W_H_CNT[0];\r
\r
Z80IP CPU(\r
	\r
.CLK(W_CPU_CLK),\r
.RESET_N(W_CPU_RESETn),\r
.INT_N(1'b1),\r
.NMI_N(W_CPU_NMIn),\r
.ADRS(W_A),\r
.DOUT(W_BDI),\r
.DINP(W_BDO),\r
.M1_N(),\r
.MREQ_N(W_CPU_MREQn),\r
.IORQ_N(),\r
.RD_N(W_CPU_RDn ),\r
.WR_N(W_CPU_WRn ),\r
.WAIT_N(W_CPU_WAITn),\r
.BUSWO(),\r
.RFSH_N(W_CPU_RFSHn),\r
.HALT_N()\r
\r
);\r
\r
wire   W_CPU_RAM_CLK = W_CLK_12M & ~W_CPU_RAM_CSn;\r
\r
mc_cpu_ram MC_CPU_RAM(\r
\r
.I_CLK(W_CPU_RAM_CLK),\r
.I_ADDR(W_A[9:0]),\r
.I_D(W_BDI),\r
.I_WE(~W_CPU_WRn),\r
.I_OE(~W_CPU_RAM_RDn ),\r
.O_D(W_CPU_RAM_DO)\r
\r
);\r
\r
\r
mc_adec MC_ADEC(\r
\r
.I_CLK_12M(W_CLK_12M),\r
.I_CLK_6M(W_CLK_6M),\r
.I_CPU_CLK(W_H_CNT[0]),\r
.I_RSTn(W_RESETn),\r
\r
.I_CPU_A(W_A),\r
.I_CPU_D(W_BDI[0]),\r
.I_MREQn(W_CPU_MREQn),\r
.I_RFSHn(W_CPU_RFSHn),\r
.I_RDn(W_CPU_RDn),\r
.I_WRn(W_CPU_WRn),\r
.I_H_BL(W_H_BL),\r
.I_V_BLn(W_V_BLn),\r
\r
.O_WAITn(W_CPU_WAITn),\r
.O_NMIn(W_CPU_NMIn),\r
.O_CPU_ROM_CSn(W_CPU_ROM_CSn),\r
.O_CPU_RAM_RDn(W_CPU_RAM_RDn),\r
.O_CPU_RAM_WRn(W_CPU_RAM_WRn),\r
.O_CPU_RAM_CSn(W_CPU_RAM_CSn),\r
.O_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
.O_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
.O_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
.O_VID_RAM_RDn(W_VID_RAM_RDn),\r
.O_VID_RAM_WRn(W_VID_RAM_WRn),\r
.O_SW0_OEn(W_SW0_OEn),\r
.O_SW1_OEn(W_SW1_OEn),\r
.O_DIP_OEn(W_DIP_OEn),\r
.O_WDR_OEn(W_WDR_OEn),\r
.O_LAMP_WEn(W_LAMP_WEn),\r
.O_SOUND_WEn(W_SOUND_WEn),\r
.O_PITCHn(W_PITCHn),\r
.O_H_FLIP(W_H_FLIP),\r
.O_V_FLIP(W_V_FLIP),\r
.O_BD_G(W_BD_G),\r
.O_STARS_ON(W_STARS_ON)\r
\r
);\r
\r
//-------- SOUND I/F -----------------------------\r
//---  Parts 9L ---------\r
reg    [7:0]W_9L_Q;\r
always@(posedge W_CLK_12M or negedge W_RESETn)\r
begin\r
   if(W_RESETn == 1'b0)begin\r
      W_9L_Q <= 0;\r
   end \r
   else begin\r
      if(W_SOUND_WEn == 1'b0)begin\r
         case(W_A[2:0])\r
            3'h0 : W_9L_Q[0] <= W_BDI[0];\r
            3'h1 : W_9L_Q[1] <= W_BDI[0];\r
            3'h2 : W_9L_Q[2] <= W_BDI[0];\r
            3'h3 : W_9L_Q[3] <= W_BDI[0];\r
            3'h4 : W_9L_Q[4] <= W_BDI[0];\r
            3'h5 : W_9L_Q[5] <= W_BDI[0];\r
            3'h6 : W_9L_Q[6] <= W_BDI[0];\r
            3'h7 : W_9L_Q[7] <= W_BDI[0];\r
         endcase\r
      end\r
   end\r
end\r
wire   W_VOL1 = W_9L_Q[6];\r
wire   W_VOL2 = W_9L_Q[7];\r
wire   W_FIRE = W_9L_Q[5];\r
wire   W_HIT  = W_9L_Q[3];\r
wire   W_FS3  = W_9L_Q[2];\r
wire   W_FS2  = W_9L_Q[1];\r
wire   W_FS1  = W_9L_Q[0];\r
//---------------------------------------------------\r
//---- CPU DATA WATCH -------------------------------\r
wire   ZMWR = W_CPU_MREQn | W_CPU_WRn ;\r
\r
reg   [1:0]on_game;\r
always @(posedge W_CPU_CLK)\r
begin\r
   if(~ZMWR)begin\r
      if(W_A == 16'h4007)begin\r
         if(W_BDI == 8'h00) \r
            on_game[0] <= 1;\r
         else\r
            on_game[0] <= 0;\r
      end\r
      if(W_A == 16'h4005)begin\r
         if(W_BDI == 8'h03 || W_BDI == 8'h04 ) \r
            on_game[1] <= 1;\r
         else\r
            on_game[1] <= 0;\r
      end\r
   end  \r
end\r
\r
`ifdef PSPAD_USE\r
reg   died;\r
always @(posedge W_CPU_CLK)\r
begin\r
   if(~ZMWR)begin\r
      if(W_A == 16'h4206)begin\r
         if(W_BDI == 8'h00) \r
            died <= 0;\r
         else\r
            died <= 1;\r
      end\r
   end\r
end\r
//---- PS_PAD Interface -----------------------------\r
wire	[8:0]ps_PSW;\r
wire	VIB_SW = died & (&on_game[1:0]);\r
\r
fpga_arcade_if pspad(\r
\r
.CLK_18M432(I_CLK_18432M),\r
.I_RSTn(W_RESETn),\r
.psCLK(psCLK),\r
.psSEL(psSEL),\r
.psTXD(psTXD),\r
.psRXD(psRXD),\r
.ps_PSW(ps_PSW),\r
.I_VIB_SW(VIB_SW)\r
\r
);\r
`endif\r
//---- SW Interface ---------------------------------\r
`ifdef PSPAD_USE\r
wire   L1 = I_PSW[2] & ps_PSW[2];\r
wire   R1 = I_PSW[3] & ps_PSW[3];\r
wire   U1 = I_PSW[0];\r
wire   D1 = I_PSW[1];\r
wire   J1 = I_PSW[4] & ps_PSW[8];\r
\r
wire   S1 = (U1|J1)  & ps_PSW[6];\r
wire   S2 = (D1|J1)  & ps_PSW[7];\r
\r
wire   C1 = (L1|R1|U1|~D1) & ps_PSW[4];\r
`else\r
wire   L1 = ! I_PSW[2];\r
wire   R1 = ! I_PSW[3];\r
wire   U1 = ! I_PSW[0];\r
wire   D1 = ! I_PSW[1];\r
wire   J1 = ! I_PSW[4];\r
\r
wire   S1 = ! I_PSW[5];\r
wire   S2 = ! I_PSW[7];\r
\r
wire   C1 = ! I_PSW[6];\r
`endif\r
wire   C2 = ! I_PSW[8];\r
\r
wire   L2 = L1;\r
wire   R2 = R1;\r
wire   U2 = U1;\r
wire   D2 = D1;\r
wire   J2 = J1;\r
\r
mc_inport MC_INPORT(\r
\r
.I_COIN1(~C1),      //  ACTIVE HI\r
.I_COIN2(~C2),      //  ACTIVE HI\r
.I_1P_LE(~L1),      //  ACTIVE HI\r
.I_1P_RI(~R1),      //  ACTIVE HI\r
.I_1P_SH(~J1),      //  ACTIVE HI\r
.I_2P_LE(~L2),      //  ACTIVE HI\r
.I_2P_RI(~R2),      //  ACTIVE HI\r
.I_2P_SH(~J2),      //  ACTIVE HI\r
.I_1P_START(~S1),   //  ACTIVE HI\r
.I_2P_START(~S2),   //  ACTIVE HI\r
\r
.I_SW0_OEn(W_SW0_OEn),\r
.I_SW1_OEn(W_SW1_OEn),\r
.I_DIP_OEn(W_DIP_OEn),\r
\r
.O_D(W_SW_DO)\r
\r
);\r
\r
//-----------------------------------------------------------------------------\r
//------- ROM           -------------------------------------------------------\r
reg    [18:0]ROM_A;\r
wire   [10:0]W_OBJ_ROM_A;\r
reg    [7:0]W_OBJ_ROM_A_D;\r
reg    [7:0]W_OBJ_ROM_B_D;\r
\r
wire   [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;\r
reg    [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;\r
\r
wire   [7:0]ROM_D; // = I_ROM_DB;\r
//assign O_ROM_AB  = ROM_A;\r
\r
//assign O_ROM_OEn = 1'b0;\r
//assign O_ROM_CSn = 1'b0;\r
//assign O_ROM_WEn = 1'b1;\r
\r
galaxian_roms ROMS(\r
.I_ROM_CLK(W_ROM_CLK),\r
.I_ADDR(ROM_A),\r
.O_DATA(ROM_D)\r
);\r
\r
\r
reg    [1:0]clk_d;\r
reg    [4:0]seq;\r
always @(posedge I_CLK_18432M)\r
begin\r
  // 24 phase generator\r
   clk_d[0] <= W_H_CNT[0] & W_H_CNT[1] & W_H_CNT[2];\r
   clk_d[1] <= clk_d[0];\r
   seq <= (~clk_d[1] & clk_d[0]) ? 0 : seq+1;\r
   case(seq)\r
      0:begin\r
        ROM_A <= W_WAV_A0;\r
        W_CPU_ROM_DO <= ROM_D;\r
        end\r
      2:begin\r
        ROM_A <= W_WAV_A1;\r
        W_WAV_D0 <= ROM_D;\r
        end\r
      4:begin\r
        ROM_A <= {3'h0,W_A[15:0]};\r
        W_WAV_D1 <= ROM_D;\r
        end\r
      6:begin\r
        ROM_A <= W_WAV_A2;\r
        W_CPU_ROM_DO <= ROM_D;\r
        end\r
      8:W_WAV_D2 <= ROM_D;\r
     10:ROM_A <= {3'h0,W_A[15:0]};\r
     12:W_CPU_ROM_DO <= ROM_D;\r
     14:ROM_A <= {3'h0,W_A[15:0]};\r
     16:begin\r
        ROM_A <= {3'h0,4'h4,1'b0,W_OBJ_ROM_A};\r
        W_CPU_ROM_DO <= ROM_D;\r
        end\r
     18:begin\r
        ROM_A <= {3'h0,4'h5,1'b0,W_OBJ_ROM_A};\r
        W_OBJ_ROM_A_D <= ROM_D;\r
        end\r
     20:begin\r
        ROM_A <= {3'h0,W_A[15:0]};\r
        W_OBJ_ROM_B_D <= ROM_D;\r
        end\r
     default:;\r
   endcase\r
end\r
//-----------------------------------------------------------------------------\r
\r
wire   W_V_BL2n;\r
\r
mc_hv_count MC_HV(\r
\r
.I_CLK(WB_CLK_6M),\r
.I_RSTn(W_RESETn),\r
\r
.O_H_CNT(W_H_CNT),\r
.O_H_SYNC(W_H_SYNC),\r
.O_H_BL(W_H_BL),\r
.O_V_CNT(W_V_CNT),\r
.O_V_SYNC(W_V_SYNC),\r
.O_V_BL2n(W_V_BL2n),\r
.O_V_BLn(W_V_BLn),\r
.O_C_BLn(W_C_BLn)\r
\r
);\r
\r
//------ VIDEO  -----------------------------\r
wire   W_8HF;\r
wire   W_1VF;\r
wire   W_C_BLnX;\r
wire   W_256HnX;\r
wire   W_MISSILEn;\r
wire   W_SHELLn;\r
wire   [1:0]W_VID;\r
wire   [2:0]W_COL;\r
\r
mc_video MC_VID(\r
.I_CLK_18M(I_CLK_18432M),\r
.I_CLK_12M(W_CLK_12M),\r
.I_CLK_6M(W_CLK_6M),\r
.I_H_CNT(W_H_CNT),\r
.I_V_CNT(W_V_CNT),\r
.I_H_FLIP(W_H_FLIP),\r
.I_V_FLIP(W_V_FLIP),\r
.I_V_BLn(W_V_BLn),\r
.I_C_BLn(W_C_BLn),\r
\r
.I_A(W_A[9:0]),\r
.I_OBJ_SUB_A(3'b000),\r
.I_BD(W_BDI),\r
.I_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
.I_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
.I_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
.I_VID_RAM_RDn(W_VID_RAM_RDn),\r
.I_VID_RAM_WRn(W_VID_RAM_WRn),\r
\r
.O_OBJ_ROM_A(W_OBJ_ROM_A),\r
.I_OBJ_ROM_A_D(W_OBJ_ROM_A_D),\r
.I_OBJ_ROM_B_D(W_OBJ_ROM_B_D),\r
\r
.O_C_BLnX(W_C_BLnX),\r
.O_8HF(W_8HF),\r
.O_256HnX(W_256HnX),\r
.O_1VF(W_1VF),\r
.O_MISSILEn(W_MISSILEn),\r
.O_SHELLn(W_SHELLn),\r
.O_BD(W_VID_DO),\r
.O_VID(W_VID),\r
.O_COL(W_COL)\r
\r
);\r
\r
wire   W_C_BLX;\r
wire   W_STARS_OFFn;\r
wire   [2:0]W_VIDEO_R;\r
wire   [2:0]W_VIDEO_G;\r
wire   [1:0]W_VIDEO_B;\r
\r
mc_col_pal MC_COL_PAL(\r
\r
.I_CLK_12M(W_CLK_12M),\r
.I_CLK_6M(W_CLK_6M),\r
.I_VID(W_VID),\r
.I_COL(W_COL),\r
.I_C_BLnX(W_C_BLnX),\r
\r
.O_C_BLX(W_C_BLX),\r
.O_STARS_OFFn(W_STARS_OFFn),\r
.O_R(W_VIDEO_R),\r
.O_G(W_VIDEO_G),\r
.O_B(W_VIDEO_B)\r
\r
);\r
\r
wire   [2:0]W_STARS_R;\r
wire   [2:0]W_STARS_G;\r
wire   [1:0]W_STARS_B;\r
\r
mc_stars MC_STARS( \r
\r
.I_CLK_18M(I_CLK_18432M),\r
`ifdef DEVICE_CYCLONE\r
.I_CLK_6M(~WB_CLK_6M),\r
`endif\r
`ifdef DEVICE_SPARTAN2E \r
.I_CLK_6M(WB_CLK_6M),   \r
`endif\r
.I_H_FLIP(W_H_FLIP),\r
.I_V_SYNC(W_V_SYNC),\r
.I_8HF(W_8HF),\r
.I_256HnX(W_256HnX),\r
.I_1VF(W_1VF),\r
.I_2V(W_V_CNT[1]),\r
.I_STARS_ON(W_STARS_ON),\r
.I_STARS_OFFn(W_STARS_OFFn),\r
\r
.O_R(W_STARS_R),\r
.O_G(W_STARS_G),\r
.O_B(W_STARS_B),\r
.O_NOISE()\r
\r
);\r
\r
wire   [2:0]W_R;\r
wire   [2:0]W_G;\r
wire   [1:0]W_B;\r
\r
mc_vedio_mix MIX(\r
\r
.I_VID_R(W_VIDEO_R),\r
.I_VID_G(W_VIDEO_G),\r
.I_VID_B(W_VIDEO_B),\r
.I_STR_R(W_STARS_R),\r
.I_STR_G(W_STARS_G),\r
.I_STR_B(W_STARS_B),\r
\r
.I_C_BLnXX(~W_C_BLX),\r
.I_C_BLX(W_C_BLX | ~W_V_BL2n),\r
.I_MISSILEn(W_MISSILEn),\r
.I_SHELLn(W_SHELLn),\r
\r
.O_R(W_R),\r
.O_G(W_G),\r
.O_B(W_B)\r
\r
);\r
\r
wire [2:0]W_VGA_R;\r
wire [2:0]W_VGA_G;\r
wire [1:0]W_VGA_B;\r
\r
`ifdef VGA_USE\r
mc_vga_if  VGA(\r
\r
// input\r
.I_CLK_1(W_CLK_6M),\r
.I_CLK_2(W_CLK_12M),\r
.I_R(W_R),\r
.I_G(W_G),\r
.I_B(W_B),\r
.I_H_SYNC(W_H_SYNC),\r
.I_V_SYNC(W_V_SYNC),\r
// output\r
.O_R(W_VGA_R),\r
.O_G(W_VGA_G),\r
.O_B(W_VGA_B),\r
.O_H_SYNCn(O_VGA_H_SYNCn),\r
.O_V_SYNCn(O_VGA_V_SYNCn)\r
\r
);\r
\r
`else\r
\r
assign W_VGA_R[2:0] = W_R;\r
\r
assign W_VGA_G[2:0] = W_G;\r
\r
assign W_VGA_B[1:0] = W_B;\r
\r
//assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ;  //  AKIDUKI LCD USED\r
assign O_VGA_H_SYNCn = ~W_H_SYNC ;\r
assign O_VGA_V_SYNCn = ~W_V_SYNC ;\r
\r
`endif\r
\r
assign O_VGA_R[3:0] = {W_VGA_R[0], W_VGA_R[1], W_VGA_R[2], 1'b0};\r
\r
assign O_VGA_G[3:0] = {W_VGA_G[0], W_VGA_G[1], W_VGA_G[2], 1'b0};\r
\r
assign O_VGA_B[3:0] = {W_VGA_B[0], W_VGA_B[1], 2'b0};\r
\r
wire   [7:0]W_SDAT_A;\r
\r
mc_sound_a MC_SOUND_A(\r
\r
.I_CLK_12M(W_CLK_12M),\r
.I_CLK_6M(W_CLK_6M),\r
.I_H_CNT1(W_H_CNT[1]),\r
.I_BD(W_BDI),\r
.I_PITCHn(W_PITCHn),\r
.I_VOL1(W_VOL1),\r
.I_VOL2(W_VOL2),\r
\r
.O_SDAT(W_SDAT_A),\r
.O_DO()\r
\r
);\r
\r
wire   [7:0]W_SDAT_B;\r
\r
mc_sound_b MC_SOUND_B(\r
\r
.I_CLK1(I_CLK_18432M),\r
.I_CLK2(W_CLK_6M),\r
.I_RSTn(rst_count[3]),\r
.I_SW({&on_game[1:0],W_HIT,W_FIRE}),\r
\r
.O_WAV_A0(W_WAV_A0),\r
.O_WAV_A1(W_WAV_A1),\r
.O_WAV_A2(W_WAV_A2),\r
.I_WAV_D0(W_WAV_D0),\r
.I_WAV_D1(W_WAV_D1),\r
.I_WAV_D2(W_WAV_D2),\r
\r
.O_SDAT(W_SDAT_B)\r
\r
);\r
\r
wire    W_DAC_A;\r
wire    W_DAC_B;\r
\r
assign  O_SOUND_OUT_L = W_DAC_A;\r
assign  O_SOUND_OUT_R = W_DAC_B;\r
\r
dac wav_dac_a(\r
\r
.Clk(I_CLK_18432M), \r
.Reset(~W_RESETn),\r
.DACin(W_SDAT_A),\r
.DACout(W_DAC_A)\r
\r
);\r
\r
dac wav_dac_b(\r
\r
.Clk(I_CLK_18432M), \r
.Reset(~W_RESETn),\r
.DACin(W_SDAT_B),\r
.DACout(W_DAC_B)\r
\r
);\r
\r
\r
endmodule\r
\r