change timing for rom access
[fpga-games] / galaxian / src / mc_top.v
CommitLineData
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1//===============================================================================\r
2// FPGA GALAXIAN TOP\r
3//\r
4// Version : 2.50\r
5//\r
6// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// Important !\r
9//\r
10// This program is freeware for non-commercial use. \r
11// An author does no guarantee about this program.\r
12// You can use this under your own risk.\r
13//\r
14// 2004- 4-30 galaxian modify by K.DEGAWA\r
15// 2004- 5- 6 first release.\r
16// 2004- 8-23 Improvement with T80-IP.\r
17// 2004- 9-18 The description of ALTERA(CYCLONE) and XILINX(SPARTAN2E) was made one.\r
18// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
19//================================================================================\r
20\r
21`include "src/mc_conf.v" \r
22 \r
23module mc_top(\r
24\r
25// FPGA_USE\r
26I_CLK_125M,\r
27\r
28`ifdef PSPAD_USE\r
29// PS_PAD interface\r
30psCLK,\r
31psSEL,\r
32psTXD,\r
33psRXD,\r
34`endif\r
35\r
36// ROM IF\r
37//O_ROM_AB,\r
38//I_ROM_DB,\r
39//O_ROM_OEn,\r
40//O_ROM_CSn,\r
41//O_ROM_WEn,\r
42\r
43// INPORT SW IF\r
44I_PSW,\r
45\r
46// SOUND OUT\r
47O_SOUND_OUT_L,\r
48O_SOUND_OUT_R,\r
49\r
50// VGA (VIDEO) IF\r
51O_VGA_R,\r
52O_VGA_G,\r
53O_VGA_B,\r
54O_VGA_H_SYNCn,\r
55O_VGA_V_SYNCn\r
56\r
57);\r
58\r
59// FPGA_USE\r
60input I_CLK_125M;\r
61\r
62// CPU ADDRESS BUS\r
63wire [15:0]W_A;\r
64// CPU IF\r
65wire W_CPU_RDn;\r
66wire W_CPU_WRn;\r
67wire W_CPU_MREQn;\r
68wire W_CPU_RFSHn;\r
69wire W_CPU_BUSAKn;\r
70wire W_CPU_IORQn;\r
71wire W_CPU_M1n;\r
72wire W_CPU_CLK;\r
73wire W_CPU_HRDWR_RESETn;\r
74wire W_CPU_WAITn;\r
75wire W_CPU_NMIn;\r
76\r
77`ifdef PSPAD_USE\r
78// PS_PAD interface\r
79input psRXD;\r
80output psTXD,psCLK,psSEL;\r
81`endif\r
82\r
83// ROM IF\r
84//output [18:0]O_ROM_AB;\r
85//input [7:0]I_ROM_DB;\r
86//output O_ROM_OEn;\r
87//output O_ROM_CSn;\r
88//output O_ROM_WEn;\r
89\r
90// INPORT SW IF\r
3fc34adf 91input [8:0]I_PSW;\r
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92\r
93// SOUND OUT \r
94output O_SOUND_OUT_L;\r
95output O_SOUND_OUT_R;\r
96\r
97// VGA (VIDEO) IF\r
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98output [3:0]O_VGA_R;\r
99output [3:0]O_VGA_G;\r
100output [3:0]O_VGA_B;\r
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101output O_VGA_H_SYNCn;\r
102output O_VGA_V_SYNCn;\r
103\r
3fc34adf 104wire W_RESETn = |(~I_PSW[8:5]);\r
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105//------ CLOCK GEN ---------------------------\r
106wire I_CLK_18432M;\r
107wire W_CLK_12M,WB_CLK_12M;\r
108wire W_CLK_6M,WB_CLK_6M;\r
109wire W_STARS_CLK;\r
556154d1 110wire W_ROM_CLK;\r
782690d0 111\r
b884ab49 112mc_dcm clockgen(\r
782690d0 113.CLKIN_IN(I_CLK_125M),\r
fc28fcbf 114.RST_IN(! W_RESETn),\r
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115.CLKFX_OUT(I_CLK_18432M),\r
116.CLK0_OUT(W_ROM_CLK)\r
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117);\r
118\r
119//------ H&V COUNTER -------------------------\r
120wire [8:0]W_H_CNT;\r
121wire [7:0]W_V_CNT;\r
122wire W_H_BL;\r
123wire W_V_BLn;\r
124wire W_C_BLn;\r
125wire W_H_SYNC;\r
126wire W_V_SYNC;\r
127\r
128//------ CPU RAM ----------------------------\r
129wire [7:0]W_CPU_RAM_DO;\r
130\r
131//------ ADDRESS DECDER ----------------------\r
132wire W_CPU_ROM_CSn;\r
133wire W_CPU_RAM_RDn;\r
134wire W_CPU_RAM_WRn;\r
135wire W_CPU_RAM_CSn;\r
136wire W_OBJ_RAM_RDn;\r
137wire W_OBJ_RAM_WRn;\r
138wire W_OBJ_RAM_RQn;\r
139wire W_VID_RAM_RDn;\r
140wire W_VID_RAM_WRn;\r
141wire W_SW0_OEn;\r
142wire W_SW1_OEn;\r
143wire W_DIP_OEn;\r
144wire W_WDR_OEn;\r
145wire W_LAMP_WEn;\r
146wire W_SOUND_WEn;\r
147wire W_PITCHn;\r
148wire W_H_FLIP;\r
149wire W_V_FLIP;\r
150wire W_BD_G;\r
151wire W_STARS_ON;\r
152\r
153wire W_VID_RDn = W_OBJ_RAM_RDn & W_VID_RAM_RDn ;\r
154wire W_SW_OEn = W_SW0_OEn & W_SW1_OEn & W_DIP_OEn ;\r
155//------- INPORT -----------------------------\r
156wire [7:0]W_SW_DO;\r
157//------- VIDEO -----------------------------\r
158wire [7:0]W_VID_DO;\r
159//--------------------------------------------\r
160\r
161mc_clock MC_CLK(\r
162\r
163.I_CLK_18M(I_CLK_18432M),\r
164.O_CLK_12M(WB_CLK_12M),\r
165.O_CLK_06M(WB_CLK_6M)\r
166\r
167);\r
168\r
169`ifdef DEVICE_CYCLONE\r
170assign W_CLK_12M = WB_CLK_12M;\r
171assign W_CLK_6M = WB_CLK_6M;\r
172`endif\r
173`ifdef DEVICE_SPARTAN2E\r
174BUFG BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) );\r
175BUFG BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) );\r
176`endif\r
177//--- DATA I/F -------------------------------------\r
178reg [7:0]W_CPU_ROM_DO;\r
179wire [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;\r
180\r
181wire [7:0]W_BDO = W_SW_DO | W_VID_DO | W_CPU_RAM_DO | W_CPU_ROM_DOB ;\r
182wire [7:0]W_BDI;\r
183\r
184//--- CPU I/F -------------------------------------\r
185reg [3:0]rst_count;\r
186always@(posedge W_H_CNT[0] or negedge W_RESETn)\r
187begin\r
188 if(! W_RESETn) rst_count <= 0;\r
189 else begin\r
190 if( rst_count == 15) \r
191 rst_count <= rst_count;\r
192 else\r
193 rst_count <= rst_count+1;\r
194 end\r
195end\r
196\r
197assign W_CPU_RESETn = W_RESETn;\r
198assign W_CPU_CLK = W_H_CNT[0];\r
199\r
200Z80IP CPU(\r
201 \r
202.CLK(W_CPU_CLK),\r
203.RESET_N(W_CPU_RESETn),\r
204.INT_N(1'b1),\r
205.NMI_N(W_CPU_NMIn),\r
206.ADRS(W_A),\r
207.DOUT(W_BDI),\r
208.DINP(W_BDO),\r
209.M1_N(),\r
210.MREQ_N(W_CPU_MREQn),\r
211.IORQ_N(),\r
212.RD_N(W_CPU_RDn ),\r
213.WR_N(W_CPU_WRn ),\r
214.WAIT_N(W_CPU_WAITn),\r
215.BUSWO(),\r
216.RFSH_N(W_CPU_RFSHn),\r
217.HALT_N()\r
218\r
219);\r
220\r
221wire W_CPU_RAM_CLK = W_CLK_12M & ~W_CPU_RAM_CSn;\r
222\r
223mc_cpu_ram MC_CPU_RAM(\r
224\r
225.I_CLK(W_CPU_RAM_CLK),\r
226.I_ADDR(W_A[9:0]),\r
227.I_D(W_BDI),\r
228.I_WE(~W_CPU_WRn),\r
229.I_OE(~W_CPU_RAM_RDn ),\r
230.O_D(W_CPU_RAM_DO)\r
231\r
232);\r
233\r
234\r
235mc_adec MC_ADEC(\r
236\r
237.I_CLK_12M(W_CLK_12M),\r
238.I_CLK_6M(W_CLK_6M),\r
239.I_CPU_CLK(W_H_CNT[0]),\r
240.I_RSTn(W_RESETn),\r
241\r
242.I_CPU_A(W_A),\r
243.I_CPU_D(W_BDI[0]),\r
244.I_MREQn(W_CPU_MREQn),\r
245.I_RFSHn(W_CPU_RFSHn),\r
246.I_RDn(W_CPU_RDn),\r
247.I_WRn(W_CPU_WRn),\r
248.I_H_BL(W_H_BL),\r
249.I_V_BLn(W_V_BLn),\r
250\r
251.O_WAITn(W_CPU_WAITn),\r
252.O_NMIn(W_CPU_NMIn),\r
253.O_CPU_ROM_CSn(W_CPU_ROM_CSn),\r
254.O_CPU_RAM_RDn(W_CPU_RAM_RDn),\r
255.O_CPU_RAM_WRn(W_CPU_RAM_WRn),\r
256.O_CPU_RAM_CSn(W_CPU_RAM_CSn),\r
257.O_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
258.O_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
259.O_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
260.O_VID_RAM_RDn(W_VID_RAM_RDn),\r
261.O_VID_RAM_WRn(W_VID_RAM_WRn),\r
262.O_SW0_OEn(W_SW0_OEn),\r
263.O_SW1_OEn(W_SW1_OEn),\r
264.O_DIP_OEn(W_DIP_OEn),\r
265.O_WDR_OEn(W_WDR_OEn),\r
266.O_LAMP_WEn(W_LAMP_WEn),\r
267.O_SOUND_WEn(W_SOUND_WEn),\r
268.O_PITCHn(W_PITCHn),\r
269.O_H_FLIP(W_H_FLIP),\r
270.O_V_FLIP(W_V_FLIP),\r
271.O_BD_G(W_BD_G),\r
272.O_STARS_ON(W_STARS_ON)\r
273\r
274);\r
275\r
276//-------- SOUND I/F -----------------------------\r
277//--- Parts 9L ---------\r
278reg [7:0]W_9L_Q;\r
279always@(posedge W_CLK_12M or negedge W_RESETn)\r
280begin\r
281 if(W_RESETn == 1'b0)begin\r
282 W_9L_Q <= 0;\r
283 end \r
284 else begin\r
285 if(W_SOUND_WEn == 1'b0)begin\r
286 case(W_A[2:0])\r
287 3'h0 : W_9L_Q[0] <= W_BDI[0];\r
288 3'h1 : W_9L_Q[1] <= W_BDI[0];\r
289 3'h2 : W_9L_Q[2] <= W_BDI[0];\r
290 3'h3 : W_9L_Q[3] <= W_BDI[0];\r
291 3'h4 : W_9L_Q[4] <= W_BDI[0];\r
292 3'h5 : W_9L_Q[5] <= W_BDI[0];\r
293 3'h6 : W_9L_Q[6] <= W_BDI[0];\r
294 3'h7 : W_9L_Q[7] <= W_BDI[0];\r
295 endcase\r
296 end\r
297 end\r
298end\r
299wire W_VOL1 = W_9L_Q[6];\r
300wire W_VOL2 = W_9L_Q[7];\r
301wire W_FIRE = W_9L_Q[5];\r
302wire W_HIT = W_9L_Q[3];\r
303wire W_FS3 = W_9L_Q[2];\r
304wire W_FS2 = W_9L_Q[1];\r
305wire W_FS1 = W_9L_Q[0];\r
306//---------------------------------------------------\r
307//---- CPU DATA WATCH -------------------------------\r
308wire ZMWR = W_CPU_MREQn | W_CPU_WRn ;\r
309\r
310reg [1:0]on_game;\r
311always @(posedge W_CPU_CLK)\r
312begin\r
313 if(~ZMWR)begin\r
314 if(W_A == 16'h4007)begin\r
315 if(W_BDI == 8'h00) \r
316 on_game[0] <= 1;\r
317 else\r
318 on_game[0] <= 0;\r
319 end\r
320 if(W_A == 16'h4005)begin\r
321 if(W_BDI == 8'h03 || W_BDI == 8'h04 ) \r
322 on_game[1] <= 1;\r
323 else\r
324 on_game[1] <= 0;\r
325 end\r
326 end \r
327end\r
328\r
329`ifdef PSPAD_USE\r
330reg died;\r
331always @(posedge W_CPU_CLK)\r
332begin\r
333 if(~ZMWR)begin\r
334 if(W_A == 16'h4206)begin\r
335 if(W_BDI == 8'h00) \r
336 died <= 0;\r
337 else\r
338 died <= 1;\r
339 end\r
340 end\r
341end\r
342//---- PS_PAD Interface -----------------------------\r
343wire [8:0]ps_PSW;\r
344wire VIB_SW = died & (&on_game[1:0]);\r
345\r
346fpga_arcade_if pspad(\r
347\r
348.CLK_18M432(I_CLK_18432M),\r
349.I_RSTn(W_RESETn),\r
350.psCLK(psCLK),\r
351.psSEL(psSEL),\r
352.psTXD(psTXD),\r
353.psRXD(psRXD),\r
354.ps_PSW(ps_PSW),\r
355.I_VIB_SW(VIB_SW)\r
356\r
357);\r
358`endif\r
359//---- SW Interface ---------------------------------\r
360`ifdef PSPAD_USE\r
361wire L1 = I_PSW[2] & ps_PSW[2];\r
362wire R1 = I_PSW[3] & ps_PSW[3];\r
363wire U1 = I_PSW[0];\r
364wire D1 = I_PSW[1];\r
365wire J1 = I_PSW[4] & ps_PSW[8];\r
366\r
367wire S1 = (U1|J1) & ps_PSW[6];\r
368wire S2 = (D1|J1) & ps_PSW[7];\r
369\r
370wire C1 = (L1|R1|U1|~D1) & ps_PSW[4];\r
371`else\r
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372wire L1 = ! I_PSW[2];\r
373wire R1 = ! I_PSW[3];\r
374wire U1 = ! I_PSW[0];\r
375wire D1 = ! I_PSW[1];\r
376wire J1 = ! I_PSW[4];\r
782690d0 377\r
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378wire S1 = ! I_PSW[5];\r
379wire S2 = ! I_PSW[7];\r
782690d0 380\r
3fc34adf 381wire C1 = ! I_PSW[6];\r
782690d0 382`endif\r
3fc34adf 383wire C2 = ! I_PSW[8];\r
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384\r
385wire L2 = L1;\r
386wire R2 = R1;\r
387wire U2 = U1;\r
388wire D2 = D1;\r
389wire J2 = J1;\r
390\r
391mc_inport MC_INPORT(\r
392\r
393.I_COIN1(~C1), // ACTIVE HI\r
394.I_COIN2(~C2), // ACTIVE HI\r
395.I_1P_LE(~L1), // ACTIVE HI\r
396.I_1P_RI(~R1), // ACTIVE HI\r
397.I_1P_SH(~J1), // ACTIVE HI\r
398.I_2P_LE(~L2), // ACTIVE HI\r
399.I_2P_RI(~R2), // ACTIVE HI\r
400.I_2P_SH(~J2), // ACTIVE HI\r
401.I_1P_START(~S1), // ACTIVE HI\r
402.I_2P_START(~S2), // ACTIVE HI\r
403\r
404.I_SW0_OEn(W_SW0_OEn),\r
405.I_SW1_OEn(W_SW1_OEn),\r
406.I_DIP_OEn(W_DIP_OEn),\r
407\r
408.O_D(W_SW_DO)\r
409\r
410);\r
411\r
412//-----------------------------------------------------------------------------\r
413//------- ROM -------------------------------------------------------\r
414reg [18:0]ROM_A;\r
415wire [10:0]W_OBJ_ROM_A;\r
416reg [7:0]W_OBJ_ROM_A_D;\r
417reg [7:0]W_OBJ_ROM_B_D;\r
418\r
419wire [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;\r
420reg [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;\r
421\r
422wire [7:0]ROM_D; // = I_ROM_DB;\r
423//assign O_ROM_AB = ROM_A;\r
424\r
425//assign O_ROM_OEn = 1'b0;\r
426//assign O_ROM_CSn = 1'b0;\r
427//assign O_ROM_WEn = 1'b1;\r
428\r
429galaxian_roms ROMS(\r
556154d1 430.I_ROM_CLK(W_ROM_CLK),\r
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431.I_ADDR(ROM_A),\r
432.O_DATA(ROM_D)\r
433);\r
434\r
435\r
436reg [1:0]clk_d;\r
437reg [4:0]seq;\r
438always @(posedge I_CLK_18432M)\r
439begin\r
440 // 24 phase generator\r
441 clk_d[0] <= W_H_CNT[0] & W_H_CNT[1] & W_H_CNT[2];\r
442 clk_d[1] <= clk_d[0];\r
443 seq <= (~clk_d[1] & clk_d[0]) ? 0 : seq+1;\r
444 case(seq)\r
445 0:begin\r
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446 ROM_A <= W_WAV_A0;\r
447 W_CPU_ROM_DO <= ROM_D;\r
448 end\r
449 2:begin\r
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450 ROM_A <= W_WAV_A1;\r
451 W_WAV_D0 <= ROM_D;\r
452 end\r
453 4:begin\r
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454 ROM_A <= {3'h0,W_A[15:0]};\r
455 W_WAV_D1 <= ROM_D;\r
456 end\r
457 6:begin\r
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458 ROM_A <= W_WAV_A2;\r
459 W_CPU_ROM_DO <= ROM_D;\r
460 end\r
3f141b41 461 8:W_WAV_D2 <= ROM_D;\r
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462 10:ROM_A <= {3'h0,W_A[15:0]};\r
463 12:W_CPU_ROM_DO <= ROM_D;\r
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464 14:ROM_A <= {3'h0,W_A[15:0]};\r
465 16:begin\r
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466 ROM_A <= {3'h0,4'h4,1'b0,W_OBJ_ROM_A};\r
467 W_CPU_ROM_DO <= ROM_D;\r
468 end\r
3f141b41 469 18:begin\r
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470 ROM_A <= {3'h0,4'h5,1'b0,W_OBJ_ROM_A};\r
471 W_OBJ_ROM_A_D <= ROM_D;\r
472 end\r
3f141b41 473 20:begin\r
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474 ROM_A <= {3'h0,W_A[15:0]};\r
475 W_OBJ_ROM_B_D <= ROM_D;\r
476 end\r
477 default:;\r
478 endcase\r
479end\r
480//-----------------------------------------------------------------------------\r
481\r
482wire W_V_BL2n;\r
483\r
484mc_hv_count MC_HV(\r
485\r
486.I_CLK(WB_CLK_6M),\r
487.I_RSTn(W_RESETn),\r
488\r
489.O_H_CNT(W_H_CNT),\r
490.O_H_SYNC(W_H_SYNC),\r
491.O_H_BL(W_H_BL),\r
492.O_V_CNT(W_V_CNT),\r
493.O_V_SYNC(W_V_SYNC),\r
494.O_V_BL2n(W_V_BL2n),\r
495.O_V_BLn(W_V_BLn),\r
496.O_C_BLn(W_C_BLn)\r
497\r
498);\r
499\r
500//------ VIDEO -----------------------------\r
501wire W_8HF;\r
502wire W_1VF;\r
503wire W_C_BLnX;\r
504wire W_256HnX;\r
505wire W_MISSILEn;\r
506wire W_SHELLn;\r
507wire [1:0]W_VID;\r
508wire [2:0]W_COL;\r
509\r
510mc_video MC_VID(\r
511.I_CLK_18M(I_CLK_18432M),\r
512.I_CLK_12M(W_CLK_12M),\r
513.I_CLK_6M(W_CLK_6M),\r
514.I_H_CNT(W_H_CNT),\r
515.I_V_CNT(W_V_CNT),\r
516.I_H_FLIP(W_H_FLIP),\r
517.I_V_FLIP(W_V_FLIP),\r
518.I_V_BLn(W_V_BLn),\r
519.I_C_BLn(W_C_BLn),\r
520\r
521.I_A(W_A[9:0]),\r
522.I_OBJ_SUB_A(3'b000),\r
523.I_BD(W_BDI),\r
524.I_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
525.I_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
526.I_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
527.I_VID_RAM_RDn(W_VID_RAM_RDn),\r
528.I_VID_RAM_WRn(W_VID_RAM_WRn),\r
529\r
530.O_OBJ_ROM_A(W_OBJ_ROM_A),\r
531.I_OBJ_ROM_A_D(W_OBJ_ROM_A_D),\r
532.I_OBJ_ROM_B_D(W_OBJ_ROM_B_D),\r
533\r
534.O_C_BLnX(W_C_BLnX),\r
535.O_8HF(W_8HF),\r
536.O_256HnX(W_256HnX),\r
537.O_1VF(W_1VF),\r
538.O_MISSILEn(W_MISSILEn),\r
539.O_SHELLn(W_SHELLn),\r
540.O_BD(W_VID_DO),\r
541.O_VID(W_VID),\r
542.O_COL(W_COL)\r
543\r
544);\r
545\r
546wire W_C_BLX;\r
547wire W_STARS_OFFn;\r
548wire [2:0]W_VIDEO_R;\r
549wire [2:0]W_VIDEO_G;\r
550wire [1:0]W_VIDEO_B;\r
551\r
552mc_col_pal MC_COL_PAL(\r
553\r
554.I_CLK_12M(W_CLK_12M),\r
555.I_CLK_6M(W_CLK_6M),\r
556.I_VID(W_VID),\r
557.I_COL(W_COL),\r
558.I_C_BLnX(W_C_BLnX),\r
559\r
560.O_C_BLX(W_C_BLX),\r
561.O_STARS_OFFn(W_STARS_OFFn),\r
562.O_R(W_VIDEO_R),\r
563.O_G(W_VIDEO_G),\r
564.O_B(W_VIDEO_B)\r
565\r
566);\r
567\r
568wire [2:0]W_STARS_R;\r
569wire [2:0]W_STARS_G;\r
570wire [1:0]W_STARS_B;\r
571\r
572mc_stars MC_STARS( \r
573\r
574.I_CLK_18M(I_CLK_18432M),\r
575`ifdef DEVICE_CYCLONE\r
576.I_CLK_6M(~WB_CLK_6M),\r
577`endif\r
578`ifdef DEVICE_SPARTAN2E \r
579.I_CLK_6M(WB_CLK_6M), \r
580`endif\r
581.I_H_FLIP(W_H_FLIP),\r
582.I_V_SYNC(W_V_SYNC),\r
583.I_8HF(W_8HF),\r
584.I_256HnX(W_256HnX),\r
585.I_1VF(W_1VF),\r
586.I_2V(W_V_CNT[1]),\r
587.I_STARS_ON(W_STARS_ON),\r
588.I_STARS_OFFn(W_STARS_OFFn),\r
589\r
590.O_R(W_STARS_R),\r
591.O_G(W_STARS_G),\r
592.O_B(W_STARS_B),\r
593.O_NOISE()\r
594\r
595);\r
596\r
597wire [2:0]W_R;\r
598wire [2:0]W_G;\r
599wire [1:0]W_B;\r
600\r
601mc_vedio_mix MIX(\r
602\r
603.I_VID_R(W_VIDEO_R),\r
604.I_VID_G(W_VIDEO_G),\r
605.I_VID_B(W_VIDEO_B),\r
606.I_STR_R(W_STARS_R),\r
607.I_STR_G(W_STARS_G),\r
608.I_STR_B(W_STARS_B),\r
609\r
610.I_C_BLnXX(~W_C_BLX),\r
611.I_C_BLX(W_C_BLX | ~W_V_BL2n),\r
612.I_MISSILEn(W_MISSILEn),\r
613.I_SHELLn(W_SHELLn),\r
614\r
615.O_R(W_R),\r
616.O_G(W_G),\r
617.O_B(W_B)\r
618\r
619);\r
620\r
491f582f
MG
621wire [2:0]W_VGA_R;\r
622wire [2:0]W_VGA_G;\r
623wire [1:0]W_VGA_B;\r
624\r
782690d0
MG
625`ifdef VGA_USE\r
626mc_vga_if VGA(\r
627\r
628// input\r
629.I_CLK_1(W_CLK_6M),\r
630.I_CLK_2(W_CLK_12M),\r
631.I_R(W_R),\r
632.I_G(W_G),\r
633.I_B(W_B),\r
634.I_H_SYNC(W_H_SYNC),\r
635.I_V_SYNC(W_V_SYNC),\r
636// output\r
491f582f
MG
637.O_R(W_VGA_R),\r
638.O_G(W_VGA_G),\r
639.O_B(W_VGA_B),\r
782690d0
MG
640.O_H_SYNCn(O_VGA_H_SYNCn),\r
641.O_V_SYNCn(O_VGA_V_SYNCn)\r
642\r
643);\r
644\r
645`else\r
646\r
491f582f 647assign W_VGA_R[2:0] = W_R;\r
782690d0 648\r
491f582f 649assign W_VGA_G[2:0] = W_G;\r
782690d0 650\r
491f582f 651assign W_VGA_B[1:0] = W_B;\r
782690d0
MG
652\r
653//assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ; // AKIDUKI LCD USED\r
654assign O_VGA_H_SYNCn = ~W_H_SYNC ;\r
655assign O_VGA_V_SYNCn = ~W_V_SYNC ;\r
656\r
657`endif\r
658\r
e780c439 659assign O_VGA_R[3:0] = {W_VGA_R[0], W_VGA_R[1], W_VGA_R[2], 1'b0};\r
491f582f 660\r
e780c439 661assign O_VGA_G[3:0] = {W_VGA_G[0], W_VGA_G[1], W_VGA_G[2], 1'b0};\r
491f582f 662\r
e780c439 663assign O_VGA_B[3:0] = {W_VGA_B[0], W_VGA_B[1], 2'b0};\r
491f582f 664\r
782690d0
MG
665wire [7:0]W_SDAT_A;\r
666\r
667mc_sound_a MC_SOUND_A(\r
668\r
669.I_CLK_12M(W_CLK_12M),\r
670.I_CLK_6M(W_CLK_6M),\r
671.I_H_CNT1(W_H_CNT[1]),\r
672.I_BD(W_BDI),\r
673.I_PITCHn(W_PITCHn),\r
674.I_VOL1(W_VOL1),\r
675.I_VOL2(W_VOL2),\r
676\r
677.O_SDAT(W_SDAT_A),\r
678.O_DO()\r
679\r
680);\r
681\r
682wire [7:0]W_SDAT_B;\r
683\r
684mc_sound_b MC_SOUND_B(\r
685\r
686.I_CLK1(I_CLK_18432M),\r
687.I_CLK2(W_CLK_6M),\r
688.I_RSTn(rst_count[3]),\r
689.I_SW({&on_game[1:0],W_HIT,W_FIRE}),\r
690\r
691.O_WAV_A0(W_WAV_A0),\r
692.O_WAV_A1(W_WAV_A1),\r
693.O_WAV_A2(W_WAV_A2),\r
694.I_WAV_D0(W_WAV_D0),\r
695.I_WAV_D1(W_WAV_D1),\r
696.I_WAV_D2(W_WAV_D2),\r
697\r
698.O_SDAT(W_SDAT_B)\r
699\r
700);\r
701\r
702wire W_DAC_A;\r
703wire W_DAC_B;\r
704\r
705assign O_SOUND_OUT_L = W_DAC_A;\r
706assign O_SOUND_OUT_R = W_DAC_B;\r
707\r
708dac wav_dac_a(\r
709\r
710.Clk(I_CLK_18432M), \r
711.Reset(~W_RESETn),\r
712.DACin(W_SDAT_A),\r
713.DACout(W_DAC_A)\r
714\r
715);\r
716\r
717dac wav_dac_b(\r
718\r
719.Clk(I_CLK_18432M), \r
720.Reset(~W_RESETn),\r
721.DACin(W_SDAT_B),\r
722.DACout(W_DAC_B)\r
723\r
724);\r
725\r
726\r
727endmodule\r
728\r
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