don't modify data bus when accessing unknown address

[fpga-games] / galaxian / src / dac.v

//\r
// XAPP154 based SigmaDeltaPCM Module\r
//\r
// Important !\r
//\r
// This program is freeware for non-commercial use. \r
// An author does no guarantee about this program.\r
// You can use this under your own risk. \r
//\r
// See the xapp154.pdf on Xilinx application note.\r
//\r
//\r
\r
`timescale 100 ps / 10 ps\r
`define MSBI 7 // Most significant Bit of DAC input\r
//This is a Delta-Sigma Digital to Analog Converter\r
\r
module dac(DACout, DACin, Clk, Reset);\r
output DACout; // This is the average output that feeds low pass filter\r
reg DACout; // for optimum performance, ensure that this ff is in IOB\r
input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)\r
input Clk;\r
input Reset;\r
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder\r
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder\r
reg [`MSBI+2:0] SigmaLatch; // Latches output of Sigma adder\r
reg [`MSBI+2:0] DeltaB; // B input of Delta adder\r
\r
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);\r
\r
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;\r
\r
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;\r
\r
always @(posedge Clk or posedge Reset)\r
begin\r
	if(Reset)\r
	begin\r
		SigmaLatch <= #1 1'b1 << (`MSBI+1);\r
		DACout <= #1 1'b0;\r
	end\r
	else\r
	begin\r
//		SigmaLatch <== #1 SigmaAdder;\r
		SigmaLatch <= #1 SigmaAdder;\r
		DACout <= #1  SigmaLatch[`MSBI+2];\r
	end\r
end\r
endmodule\r
\r