don't modify data bus when accessing unknown address
[fpga-games] / galaxian / src / roms.v
CommitLineData
782690d0 1module galaxian_roms(
37f1bdd7 2I_CLK_18432M,
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3I_CLK_12M,
4I_ADDR,
5O_DATA
6);
7
37f1bdd7 8input I_CLK_18432M;
782690d0 9input I_CLK_12M;
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10input [18:0]I_ADDR;
11output [7:0]O_DATA;
12
13//CPU-Roms
14wire [7:0]U_ROM_D;
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15
16GALAXIAN_U U_ROM(
17.CLK(I_CLK_12M),
b884ab49 18.ADDR(I_ADDR[10:0]),
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19.DATA(U_ROM_D),
20.ENA(1'b1)
21);
22
23wire [7:0]V_ROM_D;
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24
25GALAXIAN_V V_ROM(
26.CLK(I_CLK_12M),
b884ab49 27.ADDR(I_ADDR[10:0]),
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28.DATA(V_ROM_D),
29.ENA(1'b1)
30);
31
32wire [7:0]W_ROM_D;
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33
34GALAXIAN_W W_ROM(
35.CLK(I_CLK_12M),
b884ab49 36.ADDR(I_ADDR[10:0]),
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37.DATA(W_ROM_D),
38.ENA(1'b1)
39);
40
41wire [7:0]Y_ROM_D;
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42
43GALAXIAN_Y Y_ROM(
ead9ca4c 44.CLK(I_CLK_12M),
b884ab49 45.ADDR(I_ADDR[10:0]),
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46.DATA(Y_ROM_D),
47.ENA(1'b1)
48);
49
50//7L CPU-Rom
51wire [7:0]L_ROM_D;
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52
53GALAXIAN_7L L_ROM(
ead9ca4c 54.CLK(I_CLK_12M),
b884ab49 55.ADDR(I_ADDR[10:0]),
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56.DATA(L_ROM_D),
57.ENA(1'b1)
58);
59
60//1K VID-Rom
61wire [7:0]K_ROM_D;
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62
63GALAXIAN_1K K_ROM(
ead9ca4c 64.CLK(I_CLK_12M),
b884ab49 65.ADDR(I_ADDR[10:0]),
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66.DATA(K_ROM_D),
67.ENA(1'b1)
68);
69
70//1H VID-Rom
71wire [7:0]H_ROM_D;
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72
73GALAXIAN_1H H_ROM(
ead9ca4c 74.CLK(I_CLK_12M),
b884ab49 75.ADDR(I_ADDR[10:0]),
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76.DATA(H_ROM_D),
77.ENA(1'b1)
78);
79
80reg [7:0]DATA_OUT;
37f1bdd7 81reg [7:0]DATA_OUT2;
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82
83// address map
84//--------------------------------------------------
85// 0x00000 - 0x007FF galmidw.u CPU-ROM
86// 0x00800 - 0x00FFF galmidw.v CPU-ROM
87// 0x01000 - 0x017FF galmidw.w CPU-ROM
88// 0x01800 - 0x01FFF galmidw.y CPU-ROM
89// 0x02000 - 0x027FF 7l CPU-ROM
90// 0x04000 - 0x047FF 1k.bin VID-ROM
91// 0x05000 - 0x057FF 1h.bin VID-ROM
92// 0x10000 - 0x3FFFF mc_wav_2.bin Sound(Wav)Data
b884ab49 93always@(I_ADDR or U_ROM_D or V_ROM_D or W_ROM_D or Y_ROM_D or L_ROM_D or K_ROM_D or H_ROM_D)
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94begin
95 if (I_ADDR <= 18'h7ff) begin
96 //u
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97 DATA_OUT <= U_ROM_D;
98 end
b884ab49 99 else if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
782690d0 100 //v
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101 DATA_OUT <= V_ROM_D;
102 end
b884ab49 103 else if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
782690d0 104 //w
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105 DATA_OUT <= W_ROM_D;
106 end
b884ab49 107 else if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
782690d0 108 //y
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109 DATA_OUT <= Y_ROM_D;
110 end
b884ab49 111 else if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
782690d0 112 //7l
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113 DATA_OUT <= L_ROM_D;
114 end
b884ab49 115 else if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
782690d0 116 //1k
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117 DATA_OUT <= K_ROM_D;
118 end
b884ab49 119 else if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
782690d0 120 //1h
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121 DATA_OUT <= H_ROM_D;
122 end
b884ab49 123 else if (I_ADDR >= 18'h10000 && I_ADDR <= 18'h3fff) begin
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124 //sound
125 DATA_OUT <= 8'h00;
126 end
b884ab49 127 else begin
475bf7e7 128 DATA_OUT <= DATA_OUT;
b884ab49 129 end
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130end
131
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132always@(negedge I_CLK_18432M)
133begin
134 DATA_OUT2 <= DATA_OUT;
135end
136
137assign O_DATA = DATA_OUT2;
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138
139endmodule
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