don't modify data bus when accessing unknown address

[fpga-games] / galaxian / src / t80as.v

//\r
// Daniel Wallner's T80 header file for verilog\r
//\r
// Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved\r
//\r
// Important !\r
//\r
// This program is freeware for non-commercial use. \r
// An author does no guarantee about this program.\r
// You can use this under your own risk. \r
//\r
//\r
module T80as(\r
	RESET_n,CLK_n,WAIT_n,INT_n,NMI_n,BUSRQ_n,\r
	M1_n,MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,HALT_n,BUSAK_n,\r
	A,DI,DO,DOE);\r
\r
input RESET_n,CLK_n,WAIT_n,INT_n,NMI_n,BUSRQ_n;\r
output M1_n,MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,HALT_n,BUSAK_n;\r
output [15:0] A;\r
input [7:0] DI;\r
output [7:0] DO;\r
output DOE;\r
\r
endmodule\r