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782690d0 MG |
1 | //---------------------------------------------------------------------\r |
2 | // FPGA MOONCRESTA CLOCK GEN \r | |
3 | //\r | |
4 | // Version : 1.00\r | |
5 | //\r | |
6 | // Copyright(c) 2004 Katsumi Degawa , All rights reserved\r | |
7 | //\r | |
8 | // Important !\r | |
9 | //\r | |
10 | // This program is freeware for non-commercial use. \r | |
11 | // An author does no guarantee about this program.\r | |
12 | // You can use this under your own risk.\r | |
13 | //\r | |
14 | //---------------------------------------------------------------------\r | |
15 | \r | |
16 | \r | |
17 | \r | |
18 | module mc_clock(\r | |
19 | \r | |
c3bcc38a MG |
20 | I_CLK_36M,\r |
21 | O_CLK_18M,\r | |
782690d0 | 22 | O_CLK_12M,\r |
4b3ff7d8 MG |
23 | O_CLK_06M,\r |
24 | O_CLK_06Mn\r | |
782690d0 MG |
25 | \r |
26 | );\r | |
27 | \r | |
c3bcc38a MG |
28 | input I_CLK_36M;\r |
29 | output O_CLK_18M;\r | |
782690d0 MG |
30 | output O_CLK_12M;\r |
31 | output O_CLK_06M;\r | |
4b3ff7d8 | 32 | output O_CLK_06Mn;\r |
782690d0 MG |
33 | \r |
34 | // 2/3 clock divider(duty 33%)\r | |
782690d0 MG |
35 | //I_CLK 1010101010101010101\r |
36 | //c_ff10 0011110011110011110\r | |
37 | //c_ff11 0011000011000011000\r | |
38 | //c_ff20 0000110000110000110\r | |
39 | //c_ff21 0110000110000110000\r | |
40 | //O_12M 0000110110110110110\r | |
c3bcc38a MG |
41 | reg [1:0] state;\r |
42 | reg clk_12m;\r | |
43 | initial state = 0;\r | |
44 | initial clk_12m = 0;\r | |
45 | \r | |
46 | // 2/3 clock (duty 66%)\r | |
0a770302 | 47 | always @(posedge I_CLK_36M)\r |
782690d0 | 48 | begin\r |
c3bcc38a MG |
49 | case (state)\r |
50 | 2'd0: state <= 2'd1;\r | |
51 | 2'd1: state <= 2'd2;\r | |
52 | 2'd2: state <= 2'd0;\r | |
53 | 2'd3: state <= 2'd0;\r | |
54 | endcase\r | |
55 | \r | |
56 | if (state == 2'd2)\r | |
c3bcc38a | 57 | clk_12m = 0;\r |
0a770302 MG |
58 | else\r |
59 | clk_12m = 1;\r | |
782690d0 | 60 | end\r |
782690d0 | 61 | \r |
c3bcc38a MG |
62 | assign O_CLK_12M = clk_12m;\r |
63 | \r | |
64 | reg CLK_18M;\r | |
65 | always @(posedge I_CLK_36M)\r | |
66 | begin\r | |
67 | CLK_18M <= ~ CLK_18M;\r | |
68 | end\r | |
69 | assign O_CLK_18M = CLK_18M;\r | |
70 | \r | |
782690d0 | 71 | // 1/3 clock divider (duty 50%)\r |
c3bcc38a | 72 | reg CLK_6M;\r |
4b3ff7d8 MG |
73 | reg CLK_6Mn;\r |
74 | \r | |
782690d0 MG |
75 | always @(posedge O_CLK_12M)\r |
76 | begin\r | |
782690d0 | 77 | CLK_6M <= ~CLK_6M;\r |
4b3ff7d8 | 78 | CLK_6Mn <= CLK_6M;\r |
782690d0 | 79 | end\r |
4b3ff7d8 | 80 | \r |
782690d0 | 81 | assign O_CLK_06M = CLK_6M;\r |
4b3ff7d8 | 82 | assign O_CLK_06Mn = CLK_6Mn;\r |
782690d0 | 83 | \r |
c3bcc38a | 84 | endmodule\r |