fix clock for LRAM
[fpga-games] / galaxian / src / mc_top.v
CommitLineData
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1//===============================================================================\r
2// FPGA GALAXIAN TOP\r
3//\r
4// Version : 2.50\r
5//\r
6// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// Important !\r
9//\r
10// This program is freeware for non-commercial use. \r
11// An author does no guarantee about this program.\r
12// You can use this under your own risk.\r
13//\r
14// 2004- 4-30 galaxian modify by K.DEGAWA\r
15// 2004- 5- 6 first release.\r
16// 2004- 8-23 Improvement with T80-IP.\r
17// 2004- 9-18 The description of ALTERA(CYCLONE) and XILINX(SPARTAN2E) was made one.\r
18// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
19//================================================================================\r
20\r
21`include "src/mc_conf.v" \r
22 \r
23module mc_top(\r
24\r
25// FPGA_USE\r
26I_CLK_125M,\r
27\r
28`ifdef PSPAD_USE\r
29// PS_PAD interface\r
30psCLK,\r
31psSEL,\r
32psTXD,\r
33psRXD,\r
34`endif\r
35\r
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36// INPORT SW IF\r
37I_PSW,\r
38\r
39// SOUND OUT\r
40O_SOUND_OUT_L,\r
41O_SOUND_OUT_R,\r
42\r
43// VGA (VIDEO) IF\r
44O_VGA_R,\r
45O_VGA_G,\r
46O_VGA_B,\r
47O_VGA_H_SYNCn,\r
48O_VGA_V_SYNCn\r
49\r
50);\r
51\r
52// FPGA_USE\r
53input I_CLK_125M;\r
54\r
55// CPU ADDRESS BUS\r
56wire [15:0]W_A;\r
57// CPU IF\r
58wire W_CPU_RDn;\r
59wire W_CPU_WRn;\r
60wire W_CPU_MREQn;\r
61wire W_CPU_RFSHn;\r
62wire W_CPU_BUSAKn;\r
63wire W_CPU_IORQn;\r
64wire W_CPU_M1n;\r
65wire W_CPU_CLK;\r
66wire W_CPU_HRDWR_RESETn;\r
67wire W_CPU_WAITn;\r
68wire W_CPU_NMIn;\r
69\r
70`ifdef PSPAD_USE\r
71// PS_PAD interface\r
72input psRXD;\r
73output psTXD,psCLK,psSEL;\r
74`endif\r
75\r
782690d0 76// INPORT SW IF\r
3fc34adf 77input [8:0]I_PSW;\r
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78\r
79// SOUND OUT \r
80output O_SOUND_OUT_L;\r
81output O_SOUND_OUT_R;\r
82\r
83// VGA (VIDEO) IF\r
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84output [3:0]O_VGA_R;\r
85output [3:0]O_VGA_G;\r
86output [3:0]O_VGA_B;\r
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87output O_VGA_H_SYNCn;\r
88output O_VGA_V_SYNCn;\r
89\r
3fc34adf 90wire W_RESETn = |(~I_PSW[8:5]);\r
782690d0 91//------ CLOCK GEN ---------------------------\r
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92wire W_CLK_18M;\r
93wire W_CLK_36M;\r
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94wire W_CLK_12M,WB_CLK_12M;\r
95wire W_CLK_6M,WB_CLK_6M;\r
4b3ff7d8 96wire W_CLK_6Mn;\r
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97wire W_STARS_CLK;\r
98\r
b884ab49 99mc_dcm clockgen(\r
782690d0 100.CLKIN_IN(I_CLK_125M),\r
fc28fcbf 101.RST_IN(! W_RESETn),\r
c3bcc38a 102.CLKFX_OUT(W_CLK_36M)\r
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103);\r
104\r
105//------ H&V COUNTER -------------------------\r
106wire [8:0]W_H_CNT;\r
107wire [7:0]W_V_CNT;\r
108wire W_H_BL;\r
109wire W_V_BLn;\r
110wire W_C_BLn;\r
111wire W_H_SYNC;\r
112wire W_V_SYNC;\r
113\r
114//------ CPU RAM ----------------------------\r
115wire [7:0]W_CPU_RAM_DO;\r
116\r
117//------ ADDRESS DECDER ----------------------\r
118wire W_CPU_ROM_CSn;\r
119wire W_CPU_RAM_RDn;\r
120wire W_CPU_RAM_WRn;\r
121wire W_CPU_RAM_CSn;\r
122wire W_OBJ_RAM_RDn;\r
123wire W_OBJ_RAM_WRn;\r
124wire W_OBJ_RAM_RQn;\r
125wire W_VID_RAM_RDn;\r
126wire W_VID_RAM_WRn;\r
127wire W_SW0_OEn;\r
128wire W_SW1_OEn;\r
129wire W_DIP_OEn;\r
130wire W_WDR_OEn;\r
131wire W_LAMP_WEn;\r
132wire W_SOUND_WEn;\r
133wire W_PITCHn;\r
134wire W_H_FLIP;\r
135wire W_V_FLIP;\r
136wire W_BD_G;\r
137wire W_STARS_ON;\r
138\r
139wire W_VID_RDn = W_OBJ_RAM_RDn & W_VID_RAM_RDn ;\r
140wire W_SW_OEn = W_SW0_OEn & W_SW1_OEn & W_DIP_OEn ;\r
141//------- INPORT -----------------------------\r
142wire [7:0]W_SW_DO;\r
143//------- VIDEO -----------------------------\r
144wire [7:0]W_VID_DO;\r
145//--------------------------------------------\r
146\r
147mc_clock MC_CLK(\r
148\r
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149.I_CLK_36M(W_CLK_36M),\r
150.O_CLK_18M(W_CLK_18M),\r
782690d0 151.O_CLK_12M(WB_CLK_12M),\r
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152.O_CLK_06M(WB_CLK_6M),\r
153.O_CLK_06Mn(W_CLK_6Mn)\r
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154\r
155);\r
156\r
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157assign W_CLK_12M = WB_CLK_12M;\r
158assign W_CLK_6M = WB_CLK_6M;\r
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159//--- DATA I/F -------------------------------------\r
160reg [7:0]W_CPU_ROM_DO;\r
161wire [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;\r
162\r
163wire [7:0]W_BDO = W_SW_DO | W_VID_DO | W_CPU_RAM_DO | W_CPU_ROM_DOB ;\r
164wire [7:0]W_BDI;\r
165\r
166//--- CPU I/F -------------------------------------\r
167reg [3:0]rst_count;\r
168always@(posedge W_H_CNT[0] or negedge W_RESETn)\r
169begin\r
170 if(! W_RESETn) rst_count <= 0;\r
171 else begin\r
172 if( rst_count == 15) \r
173 rst_count <= rst_count;\r
174 else\r
175 rst_count <= rst_count+1;\r
176 end\r
177end\r
178\r
179assign W_CPU_RESETn = W_RESETn;\r
180assign W_CPU_CLK = W_H_CNT[0];\r
181\r
182Z80IP CPU(\r
183 \r
184.CLK(W_CPU_CLK),\r
185.RESET_N(W_CPU_RESETn),\r
186.INT_N(1'b1),\r
187.NMI_N(W_CPU_NMIn),\r
188.ADRS(W_A),\r
189.DOUT(W_BDI),\r
190.DINP(W_BDO),\r
191.M1_N(),\r
192.MREQ_N(W_CPU_MREQn),\r
193.IORQ_N(),\r
194.RD_N(W_CPU_RDn ),\r
195.WR_N(W_CPU_WRn ),\r
196.WAIT_N(W_CPU_WAITn),\r
197.BUSWO(),\r
198.RFSH_N(W_CPU_RFSHn),\r
199.HALT_N()\r
200\r
201);\r
202\r
203wire W_CPU_RAM_CLK = W_CLK_12M & ~W_CPU_RAM_CSn;\r
204\r
205mc_cpu_ram MC_CPU_RAM(\r
206\r
207.I_CLK(W_CPU_RAM_CLK),\r
208.I_ADDR(W_A[9:0]),\r
209.I_D(W_BDI),\r
210.I_WE(~W_CPU_WRn),\r
211.I_OE(~W_CPU_RAM_RDn ),\r
212.O_D(W_CPU_RAM_DO)\r
213\r
214);\r
215\r
216\r
217mc_adec MC_ADEC(\r
218\r
219.I_CLK_12M(W_CLK_12M),\r
220.I_CLK_6M(W_CLK_6M),\r
221.I_CPU_CLK(W_H_CNT[0]),\r
222.I_RSTn(W_RESETn),\r
223\r
224.I_CPU_A(W_A),\r
225.I_CPU_D(W_BDI[0]),\r
226.I_MREQn(W_CPU_MREQn),\r
227.I_RFSHn(W_CPU_RFSHn),\r
228.I_RDn(W_CPU_RDn),\r
229.I_WRn(W_CPU_WRn),\r
230.I_H_BL(W_H_BL),\r
231.I_V_BLn(W_V_BLn),\r
232\r
233.O_WAITn(W_CPU_WAITn),\r
234.O_NMIn(W_CPU_NMIn),\r
235.O_CPU_ROM_CSn(W_CPU_ROM_CSn),\r
236.O_CPU_RAM_RDn(W_CPU_RAM_RDn),\r
237.O_CPU_RAM_WRn(W_CPU_RAM_WRn),\r
238.O_CPU_RAM_CSn(W_CPU_RAM_CSn),\r
239.O_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
240.O_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
241.O_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
242.O_VID_RAM_RDn(W_VID_RAM_RDn),\r
243.O_VID_RAM_WRn(W_VID_RAM_WRn),\r
244.O_SW0_OEn(W_SW0_OEn),\r
245.O_SW1_OEn(W_SW1_OEn),\r
246.O_DIP_OEn(W_DIP_OEn),\r
247.O_WDR_OEn(W_WDR_OEn),\r
248.O_LAMP_WEn(W_LAMP_WEn),\r
249.O_SOUND_WEn(W_SOUND_WEn),\r
250.O_PITCHn(W_PITCHn),\r
251.O_H_FLIP(W_H_FLIP),\r
252.O_V_FLIP(W_V_FLIP),\r
253.O_BD_G(W_BD_G),\r
254.O_STARS_ON(W_STARS_ON)\r
255\r
256);\r
257\r
258//-------- SOUND I/F -----------------------------\r
259//--- Parts 9L ---------\r
260reg [7:0]W_9L_Q;\r
261always@(posedge W_CLK_12M or negedge W_RESETn)\r
262begin\r
263 if(W_RESETn == 1'b0)begin\r
264 W_9L_Q <= 0;\r
265 end \r
266 else begin\r
267 if(W_SOUND_WEn == 1'b0)begin\r
268 case(W_A[2:0])\r
269 3'h0 : W_9L_Q[0] <= W_BDI[0];\r
270 3'h1 : W_9L_Q[1] <= W_BDI[0];\r
271 3'h2 : W_9L_Q[2] <= W_BDI[0];\r
272 3'h3 : W_9L_Q[3] <= W_BDI[0];\r
273 3'h4 : W_9L_Q[4] <= W_BDI[0];\r
274 3'h5 : W_9L_Q[5] <= W_BDI[0];\r
275 3'h6 : W_9L_Q[6] <= W_BDI[0];\r
276 3'h7 : W_9L_Q[7] <= W_BDI[0];\r
277 endcase\r
278 end\r
279 end\r
280end\r
281wire W_VOL1 = W_9L_Q[6];\r
282wire W_VOL2 = W_9L_Q[7];\r
283wire W_FIRE = W_9L_Q[5];\r
284wire W_HIT = W_9L_Q[3];\r
285wire W_FS3 = W_9L_Q[2];\r
286wire W_FS2 = W_9L_Q[1];\r
287wire W_FS1 = W_9L_Q[0];\r
288//---------------------------------------------------\r
289//---- CPU DATA WATCH -------------------------------\r
290wire ZMWR = W_CPU_MREQn | W_CPU_WRn ;\r
291\r
292reg [1:0]on_game;\r
293always @(posedge W_CPU_CLK)\r
294begin\r
295 if(~ZMWR)begin\r
296 if(W_A == 16'h4007)begin\r
297 if(W_BDI == 8'h00) \r
298 on_game[0] <= 1;\r
299 else\r
300 on_game[0] <= 0;\r
301 end\r
302 if(W_A == 16'h4005)begin\r
303 if(W_BDI == 8'h03 || W_BDI == 8'h04 ) \r
304 on_game[1] <= 1;\r
305 else\r
306 on_game[1] <= 0;\r
307 end\r
308 end \r
309end\r
310\r
311`ifdef PSPAD_USE\r
312reg died;\r
313always @(posedge W_CPU_CLK)\r
314begin\r
315 if(~ZMWR)begin\r
316 if(W_A == 16'h4206)begin\r
317 if(W_BDI == 8'h00) \r
318 died <= 0;\r
319 else\r
320 died <= 1;\r
321 end\r
322 end\r
323end\r
324//---- PS_PAD Interface -----------------------------\r
325wire [8:0]ps_PSW;\r
326wire VIB_SW = died & (&on_game[1:0]);\r
327\r
328fpga_arcade_if pspad(\r
329\r
c3bcc38a 330.CLK_18M432(W_CLK_18M),\r
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331.I_RSTn(W_RESETn),\r
332.psCLK(psCLK),\r
333.psSEL(psSEL),\r
334.psTXD(psTXD),\r
335.psRXD(psRXD),\r
336.ps_PSW(ps_PSW),\r
337.I_VIB_SW(VIB_SW)\r
338\r
339);\r
340`endif\r
341//---- SW Interface ---------------------------------\r
342`ifdef PSPAD_USE\r
343wire L1 = I_PSW[2] & ps_PSW[2];\r
344wire R1 = I_PSW[3] & ps_PSW[3];\r
345wire U1 = I_PSW[0];\r
346wire D1 = I_PSW[1];\r
347wire J1 = I_PSW[4] & ps_PSW[8];\r
348\r
349wire S1 = (U1|J1) & ps_PSW[6];\r
350wire S2 = (D1|J1) & ps_PSW[7];\r
351\r
352wire C1 = (L1|R1|U1|~D1) & ps_PSW[4];\r
353`else\r
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354wire L1 = ! I_PSW[2];\r
355wire R1 = ! I_PSW[3];\r
356wire U1 = ! I_PSW[0];\r
357wire D1 = ! I_PSW[1];\r
358wire J1 = ! I_PSW[4];\r
782690d0 359\r
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360wire S1 = ! I_PSW[5];\r
361wire S2 = ! I_PSW[7];\r
782690d0 362\r
3fc34adf 363wire C1 = ! I_PSW[6];\r
782690d0 364`endif\r
3fc34adf 365wire C2 = ! I_PSW[8];\r
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366\r
367wire L2 = L1;\r
368wire R2 = R1;\r
369wire U2 = U1;\r
370wire D2 = D1;\r
371wire J2 = J1;\r
372\r
373mc_inport MC_INPORT(\r
374\r
375.I_COIN1(~C1), // ACTIVE HI\r
376.I_COIN2(~C2), // ACTIVE HI\r
377.I_1P_LE(~L1), // ACTIVE HI\r
378.I_1P_RI(~R1), // ACTIVE HI\r
379.I_1P_SH(~J1), // ACTIVE HI\r
380.I_2P_LE(~L2), // ACTIVE HI\r
381.I_2P_RI(~R2), // ACTIVE HI\r
382.I_2P_SH(~J2), // ACTIVE HI\r
383.I_1P_START(~S1), // ACTIVE HI\r
384.I_2P_START(~S2), // ACTIVE HI\r
385\r
386.I_SW0_OEn(W_SW0_OEn),\r
387.I_SW1_OEn(W_SW1_OEn),\r
388.I_DIP_OEn(W_DIP_OEn),\r
389\r
390.O_D(W_SW_DO)\r
391\r
392);\r
393\r
394//-----------------------------------------------------------------------------\r
395//------- ROM -------------------------------------------------------\r
396reg [18:0]ROM_A;\r
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397\r
398wire [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;\r
399reg [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;\r
400\r
36a47d3c 401wire [7:0]ROM_D;\r
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402\r
403galaxian_roms ROMS(\r
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404.I_ROM_CLK(W_CLK_12M),\r
405.I_ADDR({3'h0,W_A[15:0]}),\r
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406.O_DATA(ROM_D)\r
407);\r
408\r
36a47d3c 409always@(posedge W_CLK_12M)\r
782690d0 410begin\r
36a47d3c 411 W_CPU_ROM_DO <= ROM_D;\r
782690d0 412end\r
36a47d3c 413\r
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414//-----------------------------------------------------------------------------\r
415\r
416wire W_V_BL2n;\r
417\r
418mc_hv_count MC_HV(\r
419\r
420.I_CLK(WB_CLK_6M),\r
421.I_RSTn(W_RESETn),\r
422\r
423.O_H_CNT(W_H_CNT),\r
424.O_H_SYNC(W_H_SYNC),\r
425.O_H_BL(W_H_BL),\r
426.O_V_CNT(W_V_CNT),\r
427.O_V_SYNC(W_V_SYNC),\r
428.O_V_BL2n(W_V_BL2n),\r
429.O_V_BLn(W_V_BLn),\r
430.O_C_BLn(W_C_BLn)\r
431\r
432);\r
433\r
434//------ VIDEO -----------------------------\r
435wire W_8HF;\r
436wire W_1VF;\r
437wire W_C_BLnX;\r
438wire W_256HnX;\r
439wire W_MISSILEn;\r
440wire W_SHELLn;\r
441wire [1:0]W_VID;\r
442wire [2:0]W_COL;\r
443\r
444mc_video MC_VID(\r
c3bcc38a 445.I_CLK_18M(W_CLK_18M),\r
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446.I_CLK_12M(W_CLK_12M),\r
447.I_CLK_6M(W_CLK_6M),\r
4b3ff7d8 448.I_CLK_6Mn(W_CLK_6Mn),\r
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449.I_H_CNT(W_H_CNT),\r
450.I_V_CNT(W_V_CNT),\r
451.I_H_FLIP(W_H_FLIP),\r
452.I_V_FLIP(W_V_FLIP),\r
453.I_V_BLn(W_V_BLn),\r
454.I_C_BLn(W_C_BLn),\r
455\r
456.I_A(W_A[9:0]),\r
457.I_OBJ_SUB_A(3'b000),\r
458.I_BD(W_BDI),\r
459.I_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
460.I_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
461.I_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
462.I_VID_RAM_RDn(W_VID_RAM_RDn),\r
463.I_VID_RAM_WRn(W_VID_RAM_WRn),\r
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464\r
465.O_C_BLnX(W_C_BLnX),\r
466.O_8HF(W_8HF),\r
467.O_256HnX(W_256HnX),\r
468.O_1VF(W_1VF),\r
469.O_MISSILEn(W_MISSILEn),\r
470.O_SHELLn(W_SHELLn),\r
471.O_BD(W_VID_DO),\r
472.O_VID(W_VID),\r
473.O_COL(W_COL)\r
474\r
475);\r
476\r
477wire W_C_BLX;\r
478wire W_STARS_OFFn;\r
479wire [2:0]W_VIDEO_R;\r
480wire [2:0]W_VIDEO_G;\r
481wire [1:0]W_VIDEO_B;\r
482\r
483mc_col_pal MC_COL_PAL(\r
484\r
485.I_CLK_12M(W_CLK_12M),\r
486.I_CLK_6M(W_CLK_6M),\r
487.I_VID(W_VID),\r
488.I_COL(W_COL),\r
489.I_C_BLnX(W_C_BLnX),\r
490\r
491.O_C_BLX(W_C_BLX),\r
492.O_STARS_OFFn(W_STARS_OFFn),\r
493.O_R(W_VIDEO_R),\r
494.O_G(W_VIDEO_G),\r
495.O_B(W_VIDEO_B)\r
496\r
497);\r
498\r
499wire [2:0]W_STARS_R;\r
500wire [2:0]W_STARS_G;\r
501wire [1:0]W_STARS_B;\r
502\r
503mc_stars MC_STARS( \r
504\r
c3bcc38a 505.I_CLK_18M(W_CLK_18M),\r
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506`ifdef DEVICE_CYCLONE\r
507.I_CLK_6M(~WB_CLK_6M),\r
508`endif\r
509`ifdef DEVICE_SPARTAN2E \r
510.I_CLK_6M(WB_CLK_6M), \r
511`endif\r
512.I_H_FLIP(W_H_FLIP),\r
513.I_V_SYNC(W_V_SYNC),\r
514.I_8HF(W_8HF),\r
515.I_256HnX(W_256HnX),\r
516.I_1VF(W_1VF),\r
517.I_2V(W_V_CNT[1]),\r
518.I_STARS_ON(W_STARS_ON),\r
519.I_STARS_OFFn(W_STARS_OFFn),\r
520\r
521.O_R(W_STARS_R),\r
522.O_G(W_STARS_G),\r
523.O_B(W_STARS_B),\r
524.O_NOISE()\r
525\r
526);\r
527\r
528wire [2:0]W_R;\r
529wire [2:0]W_G;\r
530wire [1:0]W_B;\r
531\r
532mc_vedio_mix MIX(\r
533\r
534.I_VID_R(W_VIDEO_R),\r
535.I_VID_G(W_VIDEO_G),\r
536.I_VID_B(W_VIDEO_B),\r
537.I_STR_R(W_STARS_R),\r
538.I_STR_G(W_STARS_G),\r
539.I_STR_B(W_STARS_B),\r
540\r
541.I_C_BLnXX(~W_C_BLX),\r
542.I_C_BLX(W_C_BLX | ~W_V_BL2n),\r
543.I_MISSILEn(W_MISSILEn),\r
544.I_SHELLn(W_SHELLn),\r
545\r
546.O_R(W_R),\r
547.O_G(W_G),\r
548.O_B(W_B)\r
549\r
550);\r
551\r
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552wire [2:0]W_VGA_R;\r
553wire [2:0]W_VGA_G;\r
554wire [1:0]W_VGA_B;\r
555\r
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556`ifdef VGA_USE\r
557mc_vga_if VGA(\r
558\r
559// input\r
560.I_CLK_1(W_CLK_6M),\r
561.I_CLK_2(W_CLK_12M),\r
562.I_R(W_R),\r
563.I_G(W_G),\r
564.I_B(W_B),\r
565.I_H_SYNC(W_H_SYNC),\r
566.I_V_SYNC(W_V_SYNC),\r
567// output\r
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568.O_R(W_VGA_R),\r
569.O_G(W_VGA_G),\r
570.O_B(W_VGA_B),\r
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571.O_H_SYNCn(O_VGA_H_SYNCn),\r
572.O_V_SYNCn(O_VGA_V_SYNCn)\r
573\r
574);\r
575\r
576`else\r
577\r
491f582f 578assign W_VGA_R[2:0] = W_R;\r
782690d0 579\r
491f582f 580assign W_VGA_G[2:0] = W_G;\r
782690d0 581\r
491f582f 582assign W_VGA_B[1:0] = W_B;\r
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583\r
584//assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ; // AKIDUKI LCD USED\r
585assign O_VGA_H_SYNCn = ~W_H_SYNC ;\r
586assign O_VGA_V_SYNCn = ~W_V_SYNC ;\r
587\r
588`endif\r
589\r
e780c439 590assign O_VGA_R[3:0] = {W_VGA_R[0], W_VGA_R[1], W_VGA_R[2], 1'b0};\r
491f582f 591\r
e780c439 592assign O_VGA_G[3:0] = {W_VGA_G[0], W_VGA_G[1], W_VGA_G[2], 1'b0};\r
491f582f 593\r
e780c439 594assign O_VGA_B[3:0] = {W_VGA_B[0], W_VGA_B[1], 2'b0};\r
491f582f 595\r
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596wire [7:0]W_SDAT_A;\r
597\r
598mc_sound_a MC_SOUND_A(\r
599\r
600.I_CLK_12M(W_CLK_12M),\r
601.I_CLK_6M(W_CLK_6M),\r
602.I_H_CNT1(W_H_CNT[1]),\r
603.I_BD(W_BDI),\r
604.I_PITCHn(W_PITCHn),\r
605.I_VOL1(W_VOL1),\r
606.I_VOL2(W_VOL2),\r
607\r
608.O_SDAT(W_SDAT_A),\r
609.O_DO()\r
610\r
611);\r
612\r
613wire [7:0]W_SDAT_B;\r
614\r
615mc_sound_b MC_SOUND_B(\r
616\r
c3bcc38a 617.I_CLK1(W_CLK_18M),\r
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618.I_CLK2(W_CLK_6M),\r
619.I_RSTn(rst_count[3]),\r
620.I_SW({&on_game[1:0],W_HIT,W_FIRE}),\r
621\r
622.O_WAV_A0(W_WAV_A0),\r
623.O_WAV_A1(W_WAV_A1),\r
624.O_WAV_A2(W_WAV_A2),\r
625.I_WAV_D0(W_WAV_D0),\r
626.I_WAV_D1(W_WAV_D1),\r
627.I_WAV_D2(W_WAV_D2),\r
628\r
629.O_SDAT(W_SDAT_B)\r
630\r
631);\r
632\r
633wire W_DAC_A;\r
634wire W_DAC_B;\r
635\r
636assign O_SOUND_OUT_L = W_DAC_A;\r
637assign O_SOUND_OUT_R = W_DAC_B;\r
638\r
639dac wav_dac_a(\r
640\r
c3bcc38a 641.Clk(W_CLK_18M), \r
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642.Reset(~W_RESETn),\r
643.DACin(W_SDAT_A),\r
644.DACout(W_DAC_A)\r
645\r
646);\r
647\r
648dac wav_dac_b(\r
649\r
c3bcc38a 650.Clk(W_CLK_18M), \r
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651.Reset(~W_RESETn),\r
652.DACin(W_SDAT_B),\r
653.DACout(W_DAC_B)\r
654\r
655);\r
656\r
657\r
658endmodule\r
659\r
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