]> git.zerfleddert.de Git - fpga-games/blame - galaxian/src/altera/alt_ram_1024_8_8.v
projects / fpga-games / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
galaxians
[fpga-games] / galaxian / src / altera / alt_ram_1024_8_8.v
CommitLineData
782690d0
MG		 1// megafunction wizard: %RAM: 2-PORT%\r
2// GENERATION: STANDARD\r
3// VERSION: WM1.0\r
4// MODULE: altsyncram \r
5\r
6// ============================================================\r
7// File Name: alt_ram_1024_8_8.v\r
8// Megafunction Name(s):\r
9// altsyncram\r
10// ============================================================\r
11// ************************************************************\r
12// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
13//\r
14// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition\r
15// ************************************************************\r
16\r
17\r
18//Copyright (C) 1991-2004 Altera Corporation\r
19//Any megafunction design, and related netlist (encrypted or decrypted),\r
20//support information, device programming or simulation file, and any other\r
21//associated documentation or information provided by Altera or a partner\r
22//under Altera's Megafunction Partnership Program may be used only\r
23//to program PLD devices (but not masked PLD devices) from Altera. Any\r
24//other use of such megafunction design, netlist, support information,\r
25//device programming or simulation file, or any other related documentation\r
26//or information is prohibited for any other purpose, including, but not\r
27//limited to modification, reverse engineering, de-compiling, or use with\r
28//any other silicon devices, unless such use is explicitly licensed under\r
29//a separate agreement with Altera or a megafunction partner. Title to the\r
30//intellectual property, including patents, copyrights, trademarks, trade\r
31//secrets, or maskworks, embodied in any such megafunction design, netlist,\r
32//support information, device programming or simulation file, or any other\r
33//related documentation or information provided by Altera or a megafunction\r
34//partner, remains with Altera, the megafunction partner, or their respective\r
35//licensors. No other licenses, including any licenses needed under any third\r
36//party's intellectual property, are provided herein.\r
37\r
38\r
39// synopsys translate_off\r
40`timescale 1 ps / 1 ps\r
41// synopsys translate_on\r
42module alt_ram_1024_8_8 (\r
43 data_a,\r
44 wren_a,\r
45 address_a,\r
46 data_b,\r
47 address_b,\r
48 wren_b,\r
49 clock_a,\r
50 enable_a,\r
51 clock_b,\r
52 enable_b,\r
53 q_a,\r
54 q_b);\r
55\r
56 input [7:0] data_a;\r
57 input wren_a;\r
58 input [9:0] address_a;\r
59 input [7:0] data_b;\r
60 input [9:0] address_b;\r
61 input wren_b;\r
62 input clock_a;\r
63 input enable_a;\r
64 input clock_b;\r
65 input enable_b;\r
66 output [7:0] q_a;\r
67 output [7:0] q_b;\r
68\r
69 wire [7:0] sub_wire0;\r
70 wire [7:0] sub_wire1;\r
71 wire [7:0] q_a = sub_wire0[7:0];\r
72 wire [7:0] q_b = sub_wire1[7:0];\r
73\r
74 altsyncram altsyncram_component (\r
75 .clocken0 (enable_a),\r
76 .clocken1 (enable_b),\r
77 .wren_a (wren_a),\r
78 .clock0 (clock_a),\r
79 .wren_b (wren_b),\r
80 .clock1 (clock_b),\r
81 .address_a (address_a),\r
82 .address_b (address_b),\r
83 .data_a (data_a),\r
84 .data_b (data_b),\r
85 .q_a (sub_wire0),\r
86 .q_b (sub_wire1)\r
87 // synopsys translate_off\r
88,\r
89 .rden_b (),\r
90 .aclr0 (),\r
91 .aclr1 (),\r
92 .byteena_a (),\r
93 .byteena_b (),\r
94 .addressstall_a (),\r
95 .addressstall_b ()\r
96 // synopsys translate_on\r
97\r
98);\r
99 defparam\r
100 altsyncram_component.intended_device_family = "Cyclone",\r
101 altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",\r
102 altsyncram_component.width_a = 8,\r
103 altsyncram_component.widthad_a = 10,\r
104 altsyncram_component.numwords_a = 1024,\r
105 altsyncram_component.width_b = 8,\r
106 altsyncram_component.widthad_b = 10,\r
107 altsyncram_component.numwords_b = 1024,\r
108 altsyncram_component.lpm_type = "altsyncram",\r
109 altsyncram_component.width_byteena_a = 1,\r
110 altsyncram_component.width_byteena_b = 1,\r
111 altsyncram_component.outdata_reg_a = "UNREGISTERED",\r
112 altsyncram_component.outdata_aclr_a = "NONE",\r
113 altsyncram_component.outdata_reg_b = "UNREGISTERED",\r
114 altsyncram_component.indata_aclr_a = "NONE",\r
115 altsyncram_component.wrcontrol_aclr_a = "NONE",\r
116 altsyncram_component.address_aclr_a = "NONE",\r
117 altsyncram_component.indata_reg_b = "CLOCK1",\r
118 altsyncram_component.address_reg_b = "CLOCK1",\r
119 altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1",\r
120 altsyncram_component.indata_aclr_b = "NONE",\r
121 altsyncram_component.wrcontrol_aclr_b = "NONE",\r
122 altsyncram_component.address_aclr_b = "NONE",\r
123 altsyncram_component.outdata_aclr_b = "NONE",\r
124 altsyncram_component.ram_block_type = "AUTO";\r
125\r
126\r
127endmodule\r
128\r
129// ============================================================\r
130// CNX file retrieval info\r
131// ============================================================\r
132// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"\r
133// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"\r
134// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"\r
135// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
136// Retrieval info: PRIVATE: VarWidth NUMERIC "0"\r
137// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"\r
138// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"\r
139// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"\r
140// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"\r
141// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"\r
142// Retrieval info: PRIVATE: Clock NUMERIC "5"\r
143// Retrieval info: PRIVATE: rden NUMERIC "0"\r
144// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"\r
145// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"\r
146// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"\r
147// Retrieval info: PRIVATE: Clock_A NUMERIC "0"\r
148// Retrieval info: PRIVATE: Clock_B NUMERIC "0"\r
149// Retrieval info: PRIVATE: REGdata NUMERIC "1"\r
150// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"\r
151// Retrieval info: PRIVATE: REGwren NUMERIC "1"\r
152// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"\r
153// Retrieval info: PRIVATE: REGrren NUMERIC "0"\r
154// Retrieval info: PRIVATE: REGq NUMERIC "0"\r
155// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"\r
156// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"\r
157// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"\r
158// Retrieval info: PRIVATE: CLRdata NUMERIC "0"\r
159// Retrieval info: PRIVATE: CLRwren NUMERIC "0"\r
160// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"\r
161// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"\r
162// Retrieval info: PRIVATE: CLRrren NUMERIC "0"\r
163// Retrieval info: PRIVATE: CLRq NUMERIC "0"\r
164// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"\r
165// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"\r
166// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"\r
167// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"\r
168// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"\r
169// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"\r
170// Retrieval info: PRIVATE: enable NUMERIC "1"\r
171// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"\r
172// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"\r
173// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"\r
174// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"\r
175// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"\r
176// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"\r
177// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"\r
178// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"\r
179// Retrieval info: PRIVATE: MIFfilename STRING ""\r
180// Retrieval info: PRIVATE: UseLCs NUMERIC "0"\r
181// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"\r
182// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"\r
183// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"\r
184// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "wren_a;wren_b;rden_b;data_a;data_b"\r
185// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "address_a;address_b;clock0;clock1;clocken0"\r
186// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "clocken1;aclr0;aclr1;byteena_a;byteena_b"\r
187// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "addressstall_a;addressstall_b;q_a;q_b"\r
188// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
189// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"\r
190// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"\r
191// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"\r
192// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"\r
193// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"\r
194// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"\r
195// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"\r
196// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"\r
197// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"\r
198// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"\r
199// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"\r
200// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"\r
201// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"\r
202// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"\r
203// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"\r
204// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"\r
205// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"\r
206// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"\r
207// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"\r
208// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"\r
209// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"\r
210// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"\r
211// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"\r
212// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"\r
213// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]\r
214// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a\r
215// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]\r
216// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]\r
217// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL address_a[9..0]\r
218// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]\r
219// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL address_b[9..0]\r
220// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b\r
221// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a\r
222// Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC enable_a\r
223// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b\r
224// Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC enable_b\r
225// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0\r
226// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0\r
227// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0\r
228// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0\r
229// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0\r
230// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0\r
231// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0\r
232// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0\r
233// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0\r
234// Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0\r
235// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0\r
236// Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0\r
237// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
238// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8.v TRUE\r
239// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8.inc FALSE\r
240// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8.cmp FALSE\r
241// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8.bsf FALSE\r
242// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8_inst.v FALSE\r
243// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8_bb.v FALSE\r
244// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8_waveforms.html FALSE\r
245// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8_wave*.jpg FALSE\r
Arcade Games for FPGAs (currently only galaxian)
Impressum, Datenschutz