galaxians
[fpga-games] / galaxian / src / altera / alt_ram_256_8.v
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MG
1// megafunction wizard: %RAM: 1-PORT%\r
2// GENERATION: STANDARD\r
3// VERSION: WM1.0\r
4// MODULE: altsyncram \r
5\r
6// ============================================================\r
7// File Name: alt_ram_256_8.v\r
8// Megafunction Name(s):\r
9// altsyncram\r
10// ============================================================\r
11// ************************************************************\r
12// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
13// ************************************************************\r
14\r
15\r
16//Copyright (C) 1991-2003 Altera Corporation\r
17//Any megafunction design, and related netlist (encrypted or decrypted),\r
18//support information, device programming or simulation file, and any other\r
19//associated documentation or information provided by Altera or a partner\r
20//under Altera's Megafunction Partnership Program may be used only\r
21//to program PLD devices (but not masked PLD devices) from Altera. Any\r
22//other use of such megafunction design, netlist, support information,\r
23//device programming or simulation file, or any other related documentation\r
24//or information is prohibited for any other purpose, including, but not\r
25//limited to modification, reverse engineering, de-compiling, or use with\r
26//any other silicon devices, unless such use is explicitly licensed under\r
27//a separate agreement with Altera or a megafunction partner. Title to the\r
28//intellectual property, including patents, copyrights, trademarks, trade\r
29//secrets, or maskworks, embodied in any such megafunction design, netlist,\r
30//support information, device programming or simulation file, or any other\r
31//related documentation or information provided by Altera or a megafunction\r
32//partner, remains with Altera, the megafunction partner, or their respective\r
33//licensors. No other licenses, including any licenses needed under any third\r
34//party's intellectual property, are provided herein.\r
35\r
36\r
37module alt_ram_256_8 (\r
38 address,\r
39 clock,\r
40 data,\r
41 wren,\r
42 q);\r
43\r
44 input [7:0] address;\r
45 input clock;\r
46 input [7:0] data;\r
47 input wren;\r
48 output [7:0] q;\r
49\r
50 wire [7:0] sub_wire0;\r
51 wire [7:0] q = sub_wire0[7:0];\r
52\r
53 altsyncram altsyncram_component (\r
54 .wren_a (wren),\r
55 .clock0 (clock),\r
56 .address_a (address),\r
57 .data_a (data),\r
58 .q_a (sub_wire0));\r
59 defparam\r
60 altsyncram_component.intended_device_family = "Cyclone",\r
61 altsyncram_component.width_a = 8,\r
62 altsyncram_component.widthad_a = 8,\r
63 altsyncram_component.numwords_a = 256,\r
64 altsyncram_component.operation_mode = "SINGLE_PORT",\r
65 altsyncram_component.outdata_reg_a = "UNREGISTERED",\r
66 altsyncram_component.indata_aclr_a = "NONE",\r
67 altsyncram_component.wrcontrol_aclr_a = "NONE",\r
68 altsyncram_component.address_aclr_a = "NONE",\r
69 altsyncram_component.outdata_aclr_a = "NONE",\r
70 altsyncram_component.width_byteena_a = 1,\r
71 altsyncram_component.ram_block_type = "AUTO",\r
72 altsyncram_component.lpm_type = "altsyncram";\r
73\r
74\r
75endmodule\r
76\r
77// ============================================================\r
78// CNX file retrieval info\r
79// ============================================================\r
80// Retrieval info: PRIVATE: WidthData NUMERIC "8"\r
81// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"\r
82// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
83// Retrieval info: PRIVATE: SingleClock NUMERIC "1"\r
84// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"\r
85// Retrieval info: PRIVATE: RegData NUMERIC "1"\r
86// Retrieval info: PRIVATE: RegAddr NUMERIC "1"\r
87// Retrieval info: PRIVATE: RegOutput NUMERIC "0"\r
88// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"\r
89// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"\r
90// Retrieval info: PRIVATE: AclrByte NUMERIC "0"\r
91// Retrieval info: PRIVATE: AclrData NUMERIC "0"\r
92// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"\r
93// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"\r
94// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"\r
95// Retrieval info: PRIVATE: Clken NUMERIC "0"\r
96// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"\r
97// Retrieval info: PRIVATE: MIFfilename STRING ""\r
98// Retrieval info: PRIVATE: UseLCs NUMERIC "0"\r
99// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"\r
100// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"\r
101// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"\r
102// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"\r
103// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
104// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"\r
105// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"\r
106// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"\r
107// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"\r
108// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"\r
109// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"\r
110// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"\r
111// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"\r
112// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"\r
113// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"\r
114// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"\r
115// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"\r
116// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]\r
117// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]\r
118// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock\r
119// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]\r
120// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren\r
121// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0\r
122// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0\r
123// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0\r
124// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0\r
125// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0\r
126// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
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