galaxians
[fpga-games] / galaxian / src / mc_top.v
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782690d0
MG
1//===============================================================================\r
2// FPGA GALAXIAN TOP\r
3//\r
4// Version : 2.50\r
5//\r
6// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// Important !\r
9//\r
10// This program is freeware for non-commercial use. \r
11// An author does no guarantee about this program.\r
12// You can use this under your own risk.\r
13//\r
14// 2004- 4-30 galaxian modify by K.DEGAWA\r
15// 2004- 5- 6 first release.\r
16// 2004- 8-23 Improvement with T80-IP.\r
17// 2004- 9-18 The description of ALTERA(CYCLONE) and XILINX(SPARTAN2E) was made one.\r
18// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
19//================================================================================\r
20\r
21`include "src/mc_conf.v" \r
22 \r
23module mc_top(\r
24\r
25// FPGA_USE\r
26I_CLK_125M,\r
27\r
28`ifdef PSPAD_USE\r
29// PS_PAD interface\r
30psCLK,\r
31psSEL,\r
32psTXD,\r
33psRXD,\r
34`endif\r
35\r
36// ROM IF\r
37//O_ROM_AB,\r
38//I_ROM_DB,\r
39//O_ROM_OEn,\r
40//O_ROM_CSn,\r
41//O_ROM_WEn,\r
42\r
43// INPORT SW IF\r
44I_PSW,\r
45\r
46// SOUND OUT\r
47O_SOUND_OUT_L,\r
48O_SOUND_OUT_R,\r
49\r
50// VGA (VIDEO) IF\r
51O_VGA_R,\r
52O_VGA_G,\r
53O_VGA_B,\r
54O_VGA_H_SYNCn,\r
55O_VGA_V_SYNCn\r
56\r
57);\r
58\r
59// FPGA_USE\r
60input I_CLK_125M;\r
61\r
62// CPU ADDRESS BUS\r
63wire [15:0]W_A;\r
64// CPU IF\r
65wire W_CPU_RDn;\r
66wire W_CPU_WRn;\r
67wire W_CPU_MREQn;\r
68wire W_CPU_RFSHn;\r
69wire W_CPU_BUSAKn;\r
70wire W_CPU_IORQn;\r
71wire W_CPU_M1n;\r
72wire W_CPU_CLK;\r
73wire W_CPU_HRDWR_RESETn;\r
74wire W_CPU_WAITn;\r
75wire W_CPU_NMIn;\r
76\r
77`ifdef PSPAD_USE\r
78// PS_PAD interface\r
79input psRXD;\r
80output psTXD,psCLK,psSEL;\r
81`endif\r
82\r
83// ROM IF\r
84//output [18:0]O_ROM_AB;\r
85//input [7:0]I_ROM_DB;\r
86//output O_ROM_OEn;\r
87//output O_ROM_CSn;\r
88//output O_ROM_WEn;\r
89\r
90// INPORT SW IF\r
91input [4:0]I_PSW;\r
92\r
93// SOUND OUT \r
94output O_SOUND_OUT_L;\r
95output O_SOUND_OUT_R;\r
96\r
97// VGA (VIDEO) IF\r
98output [4:0]O_VGA_R;\r
99output [4:0]O_VGA_G;\r
100output [4:0]O_VGA_B;\r
101output O_VGA_H_SYNCn;\r
102output O_VGA_V_SYNCn;\r
103\r
104wire W_RESETn = |I_PSW[3:0];\r
105//------ CLOCK GEN ---------------------------\r
106wire I_CLK_18432M;\r
107wire W_CLK_12M,WB_CLK_12M;\r
108wire W_CLK_6M,WB_CLK_6M;\r
109wire W_STARS_CLK;\r
110\r
111dcm clockgen(\r
112.CLKIN_IN(I_CLK_125M),\r
113.RST_IN(W_RESETn),\r
114.CLKFX_OUT(I_CLK_18432M)\r
115);\r
116\r
117//------ H&V COUNTER -------------------------\r
118wire [8:0]W_H_CNT;\r
119wire [7:0]W_V_CNT;\r
120wire W_H_BL;\r
121wire W_V_BLn;\r
122wire W_C_BLn;\r
123wire W_H_SYNC;\r
124wire W_V_SYNC;\r
125\r
126//------ CPU RAM ----------------------------\r
127wire [7:0]W_CPU_RAM_DO;\r
128\r
129//------ ADDRESS DECDER ----------------------\r
130wire W_CPU_ROM_CSn;\r
131wire W_CPU_RAM_RDn;\r
132wire W_CPU_RAM_WRn;\r
133wire W_CPU_RAM_CSn;\r
134wire W_OBJ_RAM_RDn;\r
135wire W_OBJ_RAM_WRn;\r
136wire W_OBJ_RAM_RQn;\r
137wire W_VID_RAM_RDn;\r
138wire W_VID_RAM_WRn;\r
139wire W_SW0_OEn;\r
140wire W_SW1_OEn;\r
141wire W_DIP_OEn;\r
142wire W_WDR_OEn;\r
143wire W_LAMP_WEn;\r
144wire W_SOUND_WEn;\r
145wire W_PITCHn;\r
146wire W_H_FLIP;\r
147wire W_V_FLIP;\r
148wire W_BD_G;\r
149wire W_STARS_ON;\r
150\r
151wire W_VID_RDn = W_OBJ_RAM_RDn & W_VID_RAM_RDn ;\r
152wire W_SW_OEn = W_SW0_OEn & W_SW1_OEn & W_DIP_OEn ;\r
153//------- INPORT -----------------------------\r
154wire [7:0]W_SW_DO;\r
155//------- VIDEO -----------------------------\r
156wire [7:0]W_VID_DO;\r
157//--------------------------------------------\r
158\r
159mc_clock MC_CLK(\r
160\r
161.I_CLK_18M(I_CLK_18432M),\r
162.O_CLK_12M(WB_CLK_12M),\r
163.O_CLK_06M(WB_CLK_6M)\r
164\r
165);\r
166\r
167`ifdef DEVICE_CYCLONE\r
168assign W_CLK_12M = WB_CLK_12M;\r
169assign W_CLK_6M = WB_CLK_6M;\r
170`endif\r
171`ifdef DEVICE_SPARTAN2E\r
172BUFG BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) );\r
173BUFG BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) );\r
174`endif\r
175//--- DATA I/F -------------------------------------\r
176reg [7:0]W_CPU_ROM_DO;\r
177wire [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;\r
178\r
179wire [7:0]W_BDO = W_SW_DO | W_VID_DO | W_CPU_RAM_DO | W_CPU_ROM_DOB ;\r
180wire [7:0]W_BDI;\r
181\r
182//--- CPU I/F -------------------------------------\r
183reg [3:0]rst_count;\r
184always@(posedge W_H_CNT[0] or negedge W_RESETn)\r
185begin\r
186 if(! W_RESETn) rst_count <= 0;\r
187 else begin\r
188 if( rst_count == 15) \r
189 rst_count <= rst_count;\r
190 else\r
191 rst_count <= rst_count+1;\r
192 end\r
193end\r
194\r
195assign W_CPU_RESETn = W_RESETn;\r
196assign W_CPU_CLK = W_H_CNT[0];\r
197\r
198Z80IP CPU(\r
199 \r
200.CLK(W_CPU_CLK),\r
201.RESET_N(W_CPU_RESETn),\r
202.INT_N(1'b1),\r
203.NMI_N(W_CPU_NMIn),\r
204.ADRS(W_A),\r
205.DOUT(W_BDI),\r
206.DINP(W_BDO),\r
207.M1_N(),\r
208.MREQ_N(W_CPU_MREQn),\r
209.IORQ_N(),\r
210.RD_N(W_CPU_RDn ),\r
211.WR_N(W_CPU_WRn ),\r
212.WAIT_N(W_CPU_WAITn),\r
213.BUSWO(),\r
214.RFSH_N(W_CPU_RFSHn),\r
215.HALT_N()\r
216\r
217);\r
218\r
219wire W_CPU_RAM_CLK = W_CLK_12M & ~W_CPU_RAM_CSn;\r
220\r
221mc_cpu_ram MC_CPU_RAM(\r
222\r
223.I_CLK(W_CPU_RAM_CLK),\r
224.I_ADDR(W_A[9:0]),\r
225.I_D(W_BDI),\r
226.I_WE(~W_CPU_WRn),\r
227.I_OE(~W_CPU_RAM_RDn ),\r
228.O_D(W_CPU_RAM_DO)\r
229\r
230);\r
231\r
232\r
233mc_adec MC_ADEC(\r
234\r
235.I_CLK_12M(W_CLK_12M),\r
236.I_CLK_6M(W_CLK_6M),\r
237.I_CPU_CLK(W_H_CNT[0]),\r
238.I_RSTn(W_RESETn),\r
239\r
240.I_CPU_A(W_A),\r
241.I_CPU_D(W_BDI[0]),\r
242.I_MREQn(W_CPU_MREQn),\r
243.I_RFSHn(W_CPU_RFSHn),\r
244.I_RDn(W_CPU_RDn),\r
245.I_WRn(W_CPU_WRn),\r
246.I_H_BL(W_H_BL),\r
247.I_V_BLn(W_V_BLn),\r
248\r
249.O_WAITn(W_CPU_WAITn),\r
250.O_NMIn(W_CPU_NMIn),\r
251.O_CPU_ROM_CSn(W_CPU_ROM_CSn),\r
252.O_CPU_RAM_RDn(W_CPU_RAM_RDn),\r
253.O_CPU_RAM_WRn(W_CPU_RAM_WRn),\r
254.O_CPU_RAM_CSn(W_CPU_RAM_CSn),\r
255.O_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
256.O_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
257.O_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
258.O_VID_RAM_RDn(W_VID_RAM_RDn),\r
259.O_VID_RAM_WRn(W_VID_RAM_WRn),\r
260.O_SW0_OEn(W_SW0_OEn),\r
261.O_SW1_OEn(W_SW1_OEn),\r
262.O_DIP_OEn(W_DIP_OEn),\r
263.O_WDR_OEn(W_WDR_OEn),\r
264.O_LAMP_WEn(W_LAMP_WEn),\r
265.O_SOUND_WEn(W_SOUND_WEn),\r
266.O_PITCHn(W_PITCHn),\r
267.O_H_FLIP(W_H_FLIP),\r
268.O_V_FLIP(W_V_FLIP),\r
269.O_BD_G(W_BD_G),\r
270.O_STARS_ON(W_STARS_ON)\r
271\r
272);\r
273\r
274//-------- SOUND I/F -----------------------------\r
275//--- Parts 9L ---------\r
276reg [7:0]W_9L_Q;\r
277always@(posedge W_CLK_12M or negedge W_RESETn)\r
278begin\r
279 if(W_RESETn == 1'b0)begin\r
280 W_9L_Q <= 0;\r
281 end \r
282 else begin\r
283 if(W_SOUND_WEn == 1'b0)begin\r
284 case(W_A[2:0])\r
285 3'h0 : W_9L_Q[0] <= W_BDI[0];\r
286 3'h1 : W_9L_Q[1] <= W_BDI[0];\r
287 3'h2 : W_9L_Q[2] <= W_BDI[0];\r
288 3'h3 : W_9L_Q[3] <= W_BDI[0];\r
289 3'h4 : W_9L_Q[4] <= W_BDI[0];\r
290 3'h5 : W_9L_Q[5] <= W_BDI[0];\r
291 3'h6 : W_9L_Q[6] <= W_BDI[0];\r
292 3'h7 : W_9L_Q[7] <= W_BDI[0];\r
293 endcase\r
294 end\r
295 end\r
296end\r
297wire W_VOL1 = W_9L_Q[6];\r
298wire W_VOL2 = W_9L_Q[7];\r
299wire W_FIRE = W_9L_Q[5];\r
300wire W_HIT = W_9L_Q[3];\r
301wire W_FS3 = W_9L_Q[2];\r
302wire W_FS2 = W_9L_Q[1];\r
303wire W_FS1 = W_9L_Q[0];\r
304//---------------------------------------------------\r
305//---- CPU DATA WATCH -------------------------------\r
306wire ZMWR = W_CPU_MREQn | W_CPU_WRn ;\r
307\r
308reg [1:0]on_game;\r
309always @(posedge W_CPU_CLK)\r
310begin\r
311 if(~ZMWR)begin\r
312 if(W_A == 16'h4007)begin\r
313 if(W_BDI == 8'h00) \r
314 on_game[0] <= 1;\r
315 else\r
316 on_game[0] <= 0;\r
317 end\r
318 if(W_A == 16'h4005)begin\r
319 if(W_BDI == 8'h03 || W_BDI == 8'h04 ) \r
320 on_game[1] <= 1;\r
321 else\r
322 on_game[1] <= 0;\r
323 end\r
324 end \r
325end\r
326\r
327`ifdef PSPAD_USE\r
328reg died;\r
329always @(posedge W_CPU_CLK)\r
330begin\r
331 if(~ZMWR)begin\r
332 if(W_A == 16'h4206)begin\r
333 if(W_BDI == 8'h00) \r
334 died <= 0;\r
335 else\r
336 died <= 1;\r
337 end\r
338 end\r
339end\r
340//---- PS_PAD Interface -----------------------------\r
341wire [8:0]ps_PSW;\r
342wire VIB_SW = died & (&on_game[1:0]);\r
343\r
344fpga_arcade_if pspad(\r
345\r
346.CLK_18M432(I_CLK_18432M),\r
347.I_RSTn(W_RESETn),\r
348.psCLK(psCLK),\r
349.psSEL(psSEL),\r
350.psTXD(psTXD),\r
351.psRXD(psRXD),\r
352.ps_PSW(ps_PSW),\r
353.I_VIB_SW(VIB_SW)\r
354\r
355);\r
356`endif\r
357//---- SW Interface ---------------------------------\r
358`ifdef PSPAD_USE\r
359wire L1 = I_PSW[2] & ps_PSW[2];\r
360wire R1 = I_PSW[3] & ps_PSW[3];\r
361wire U1 = I_PSW[0];\r
362wire D1 = I_PSW[1];\r
363wire J1 = I_PSW[4] & ps_PSW[8];\r
364\r
365wire S1 = (U1|J1) & ps_PSW[6];\r
366wire S2 = (D1|J1) & ps_PSW[7];\r
367\r
368wire C1 = (L1|R1|U1|~D1) & ps_PSW[4];\r
369`else\r
370wire L1 = I_PSW[2];\r
371wire R1 = I_PSW[3];\r
372wire U1 = I_PSW[0];\r
373wire D1 = I_PSW[1];\r
374wire J1 = I_PSW[4];\r
375\r
376wire S1 = U1|J1;\r
377wire S2 = D1|J1;\r
378\r
379wire C1 = L1|R1|U1|~D1;\r
380`endif\r
381wire C2 = L1|R1|~U1|D1;\r
382\r
383wire L2 = L1;\r
384wire R2 = R1;\r
385wire U2 = U1;\r
386wire D2 = D1;\r
387wire J2 = J1;\r
388\r
389mc_inport MC_INPORT(\r
390\r
391.I_COIN1(~C1), // ACTIVE HI\r
392.I_COIN2(~C2), // ACTIVE HI\r
393.I_1P_LE(~L1), // ACTIVE HI\r
394.I_1P_RI(~R1), // ACTIVE HI\r
395.I_1P_SH(~J1), // ACTIVE HI\r
396.I_2P_LE(~L2), // ACTIVE HI\r
397.I_2P_RI(~R2), // ACTIVE HI\r
398.I_2P_SH(~J2), // ACTIVE HI\r
399.I_1P_START(~S1), // ACTIVE HI\r
400.I_2P_START(~S2), // ACTIVE HI\r
401\r
402.I_SW0_OEn(W_SW0_OEn),\r
403.I_SW1_OEn(W_SW1_OEn),\r
404.I_DIP_OEn(W_DIP_OEn),\r
405\r
406.O_D(W_SW_DO)\r
407\r
408);\r
409\r
410//-----------------------------------------------------------------------------\r
411//------- ROM -------------------------------------------------------\r
412reg [18:0]ROM_A;\r
413wire [10:0]W_OBJ_ROM_A;\r
414reg [7:0]W_OBJ_ROM_A_D;\r
415reg [7:0]W_OBJ_ROM_B_D;\r
416\r
417wire [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;\r
418reg [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;\r
419\r
420wire [7:0]ROM_D; // = I_ROM_DB;\r
421//assign O_ROM_AB = ROM_A;\r
422\r
423//assign O_ROM_OEn = 1'b0;\r
424//assign O_ROM_CSn = 1'b0;\r
425//assign O_ROM_WEn = 1'b1;\r
426\r
427galaxian_roms ROMS(\r
428.I_CLK_18432M(I_CLK_18432M),\r
429.I_CLK_12M(WB_CLK_12M),\r
430.I_ADDR(ROM_A),\r
431.O_DATA(ROM_D)\r
432);\r
433\r
434\r
435reg [1:0]clk_d;\r
436reg [4:0]seq;\r
437always @(posedge I_CLK_18432M)\r
438begin\r
439 // 24 phase generator\r
440 clk_d[0] <= W_H_CNT[0] & W_H_CNT[1] & W_H_CNT[2];\r
441 clk_d[1] <= clk_d[0];\r
442 seq <= (~clk_d[1] & clk_d[0]) ? 0 : seq+1;\r
443 case(seq)\r
444 0:begin\r
445 //sound\r
446 ROM_A <= W_WAV_A0;\r
447 W_CPU_ROM_DO <= ROM_D;\r
448 end\r
449 2:begin\r
450 //sound\r
451 ROM_A <= W_WAV_A1;\r
452 W_WAV_D0 <= ROM_D;\r
453 end\r
454 4:begin\r
455 //sound\r
456 ROM_A <= {3'h0,W_A[15:0]};\r
457 W_WAV_D1 <= ROM_D;\r
458 end\r
459 6:begin\r
460 //sound\r
461 ROM_A <= W_WAV_A2;\r
462 W_CPU_ROM_DO <= ROM_D;\r
463 end\r
464 8:W_WAV_D2 <= ROM_D; //sound\r
465 10:ROM_A <= {3'h0,W_A[15:0]};\r
466 12:W_CPU_ROM_DO <= ROM_D;\r
467 16:ROM_A <= {3'h0,W_A[15:0]};\r
468 18:begin\r
469 ROM_A <= {3'h0,4'h4,1'b0,W_OBJ_ROM_A};\r
470 W_CPU_ROM_DO <= ROM_D;\r
471 end\r
472 20:begin\r
473 ROM_A <= {3'h0,4'h5,1'b0,W_OBJ_ROM_A};\r
474 W_OBJ_ROM_A_D <= ROM_D;\r
475 end\r
476 22:begin\r
477 ROM_A <= {3'h0,W_A[15:0]};\r
478 W_OBJ_ROM_B_D <= ROM_D;\r
479 end\r
480 default:;\r
481 endcase\r
482end\r
483//-----------------------------------------------------------------------------\r
484\r
485wire W_V_BL2n;\r
486\r
487mc_hv_count MC_HV(\r
488\r
489.I_CLK(WB_CLK_6M),\r
490.I_RSTn(W_RESETn),\r
491\r
492.O_H_CNT(W_H_CNT),\r
493.O_H_SYNC(W_H_SYNC),\r
494.O_H_BL(W_H_BL),\r
495.O_V_CNT(W_V_CNT),\r
496.O_V_SYNC(W_V_SYNC),\r
497.O_V_BL2n(W_V_BL2n),\r
498.O_V_BLn(W_V_BLn),\r
499.O_C_BLn(W_C_BLn)\r
500\r
501);\r
502\r
503//------ VIDEO -----------------------------\r
504wire W_8HF;\r
505wire W_1VF;\r
506wire W_C_BLnX;\r
507wire W_256HnX;\r
508wire W_MISSILEn;\r
509wire W_SHELLn;\r
510wire [1:0]W_VID;\r
511wire [2:0]W_COL;\r
512\r
513mc_video MC_VID(\r
514.I_CLK_18M(I_CLK_18432M),\r
515.I_CLK_12M(W_CLK_12M),\r
516.I_CLK_6M(W_CLK_6M),\r
517.I_H_CNT(W_H_CNT),\r
518.I_V_CNT(W_V_CNT),\r
519.I_H_FLIP(W_H_FLIP),\r
520.I_V_FLIP(W_V_FLIP),\r
521.I_V_BLn(W_V_BLn),\r
522.I_C_BLn(W_C_BLn),\r
523\r
524.I_A(W_A[9:0]),\r
525.I_OBJ_SUB_A(3'b000),\r
526.I_BD(W_BDI),\r
527.I_OBJ_RAM_RQn(W_OBJ_RAM_RQn),\r
528.I_OBJ_RAM_RDn(W_OBJ_RAM_RDn),\r
529.I_OBJ_RAM_WRn(W_OBJ_RAM_WRn),\r
530.I_VID_RAM_RDn(W_VID_RAM_RDn),\r
531.I_VID_RAM_WRn(W_VID_RAM_WRn),\r
532\r
533.O_OBJ_ROM_A(W_OBJ_ROM_A),\r
534.I_OBJ_ROM_A_D(W_OBJ_ROM_A_D),\r
535.I_OBJ_ROM_B_D(W_OBJ_ROM_B_D),\r
536\r
537.O_C_BLnX(W_C_BLnX),\r
538.O_8HF(W_8HF),\r
539.O_256HnX(W_256HnX),\r
540.O_1VF(W_1VF),\r
541.O_MISSILEn(W_MISSILEn),\r
542.O_SHELLn(W_SHELLn),\r
543.O_BD(W_VID_DO),\r
544.O_VID(W_VID),\r
545.O_COL(W_COL)\r
546\r
547);\r
548\r
549wire W_C_BLX;\r
550wire W_STARS_OFFn;\r
551wire [2:0]W_VIDEO_R;\r
552wire [2:0]W_VIDEO_G;\r
553wire [1:0]W_VIDEO_B;\r
554\r
555mc_col_pal MC_COL_PAL(\r
556\r
557.I_CLK_12M(W_CLK_12M),\r
558.I_CLK_6M(W_CLK_6M),\r
559.I_VID(W_VID),\r
560.I_COL(W_COL),\r
561.I_C_BLnX(W_C_BLnX),\r
562\r
563.O_C_BLX(W_C_BLX),\r
564.O_STARS_OFFn(W_STARS_OFFn),\r
565.O_R(W_VIDEO_R),\r
566.O_G(W_VIDEO_G),\r
567.O_B(W_VIDEO_B)\r
568\r
569);\r
570\r
571wire [2:0]W_STARS_R;\r
572wire [2:0]W_STARS_G;\r
573wire [1:0]W_STARS_B;\r
574\r
575mc_stars MC_STARS( \r
576\r
577.I_CLK_18M(I_CLK_18432M),\r
578`ifdef DEVICE_CYCLONE\r
579.I_CLK_6M(~WB_CLK_6M),\r
580`endif\r
581`ifdef DEVICE_SPARTAN2E \r
582.I_CLK_6M(WB_CLK_6M), \r
583`endif\r
584.I_H_FLIP(W_H_FLIP),\r
585.I_V_SYNC(W_V_SYNC),\r
586.I_8HF(W_8HF),\r
587.I_256HnX(W_256HnX),\r
588.I_1VF(W_1VF),\r
589.I_2V(W_V_CNT[1]),\r
590.I_STARS_ON(W_STARS_ON),\r
591.I_STARS_OFFn(W_STARS_OFFn),\r
592\r
593.O_R(W_STARS_R),\r
594.O_G(W_STARS_G),\r
595.O_B(W_STARS_B),\r
596.O_NOISE()\r
597\r
598);\r
599\r
600wire [2:0]W_R;\r
601wire [2:0]W_G;\r
602wire [1:0]W_B;\r
603\r
604mc_vedio_mix MIX(\r
605\r
606.I_VID_R(W_VIDEO_R),\r
607.I_VID_G(W_VIDEO_G),\r
608.I_VID_B(W_VIDEO_B),\r
609.I_STR_R(W_STARS_R),\r
610.I_STR_G(W_STARS_G),\r
611.I_STR_B(W_STARS_B),\r
612\r
613.I_C_BLnXX(~W_C_BLX),\r
614.I_C_BLX(W_C_BLX | ~W_V_BL2n),\r
615.I_MISSILEn(W_MISSILEn),\r
616.I_SHELLn(W_SHELLn),\r
617\r
618.O_R(W_R),\r
619.O_G(W_G),\r
620.O_B(W_B)\r
621\r
622);\r
623\r
624`ifdef VGA_USE\r
625mc_vga_if VGA(\r
626\r
627// input\r
628.I_CLK_1(W_CLK_6M),\r
629.I_CLK_2(W_CLK_12M),\r
630.I_R(W_R),\r
631.I_G(W_G),\r
632.I_B(W_B),\r
633.I_H_SYNC(W_H_SYNC),\r
634.I_V_SYNC(W_V_SYNC),\r
635// output\r
636.O_R(O_VGA_R),\r
637.O_G(O_VGA_G),\r
638.O_B(O_VGA_B),\r
639.O_H_SYNCn(O_VGA_H_SYNCn),\r
640.O_V_SYNCn(O_VGA_V_SYNCn)\r
641\r
642);\r
643\r
644`else\r
645\r
646assign O_VGA_R[2:0] = W_R;\r
647assign O_VGA_R[4:3] = 1'b0;\r
648\r
649assign O_VGA_G[2:0] = W_G;\r
650assign O_VGA_G[4:3] = 1'b0;\r
651\r
652assign O_VGA_B[1:0] = W_B;\r
653assign O_VGA_B[4:2] = 1'b0;\r
654\r
655//assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ; // AKIDUKI LCD USED\r
656assign O_VGA_H_SYNCn = ~W_H_SYNC ;\r
657assign O_VGA_V_SYNCn = ~W_V_SYNC ;\r
658\r
659`endif\r
660\r
661wire [7:0]W_SDAT_A;\r
662\r
663mc_sound_a MC_SOUND_A(\r
664\r
665.I_CLK_12M(W_CLK_12M),\r
666.I_CLK_6M(W_CLK_6M),\r
667.I_H_CNT1(W_H_CNT[1]),\r
668.I_BD(W_BDI),\r
669.I_PITCHn(W_PITCHn),\r
670.I_VOL1(W_VOL1),\r
671.I_VOL2(W_VOL2),\r
672\r
673.O_SDAT(W_SDAT_A),\r
674.O_DO()\r
675\r
676);\r
677\r
678wire [7:0]W_SDAT_B;\r
679\r
680mc_sound_b MC_SOUND_B(\r
681\r
682.I_CLK1(I_CLK_18432M),\r
683.I_CLK2(W_CLK_6M),\r
684.I_RSTn(rst_count[3]),\r
685.I_SW({&on_game[1:0],W_HIT,W_FIRE}),\r
686\r
687.O_WAV_A0(W_WAV_A0),\r
688.O_WAV_A1(W_WAV_A1),\r
689.O_WAV_A2(W_WAV_A2),\r
690.I_WAV_D0(W_WAV_D0),\r
691.I_WAV_D1(W_WAV_D1),\r
692.I_WAV_D2(W_WAV_D2),\r
693\r
694.O_SDAT(W_SDAT_B)\r
695\r
696);\r
697\r
698wire W_DAC_A;\r
699wire W_DAC_B;\r
700\r
701assign O_SOUND_OUT_L = W_DAC_A;\r
702assign O_SOUND_OUT_R = W_DAC_B;\r
703\r
704dac wav_dac_a(\r
705\r
706.Clk(I_CLK_18432M), \r
707.Reset(~W_RESETn),\r
708.DACin(W_SDAT_A),\r
709.DACout(W_DAC_A)\r
710\r
711);\r
712\r
713dac wav_dac_b(\r
714\r
715.Clk(I_CLK_18432M), \r
716.Reset(~W_RESETn),\r
717.DACin(W_SDAT_B),\r
718.DACout(W_DAC_B)\r
719\r
720);\r
721\r
722\r
723endmodule\r
724\r
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