galaxians
[fpga-games] / galaxian / t80_ip / T80_Pack.vhd
CommitLineData
782690d0
MG
1--
2-- Z80 compatible microprocessor core
3--
4-- Version : 0242
5--
6-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
7--
8-- All rights reserved
9--
10-- Redistribution and use in source and synthezised forms, with or without
11-- modification, are permitted provided that the following conditions are met:
12--
13-- Redistributions of source code must retain the above copyright notice,
14-- this list of conditions and the following disclaimer.
15--
16-- Redistributions in synthesized form must reproduce the above copyright
17-- notice, this list of conditions and the following disclaimer in the
18-- documentation and/or other materials provided with the distribution.
19--
20-- Neither the name of the author nor the names of other contributors may
21-- be used to endorse or promote products derived from this software without
22-- specific prior written permission.
23--
24-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
28-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34-- POSSIBILITY OF SUCH DAMAGE.
35--
36-- Please report bugs to the author, but before you do so, please
37-- make sure that this is not a derivative work and that
38-- you have the latest version of this file.
39--
40-- The latest version of this file can be found at:
41-- http://www.opencores.org/cvsweb.shtml/t80/
42--
43-- Limitations :
44--
45-- File history :
46--
47
48library IEEE;
49use IEEE.std_logic_1164.all;
50
51package T80_Pack is
52
53 component T80
54 generic(
55 Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
56 IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
57 Flag_C : integer := 0;
58 Flag_N : integer := 1;
59 Flag_P : integer := 2;
60 Flag_X : integer := 3;
61 Flag_H : integer := 4;
62 Flag_Y : integer := 5;
63 Flag_Z : integer := 6;
64 Flag_S : integer := 7
65 );
66 port(
67 RESET_n : in std_logic;
68 CLK_n : in std_logic;
69 CEN : in std_logic;
70 WAIT_n : in std_logic;
71 INT_n : in std_logic;
72 NMI_n : in std_logic;
73 BUSRQ_n : in std_logic;
74 M1_n : out std_logic;
75 IORQ : out std_logic;
76 NoRead : out std_logic;
77 Write : out std_logic;
78 RFSH_n : out std_logic;
79 HALT_n : out std_logic;
80 BUSAK_n : out std_logic;
81 A : out std_logic_vector(15 downto 0);
82 DInst : in std_logic_vector(7 downto 0);
83 DI : in std_logic_vector(7 downto 0);
84 DO : out std_logic_vector(7 downto 0);
85 MC : out std_logic_vector(2 downto 0);
86 TS : out std_logic_vector(2 downto 0);
87 IntCycle_n : out std_logic;
88 IntE : out std_logic;
89 Stop : out std_logic
90 );
91 end component;
92
93 component T80_Reg
94 port(
95 Clk : in std_logic;
96 CEN : in std_logic;
97 WEH : in std_logic;
98 WEL : in std_logic;
99 AddrA : in std_logic_vector(2 downto 0);
100 AddrB : in std_logic_vector(2 downto 0);
101 AddrC : in std_logic_vector(2 downto 0);
102 DIH : in std_logic_vector(7 downto 0);
103 DIL : in std_logic_vector(7 downto 0);
104 DOAH : out std_logic_vector(7 downto 0);
105 DOAL : out std_logic_vector(7 downto 0);
106 DOBH : out std_logic_vector(7 downto 0);
107 DOBL : out std_logic_vector(7 downto 0);
108 DOCH : out std_logic_vector(7 downto 0);
109 DOCL : out std_logic_vector(7 downto 0)
110 );
111 end component;
112
113 component T80_MCode
114 generic(
115 Mode : integer := 0;
116 Flag_C : integer := 0;
117 Flag_N : integer := 1;
118 Flag_P : integer := 2;
119 Flag_X : integer := 3;
120 Flag_H : integer := 4;
121 Flag_Y : integer := 5;
122 Flag_Z : integer := 6;
123 Flag_S : integer := 7
124 );
125 port(
126 IR : in std_logic_vector(7 downto 0);
127 ISet : in std_logic_vector(1 downto 0);
128 MCycle : in std_logic_vector(2 downto 0);
129 F : in std_logic_vector(7 downto 0);
130 NMICycle : in std_logic;
131 IntCycle : in std_logic;
132 MCycles : out std_logic_vector(2 downto 0);
133 TStates : out std_logic_vector(2 downto 0);
134 Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
135 Inc_PC : out std_logic;
136 Inc_WZ : out std_logic;
137 IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
138 Read_To_Reg : out std_logic;
139 Read_To_Acc : out std_logic;
140 Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
141 Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
142 ALU_Op : out std_logic_vector(3 downto 0);
143 -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
144 Save_ALU : out std_logic;
145 PreserveC : out std_logic;
146 Arith16 : out std_logic;
147 Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
148 IORQ : out std_logic;
149 Jump : out std_logic;
150 JumpE : out std_logic;
151 JumpXY : out std_logic;
152 Call : out std_logic;
153 RstP : out std_logic;
154 LDZ : out std_logic;
155 LDW : out std_logic;
156 LDSPHL : out std_logic;
157 Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
158 ExchangeDH : out std_logic;
159 ExchangeRp : out std_logic;
160 ExchangeAF : out std_logic;
161 ExchangeRS : out std_logic;
162 I_DJNZ : out std_logic;
163 I_CPL : out std_logic;
164 I_CCF : out std_logic;
165 I_SCF : out std_logic;
166 I_RETN : out std_logic;
167 I_BT : out std_logic;
168 I_BC : out std_logic;
169 I_BTR : out std_logic;
170 I_RLD : out std_logic;
171 I_RRD : out std_logic;
172 I_INRC : out std_logic;
173 SetDI : out std_logic;
174 SetEI : out std_logic;
175 IMode : out std_logic_vector(1 downto 0);
176 Halt : out std_logic;
177 NoRead : out std_logic;
178 Write : out std_logic
179 );
180 end component;
181
182 component T80_ALU
183 generic(
184 Mode : integer := 0;
185 Flag_C : integer := 0;
186 Flag_N : integer := 1;
187 Flag_P : integer := 2;
188 Flag_X : integer := 3;
189 Flag_H : integer := 4;
190 Flag_Y : integer := 5;
191 Flag_Z : integer := 6;
192 Flag_S : integer := 7
193 );
194 port(
195 Arith16 : in std_logic;
196 Z16 : in std_logic;
197 ALU_Op : in std_logic_vector(3 downto 0);
198 IR : in std_logic_vector(5 downto 0);
199 ISet : in std_logic_vector(1 downto 0);
200 BusA : in std_logic_vector(7 downto 0);
201 BusB : in std_logic_vector(7 downto 0);
202 F_In : in std_logic_vector(7 downto 0);
203 Q : out std_logic_vector(7 downto 0);
204 F_Out : out std_logic_vector(7 downto 0)
205 );
206 end component;
207
208end;
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