projects / fpga-games / blame
| Commit | Line | Data |
|---|---|---|
| 782690d0 MG |
1 | //===============================================================================\r |
| 2 | // FPGA MOONCRESTA T80_IP I/F\r | |
| 3 | //\r | |
| 4 | // Version : 1.00\r | |
| 5 | //\r | |
| 6 | // Copyright(c) 2004 Katsumi Degawa , All rights reserved\r | |
| 7 | //\r | |
| 8 | // Important !\r | |
| 9 | //\r | |
| 10 | // This program is freeware for non-commercial use. \r | |
| 11 | // An author does no guarantee about this program.\r | |
| 12 | // You can use this under your own risk.\r | |
| 13 | // \r | |
| 14 | //================================================================================\r | |
| 15 | \r | |
| 16 | module Z80IP(\r | |
| 17 | \r | |
| 18 | ADRS,\r | |
| 19 | DINP,\r | |
| 20 | DOUT,\r | |
| 21 | BUSWO,\r | |
| 22 | RESET_N,\r | |
| 23 | INT_N,\r | |
| 24 | NMI_N,\r | |
| 25 | WAIT_N,\r | |
| 26 | M1_N,\r | |
| 27 | MREQ_N,\r | |
| 28 | IORQ_N,\r | |
| 29 | RD_N, \r | |
| 30 | WR_N,\r | |
| 31 | RFSH_N,\r | |
| 32 | HALT_N,\r | |
| 33 | CLK\r | |
| 34 | \r | |
| 35 | );\r | |
| 36 | \r | |
| 37 | // I/O assign\r | |
| 38 | output [15:0]ADRS;\r | |
| 39 | input [7:0] DINP;\r | |
| 40 | output [7:0] DOUT;\r | |
| 41 | input RESET_N,INT_N,NMI_N,WAIT_N,CLK;\r | |
| 42 | output M1_N,MREQ_N,IORQ_N,RD_N,WR_N,RFSH_N,HALT_N,BUSWO;\r | |
| 43 | \r | |
| 44 | // Z80IP interface\r | |
| 45 | T80as z80core (\r | |
| 46 | \r | |
| 47 | .RESET_n(RESET_N),\r | |
| 48 | .CLK_n(CLK),\r | |
| 49 | .WAIT_n(WAIT_N),\r | |
| 50 | .INT_n(INT_N),\r | |
| 51 | .NMI_n(NMI_N),\r | |
| 52 | .BUSRQ_n(1'b1),\r | |
| 53 | .M1_n(M1_N),\r | |
| 54 | .MREQ_n(MREQ_N),\r | |
| 55 | .IORQ_n(IORQ_N),\r | |
| 56 | .RD_n(RD_N),\r | |
| 57 | .WR_n(WR_N),\r | |
| 58 | .RFSH_n(RFSH_N),\r | |
| 59 | .HALT_n(HALT_N),\r | |
| 60 | .BUSAK_n(),\r | |
| 61 | .A(ADRS),\r | |
| 62 | .DI(DINP),\r | |
| 63 | .DO(DOUT),\r | |
| 64 | .DOE(BUSWO)\r | |
| 65 | \r | |
| 66 | );\r | |
| 67 | \r | |
| 68 | endmodule\r | |
| 69 | \r |