fix rom address decoder
[fpga-games] / galaxian / src / roms.v
CommitLineData
782690d0 1module galaxian_roms(
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2I_CLK_12M,
3I_ADDR,
4O_DATA
5);
6
7input I_CLK_12M;
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8input [18:0]I_ADDR;
9output [7:0]O_DATA;
10
11//CPU-Roms
12wire [7:0]U_ROM_D;
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13
14GALAXIAN_U U_ROM(
15.CLK(I_CLK_12M),
b884ab49 16.ADDR(I_ADDR[10:0]),
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17.DATA(U_ROM_D),
18.ENA(1'b1)
19);
20
21wire [7:0]V_ROM_D;
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22
23GALAXIAN_V V_ROM(
24.CLK(I_CLK_12M),
b884ab49 25.ADDR(I_ADDR[10:0]),
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26.DATA(V_ROM_D),
27.ENA(1'b1)
28);
29
30wire [7:0]W_ROM_D;
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31
32GALAXIAN_W W_ROM(
33.CLK(I_CLK_12M),
b884ab49 34.ADDR(I_ADDR[10:0]),
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35.DATA(W_ROM_D),
36.ENA(1'b1)
37);
38
39wire [7:0]Y_ROM_D;
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MG
40
41GALAXIAN_Y Y_ROM(
ead9ca4c 42.CLK(I_CLK_12M),
b884ab49 43.ADDR(I_ADDR[10:0]),
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44.DATA(Y_ROM_D),
45.ENA(1'b1)
46);
47
48//7L CPU-Rom
49wire [7:0]L_ROM_D;
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50
51GALAXIAN_7L L_ROM(
ead9ca4c 52.CLK(I_CLK_12M),
b884ab49 53.ADDR(I_ADDR[10:0]),
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54.DATA(L_ROM_D),
55.ENA(1'b1)
56);
57
58//1K VID-Rom
59wire [7:0]K_ROM_D;
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60
61GALAXIAN_1K K_ROM(
ead9ca4c 62.CLK(I_CLK_12M),
b884ab49 63.ADDR(I_ADDR[10:0]),
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64.DATA(K_ROM_D),
65.ENA(1'b1)
66);
67
68//1H VID-Rom
69wire [7:0]H_ROM_D;
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70
71GALAXIAN_1H H_ROM(
ead9ca4c 72.CLK(I_CLK_12M),
b884ab49 73.ADDR(I_ADDR[10:0]),
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74.DATA(H_ROM_D),
75.ENA(1'b1)
76);
77
78reg [7:0]DATA_OUT;
79
80// address map
81//--------------------------------------------------
82// 0x00000 - 0x007FF galmidw.u CPU-ROM
83// 0x00800 - 0x00FFF galmidw.v CPU-ROM
84// 0x01000 - 0x017FF galmidw.w CPU-ROM
85// 0x01800 - 0x01FFF galmidw.y CPU-ROM
86// 0x02000 - 0x027FF 7l CPU-ROM
87// 0x04000 - 0x047FF 1k.bin VID-ROM
88// 0x05000 - 0x057FF 1h.bin VID-ROM
89// 0x10000 - 0x3FFFF mc_wav_2.bin Sound(Wav)Data
b884ab49 90always@(I_ADDR or U_ROM_D or V_ROM_D or W_ROM_D or Y_ROM_D or L_ROM_D or K_ROM_D or H_ROM_D)
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91begin
92 if (I_ADDR <= 18'h7ff) begin
93 //u
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94 DATA_OUT <= U_ROM_D;
95 end
b884ab49 96 else if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
782690d0 97 //v
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98 DATA_OUT <= V_ROM_D;
99 end
b884ab49 100 else if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
782690d0 101 //w
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102 DATA_OUT <= W_ROM_D;
103 end
b884ab49 104 else if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
782690d0 105 //y
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106 DATA_OUT <= Y_ROM_D;
107 end
b884ab49 108 else if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
782690d0 109 //7l
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110 DATA_OUT <= L_ROM_D;
111 end
b884ab49 112 else if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
782690d0 113 //1k
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114 DATA_OUT <= K_ROM_D;
115 end
b884ab49 116 else if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
782690d0 117 //1h
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118 DATA_OUT <= H_ROM_D;
119 end
b884ab49 120 else if (I_ADDR >= 18'h10000 && I_ADDR <= 18'h3fff) begin
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121 //sound
122 DATA_OUT <= 8'h00;
123 end
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124 else begin
125 DATA_OUT <= 8'h00;
126 end
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127end
128
129assign O_DATA = DATA_OUT;
130
131endmodule
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