fix rom clock
[fpga-games] / galaxian / src / roms.v
CommitLineData
782690d0
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1module galaxian_roms(
2I_CLK_18432M,
3I_CLK_12M,
4I_ADDR,
5O_DATA
6);
7
8input I_CLK_12M;
9input I_CLK_18432M;
10input [18:0]I_ADDR;
11output [7:0]O_DATA;
12
13//CPU-Roms
14wire [7:0]U_ROM_D;
15reg [10:0]U_ROM_A;
16
17GALAXIAN_U U_ROM(
18.CLK(I_CLK_12M),
19.ADDR(U_ROM_A),
20.DATA(U_ROM_D),
21.ENA(1'b1)
22);
23
24wire [7:0]V_ROM_D;
25reg [10:0]V_ROM_A;
26
27GALAXIAN_V V_ROM(
28.CLK(I_CLK_12M),
29.ADDR(V_ROM_A),
30.DATA(V_ROM_D),
31.ENA(1'b1)
32);
33
34wire [7:0]W_ROM_D;
35reg [10:0]W_ROM_A;
36
37GALAXIAN_W W_ROM(
38.CLK(I_CLK_12M),
39.ADDR(W_ROM_A),
40.DATA(W_ROM_D),
41.ENA(1'b1)
42);
43
44wire [7:0]Y_ROM_D;
45reg [10:0]Y_ROM_A;
46
47GALAXIAN_Y Y_ROM(
ead9ca4c 48.CLK(I_CLK_12M),
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49.ADDR(Y_ROM_A),
50.DATA(Y_ROM_D),
51.ENA(1'b1)
52);
53
54//7L CPU-Rom
55wire [7:0]L_ROM_D;
56reg [10:0]L_ROM_A;
57
58GALAXIAN_7L L_ROM(
ead9ca4c 59.CLK(I_CLK_12M),
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60.ADDR(L_ROM_A),
61.DATA(L_ROM_D),
62.ENA(1'b1)
63);
64
65//1K VID-Rom
66wire [7:0]K_ROM_D;
67reg [10:0]K_ROM_A;
68
69GALAXIAN_1K K_ROM(
ead9ca4c 70.CLK(I_CLK_12M),
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71.ADDR(K_ROM_A),
72.DATA(K_ROM_D),
73.ENA(1'b1)
74);
75
76//1H VID-Rom
77wire [7:0]H_ROM_D;
78reg [10:0]H_ROM_A;
79
80GALAXIAN_1H H_ROM(
ead9ca4c 81.CLK(I_CLK_12M),
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82.ADDR(H_ROM_A),
83.DATA(H_ROM_D),
84.ENA(1'b1)
85);
86
87reg [7:0]DATA_OUT;
88
89// address map
90//--------------------------------------------------
91// 0x00000 - 0x007FF galmidw.u CPU-ROM
92// 0x00800 - 0x00FFF galmidw.v CPU-ROM
93// 0x01000 - 0x017FF galmidw.w CPU-ROM
94// 0x01800 - 0x01FFF galmidw.y CPU-ROM
95// 0x02000 - 0x027FF 7l CPU-ROM
96// 0x04000 - 0x047FF 1k.bin VID-ROM
97// 0x05000 - 0x057FF 1h.bin VID-ROM
98// 0x10000 - 0x3FFFF mc_wav_2.bin Sound(Wav)Data
ead9ca4c 99always
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100begin
101 if (I_ADDR <= 18'h7ff) begin
102 //u
103 U_ROM_A <= I_ADDR[10:0];
104 DATA_OUT <= U_ROM_D;
105 end
ead9ca4c 106 if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
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107 //v
108 V_ROM_A <= I_ADDR[10:0];
109 DATA_OUT <= V_ROM_D;
110 end
ead9ca4c 111 if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
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112 //w
113 W_ROM_A <= I_ADDR[10:0];
114 DATA_OUT <= W_ROM_D;
115 end
ead9ca4c 116 if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
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117 //y
118 Y_ROM_A <= I_ADDR[10:0];
119 DATA_OUT <= Y_ROM_D;
120 end
ead9ca4c 121 if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
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122 //7l
123 L_ROM_A <= I_ADDR[10:0];
124 DATA_OUT <= L_ROM_D;
125 end
ead9ca4c 126 if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
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127 //1k
128 K_ROM_A <= I_ADDR[10:0];
129 DATA_OUT <= K_ROM_D;
130 end
ead9ca4c 131 if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
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132 //1h
133 H_ROM_A <= I_ADDR[10:0];
134 DATA_OUT <= H_ROM_D;
135 end
136end
137
138assign O_DATA = DATA_OUT;
139
140endmodule
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