| | 1 | CONFIG PART = XC3SD1800A-FG676-4; |
| | 2 | |
| | 3 | NET I_CLK_125M TNM_NET = clk_ref_grp; |
| | 4 | TIMESPEC TS01 = PERIOD : clk_ref_grp : 8.00 : PRIORITY 1; #125 MHz |
| | 5 | |
| | 6 | TIMESPEC TS11=FROM:PADS:TO:FFS : 30 ns; |
| | 7 | TIMESPEC TS12=FROM:FFS:TO:PADS : 30 ns; |
| | 8 | |
| | 9 | #---------- MasterClock 18.432MHz ---------- |
| | 10 | NET "I_CLK_125M" LOC = "F13" | IOSTANDARD = LVCMOS33; |
| | 11 | #------------------------------------------- |
| | 12 | #---------- SW I/F ------------------------- |
| | 13 | NET "I_PSW<0>" LOC = "K19" | IOSTANDARD = LVTTL | PULLUP; #up |
| | 14 | NET "I_PSW<1>" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP; #down |
| | 15 | NET "I_PSW<2>" LOC = "G22" | IOSTANDARD = LVTTL | PULLUP; #left |
| | 16 | NET "I_PSW<3>" LOC = "F22" | IOSTANDARD = LVTTL | PULLUP; #right |
| | 17 | NET "I_PSW<4>" LOC = "F23" | IOSTANDARD = LVTTL | PULLUP; #btn |
| | 18 | NET "I_PSW<5>" LOC = "J10" | IOSTANDARD = LVTTL | PULLDOWN; #s8 - s1 |
| | 19 | NET "I_PSW<6>" LOC = "J13" | IOSTANDARD = LVTTL | PULLDOWN; #s7 - c1 |
| | 20 | NET "I_PSW<7>" LOC = "J15" | IOSTANDARD = LVTTL | PULLDOWN; #s6 - s2 |
| | 21 | NET "I_PSW<8>" LOC = "J17" | IOSTANDARD = LVTTL | PULLDOWN; #s5 - c2 |
| | 22 | #------------------------------------------- |
| | 23 | #--------- EEPROM I/F ---------------------- |
| | 24 | #NET "I_ROM_DB<0>" LOC = "P70"; |
| | 25 | #NET "I_ROM_DB<1>" LOC = "P68"; |
| | 26 | #NET "I_ROM_DB<2>" LOC = "P63"; |
| | 27 | #NET "I_ROM_DB<3>" LOC = "P58"; |
| | 28 | #NET "I_ROM_DB<4>" LOC = "P60"; |
| | 29 | #NET "I_ROM_DB<5>" LOC = "P62"; |
| | 30 | #NET "I_ROM_DB<6>" LOC = "P57"; |
| | 31 | #NET "I_ROM_DB<7>" LOC = "P59"; |
| | 32 | #NET "O_ROM_AB<0>" LOC = "P71"; |
| | 33 | #NET "O_ROM_AB<1>" LOC = "P74"; |
| | 34 | #NET "O_ROM_AB<2>" LOC = "P73"; |
| | 35 | #NET "O_ROM_AB<3>" LOC = "P75"; |
| | 36 | #NET "O_ROM_AB<4>" LOC = "P81"; |
| | 37 | #NET "O_ROM_AB<5>" LOC = "P82"; |
| | 38 | #NET "O_ROM_AB<6>" LOC = "P84"; |
| | 39 | #NET "O_ROM_AB<7>" LOC = "P86"; |
| | 40 | #NET "O_ROM_AB<8>" LOC = "P89"; |
| | 41 | #NET "O_ROM_AB<9>" LOC = "P87"; |
| | 42 | #NET "O_ROM_AB<10>" LOC = "P64"; |
| | 43 | #NET "O_ROM_AB<11>" LOC = "P83"; |
| | 44 | #NET "O_ROM_AB<12>" LOC = "P88"; |
| | 45 | #NET "O_ROM_AB<13>" LOC = "P95"; |
| | 46 | #NET "O_ROM_AB<14>" LOC = "P97"; |
| | 47 | #NET "O_ROM_AB<15>" LOC = "P93"; |
| | 48 | #NET "O_ROM_AB<16>" LOC = "P96"; |
| | 49 | #NET "O_ROM_AB<17>" LOC = "P98"; |
| | 50 | #NET "O_ROM_AB<18>" LOC = "P94"; |
| | 51 | #NET "O_ROM_CSn" LOC = "P61"; |
| | 52 | #NET "O_ROM_OEn" LOC = "P69"; |
| | 53 | #NET "O_ROM_WEn" LOC = "P100"; |
| | 54 | #------------------------------------------- |
| | 55 | #--------- SOUND I/F ----------------------- |
| | 56 | NET "O_SOUND_OUT_L" LOC = "AA22" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; |
| | 57 | NET "O_SOUND_OUT_R" LOC = "V19" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; |
| | 58 | #------------------------------------------- |
| | 59 | #--------- VIDEO I/F ----------------------- |
| | 60 | NET "O_VGA_R<2>" LOC = "K20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
| | 61 | NET "O_VGA_R<1>" LOC = "F25" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
| | 62 | NET "O_VGA_R<0>" LOC = "F24" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
| | 63 | NET "O_VGA_G<2>" LOC = "M18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
| | 64 | NET "O_VGA_G<1>" LOC = "J23" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
| | 65 | NET "O_VGA_G<0>" LOC = "J22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
| | 66 | NET "O_VGA_B<1>" LOC = "G23" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
| | 67 | NET "O_VGA_B<0>" LOC = "G24" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
| | 68 | |
| | 69 | NET "O_VGA_H_SYNCn" LOC = "K26" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
| | 70 | NET "O_VGA_V_SYNCn" LOC = "K25" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; |
| | 71 | |
| | 72 | |
| | 73 | #------------------------------------------- |
| | 74 | # |
| | 75 | #---------- Build-in ROM ------------------------------------------------------------------------------- |
| | 76 | #INST "col_rom00" INIT_00 = c6077600f007f6000700000007a0c00007c4c0003f07d8003fc01600f6000000; |
projects / fpga-games / blame_incremental