git.zerfleddert.de Git - fpga-games/blob - galaxian/src/mc_bram_if.v

   1 //===============================================================================
   2 // FPGA MOONCRESTA & GALAXIAN
   3 //      FPGA BLOCK RAM I/F (ALTERA-CYCLONE & XILINX SPARTAN2E)
   4 //
   5 // Version : 2.50
   6 //
   7 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
   8 //
   9 // Important !
  10 //
  11 // This program is freeware for non-commercial use.
  12 // An author does no guarantee about this program.
  13 // You can use this under your own risk.
  14 //
  15 // mc_col_rom(6L) added by k.Degawa
  16 //
  17 // 2004- 5- 6  first release.
  18 // 2004- 8-23  Improvement with T80-IP.    K.Degawa
  19 // 2004- 9-18  added Xilinx Device         K.Degawa
  20 //================================================================================
  21 `include "src/mc_conf.v"
  22
  23 //  mc_top.v use
  24 module mc_cpu_ram (
  25
  26 I_CLK,
  27 I_ADDR,
  28 I_D,
  29 I_WE,
  30 I_OE,
  31 O_D
  32
  33 );
  34
  35 input  I_CLK;
  36 input  [9:0]I_ADDR;
  37 input  [7:0]I_D;
  38 input  I_WE;
  39 input  I_OE;
  40 output [7:0]O_D;
  41
  42 wire   [7:0]W_D;
  43 assign O_D = I_OE ? W_D : 8'h00 ;
  44
  45 `ifdef DEVICE_CYCLONE
  46 alt_ram_1024_8 CPURAM_ALT(
  47
  48 .clock(I_CLK),
  49 .address(I_ADDR),
  50 .data(I_D),
  51 .wren(I_WE),
  52 .q(W_D)
  53
  54 );
  55 `endif
  56 `ifdef DEVICE_SPARTAN2E
  57 RAMB4_S4 CPURAM_X1(
  58
  59 .CLK(I_CLK),
  60 .ADDR(I_ADDR[9:0]),
  61 .DI(I_D[7:4]),
  62 .DO(W_D[7:4]),
  63 .EN(1'b1),
  64 .WE(I_WE),
  65 .RST(1'b0)
  66
  67 );
  68
  69 RAMB4_S4 CPURAM_X0(
  70
  71 .CLK(I_CLK),
  72 .ADDR(I_ADDR[9:0]),
  73 .DI(I_D[3:0]),
  74 .DO(W_D[3:0]),
  75 .EN(1'b1),
  76 .WE(I_WE),
  77 .RST(1'b0)
  78
  79 );
  80 `endif
  81
  82 endmodule
  83
  84 //  mc_video.v use
  85 module mc_obj_ram(
  86
  87 I_CLKA,
  88 I_ADDRA,
  89 I_WEA,
  90 I_CEA,
  91 I_DA,
  92 O_DA,
  93
  94 I_CLKB,
  95 I_ADDRB,
  96 I_WEB,
  97 I_CEB,
  98 I_DB,
  99 O_DB
 100
 101 );
 102
 103 input  I_CLKA,I_CLKB;
 104 input  [7:0]I_ADDRA,I_ADDRB;
 105 input  I_WEA,I_WEB;
 106 input  I_CEA,I_CEB;
 107 input  [7:0]I_DA,I_DB;
 108 output [7:0]O_DA,O_DB;
 109
 110 `ifdef DEVICE_CYCLONE
 111 alt_ram_256_8_8 OBJRAM(
 112
 113 .clock_a(I_CLKA),
 114 .address_a(I_ADDRA),
 115 .wren_a(I_WEA),
 116 .enable_a(I_CEA),
 117 .data_a(I_DA),
 118 .q_a(O_DA),
 119
 120 .clock_b(I_CLKB),
 121 .address_b(I_ADDRB),
 122 .wren_b(I_WEB),
 123 .enable_b(I_CEB),
 124 .data_b(I_DB),
 125 .q_b(O_DB)
 126
 127 );
 128 `endif
 129 `ifdef DEVICE_SPARTAN2E
 130 RAMB4_S8_S8 OBJRAM(
 131
 132 .CLKA(I_CLKA),
 133 .ADDRA({1'b0,I_ADDRA[7:0]}),
 134 .DIA(I_DA),
 135 .DOA(O_DA),
 136 .ENA(I_CEA),
 137 .WEA(I_WEA),
 138 .RSTA(1'b0),
 139
 140 .CLKB(I_CLKB),
 141 .ADDRB({1'b0,I_ADDRB[7:0]}),
 142 .DIB(I_DB),
 143 .DOB(O_DB),
 144 .ENB(I_CEB),
 145 .WEB(I_WEB),
 146 .RSTB(1'b0)
 147 );
 148 `endif
 149
 150 endmodule
 151
 152
 153 //  mc_video.v use
 154 module mc_vid_ram (
 155
 156 I_CLKA,
 157 I_ADDRA,
 158 I_DA,
 159 I_WEA,
 160 I_CEA,
 161 O_DA,
 162
 163 I_CLKB,
 164 I_ADDRB,
 165 I_DB,
 166 I_WEB,
 167 I_CEB,
 168 O_DB
 169
 170 );
 171
 172 input  I_CLKA,I_CLKB;
 173 input  [9:0]I_ADDRA,I_ADDRB;
 174 input  [7:0]I_DA,I_DB;
 175 input  I_WEA,I_WEB;
 176 input  I_CEA,I_CEB;
 177 output [7:0]O_DA,O_DB;
 178
 179 `ifdef DEVICE_CYCLONE
 180 alt_ram_1024_8_8 VIDRAM(
 181
 182 .clock_a(I_CLKA),
 183 .address_a(I_ADDRA),
 184 .data_a(I_DA),
 185 .wren_a(I_WEA),
 186 .enable_a(I_CEA),
 187 .q_a(O_DA),
 188
 189 .clock_b(I_CLKB),
 190 .address_b(I_ADDRB),
 191 .data_b(I_DB),
 192 .wren_b(I_WEB),
 193 .enable_b(I_CEB),
 194 .q_b(O_DB)
 195
 196 );
 197 `endif
 198 `ifdef DEVICE_SPARTAN2E
 199 RAMB4_S4_S4 VIDRAM_X1(
 200
 201 .CLKA(I_CLKA),
 202 .ADDRA(I_ADDRA[9:0]),
 203 .DIA(I_DA[7:4]),
 204 .DOA(O_DA[7:4]),
 205 .ENA(I_CEA),
 206 .WEA(I_WEA),
 207 .RSTA(1'b0),
 208
 209 .CLKB(I_CLKB),
 210 .ADDRB(I_ADDRB[9:0]),
 211 .DIB(I_DB[7:4]),
 212 .DOB(O_DB[7:4]),
 213 .ENB(I_CEB),
 214 .WEB(I_WEB),
 215 .RSTB(1'b0)
 216
 217 );
 218
 219 RAMB4_S4_S4 VIDRAM_X0(
 220
 221 .CLKA(I_CLKA),
 222 .ADDRA(I_ADDRA[9:0]),
 223 .DIA(I_DA[3:0]),
 224 .DOA(O_DA[3:0]),
 225 .ENA(I_CEA),
 226 .WEA(I_WEA),
 227 .RSTA(1'b0),
 228
 229 .CLKB(I_CLKB),
 230 .ADDRB(I_ADDRB[9:0]),
 231 .DIB(I_DB[3:0]),
 232 .DOB(O_DB[3:0]),
 233 .ENB(I_CEB),
 234 .WEB(I_WEB),
 235 .RSTB(1'b0)
 236
 237 );
 238 `endif
 239
 240 endmodule
 241
 242 //  mc_video.v use
 243 module mc_lram(
 244
 245 I_CLK,
 246 I_ADDR,
 247 I_WE,
 248 I_D,
 249 O_Dn
 250
 251 );
 252
 253 input  I_CLK;
 254 input  [7:0]I_ADDR;
 255 input  [4:0]I_D;
 256 input  I_WE;
 257 output [4:0]O_Dn;
 258 wire   [4:0]W_D;
 259
 260 `ifdef DEVICE_CYCLONE
 261 assign O_Dn = ~W_D;
 262
 263 alt_ram_256_5 LRAM(
 264
 265 .inclock(I_CLK),
 266 .outclock(~I_CLK),
 267 .address(I_ADDR),
 268 .data(I_D),
 269 .wren(~I_WE),
 270 .q(W_D)
 271
 272 );
 273 `endif
 274 `ifdef DEVICE_SPARTAN2E
 275 reg    [4:0]O_Dn;
 276 always@(negedge I_CLK) O_Dn <= ~W_D[4:0] ;
 277
 278 RAMB4_S8 LRAM(
 279
 280 .CLK(I_CLK),
 281 .ADDR({1'b0,I_ADDR[7:0]}),
 282 .DI({3'b000,I_D}),
 283 .DO(W_D),
 284 .EN(1'b1),
 285 .WE(~I_WE),
 286 .RST(1'b0)
 287
 288 );
 289 `endif
 290
 291 endmodule
 292
 293 //  mc_col_pal.v use
 294 `ifdef DEVICE_CYCLONE
 295 module mc_col_rom(
 296
 297 I_CLK,
 298 I_ADDR,
 299 I_OEn,
 300 O_DO
 301
 302 );
 303
 304 input   I_CLK;
 305 input   [4:0]I_ADDR;
 306 input   I_OEn;
 307 output  [7:0]O_DO;
 308 wire    [7:0]W_DO;
 309
 310 assign  O_DO = I_OEn ? 8'h00 : W_DO ;
 311 alt_rom_6l U_6L(
 312
 313 .clock(I_CLK),
 314 .address(I_ADDR),
 315 .q(W_DO)
 316
 317 );
 318
 319
 320 endmodule
 321 `endif