1 //===============================================================================
6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
10 // This program is freeware for non-commercial use.
11 // An author does no guarantee about this program.
12 // You can use this under your own risk.
14 // 2004- 4-30 galaxian modify by K.DEGAWA
15 // 2004- 5- 6 first release.
16 // 2004- 8-23 Improvement with T80-IP.
17 // 2004- 9-18 The description of ALTERA(CYCLONE) and XILINX(SPARTAN2E) was made one.
18 // 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
19 //================================================================================
21 `include "src/mc_conf.v"
66 wire W_CPU_HRDWR_RESETn;
73 output psTXD,psCLK,psSEL;
90 wire W_RESETn = |(~I_PSW[8:5]);
91 //------ CLOCK GEN ---------------------------
94 wire W_CLK_12M,WB_CLK_12M;
95 wire W_CLK_6M,WB_CLK_6M;
99 .CLKIN_IN(I_CLK_125M),
101 .CLKFX_OUT(W_CLK_36M)
104 //------ H&V COUNTER -------------------------
113 //------ CPU RAM ----------------------------
114 wire [7:0]W_CPU_RAM_DO;
116 //------ ADDRESS DECDER ----------------------
138 wire W_VID_RDn = W_OBJ_RAM_RDn & W_VID_RAM_RDn ;
139 wire W_SW_OEn = W_SW0_OEn & W_SW1_OEn & W_DIP_OEn ;
140 //------- INPORT -----------------------------
142 //------- VIDEO -----------------------------
144 //--------------------------------------------
148 .I_CLK_36M(W_CLK_36M),
149 .O_CLK_18M(W_CLK_18M),
150 .O_CLK_12M(WB_CLK_12M),
151 .O_CLK_06M(WB_CLK_6M)
155 `ifdef DEVICE_CYCLONE
156 assign W_CLK_12M = WB_CLK_12M;
157 assign W_CLK_6M = WB_CLK_6M;
159 `ifdef DEVICE_SPARTAN2E
160 BUFG BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) );
161 BUFG BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) );
163 //--- DATA I/F -------------------------------------
164 reg [7:0]W_CPU_ROM_DO;
165 wire [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;
167 wire [7:0]W_BDO = W_SW_DO | W_VID_DO | W_CPU_RAM_DO | W_CPU_ROM_DOB ;
170 //--- CPU I/F -------------------------------------
172 always@(posedge W_H_CNT[0] or negedge W_RESETn)
174 if(! W_RESETn) rst_count <= 0;
177 rst_count <= rst_count;
179 rst_count <= rst_count+1;
183 assign W_CPU_RESETn = W_RESETn;
184 assign W_CPU_CLK = W_H_CNT[0];
189 .RESET_N(W_CPU_RESETn),
196 .MREQ_N(W_CPU_MREQn),
200 .WAIT_N(W_CPU_WAITn),
202 .RFSH_N(W_CPU_RFSHn),
207 wire W_CPU_RAM_CLK = W_CLK_12M & ~W_CPU_RAM_CSn;
209 mc_cpu_ram MC_CPU_RAM(
211 .I_CLK(W_CPU_RAM_CLK),
215 .I_OE(~W_CPU_RAM_RDn ),
223 .I_CLK_12M(W_CLK_12M),
225 .I_CPU_CLK(W_H_CNT[0]),
230 .I_MREQn(W_CPU_MREQn),
231 .I_RFSHn(W_CPU_RFSHn),
237 .O_WAITn(W_CPU_WAITn),
239 .O_CPU_ROM_CSn(W_CPU_ROM_CSn),
240 .O_CPU_RAM_RDn(W_CPU_RAM_RDn),
241 .O_CPU_RAM_WRn(W_CPU_RAM_WRn),
242 .O_CPU_RAM_CSn(W_CPU_RAM_CSn),
243 .O_OBJ_RAM_RDn(W_OBJ_RAM_RDn),
244 .O_OBJ_RAM_WRn(W_OBJ_RAM_WRn),
245 .O_OBJ_RAM_RQn(W_OBJ_RAM_RQn),
246 .O_VID_RAM_RDn(W_VID_RAM_RDn),
247 .O_VID_RAM_WRn(W_VID_RAM_WRn),
248 .O_SW0_OEn(W_SW0_OEn),
249 .O_SW1_OEn(W_SW1_OEn),
250 .O_DIP_OEn(W_DIP_OEn),
251 .O_WDR_OEn(W_WDR_OEn),
252 .O_LAMP_WEn(W_LAMP_WEn),
253 .O_SOUND_WEn(W_SOUND_WEn),
258 .O_STARS_ON(W_STARS_ON)
262 //-------- SOUND I/F -----------------------------
263 //--- Parts 9L ---------
265 always@(posedge W_CLK_12M or negedge W_RESETn)
267 if(W_RESETn == 1'b0)begin
271 if(W_SOUND_WEn == 1'b0)begin
273 3'h0 : W_9L_Q[0] <= W_BDI[0];
274 3'h1 : W_9L_Q[1] <= W_BDI[0];
275 3'h2 : W_9L_Q[2] <= W_BDI[0];
276 3'h3 : W_9L_Q[3] <= W_BDI[0];
277 3'h4 : W_9L_Q[4] <= W_BDI[0];
278 3'h5 : W_9L_Q[5] <= W_BDI[0];
279 3'h6 : W_9L_Q[6] <= W_BDI[0];
280 3'h7 : W_9L_Q[7] <= W_BDI[0];
285 wire W_VOL1 = W_9L_Q[6];
286 wire W_VOL2 = W_9L_Q[7];
287 wire W_FIRE = W_9L_Q[5];
288 wire W_HIT = W_9L_Q[3];
289 wire W_FS3 = W_9L_Q[2];
290 wire W_FS2 = W_9L_Q[1];
291 wire W_FS1 = W_9L_Q[0];
292 //---------------------------------------------------
293 //---- CPU DATA WATCH -------------------------------
294 wire ZMWR = W_CPU_MREQn | W_CPU_WRn ;
297 always @(posedge W_CPU_CLK)
300 if(W_A == 16'h4007)begin
306 if(W_A == 16'h4005)begin
307 if(W_BDI == 8'h03 || W_BDI == 8'h04 )
317 always @(posedge W_CPU_CLK)
320 if(W_A == 16'h4206)begin
328 //---- PS_PAD Interface -----------------------------
330 wire VIB_SW = died & (&on_game[1:0]);
332 fpga_arcade_if pspad(
334 .CLK_18M432(W_CLK_18M),
345 //---- SW Interface ---------------------------------
347 wire L1 = I_PSW[2] & ps_PSW[2];
348 wire R1 = I_PSW[3] & ps_PSW[3];
351 wire J1 = I_PSW[4] & ps_PSW[8];
353 wire S1 = (U1|J1) & ps_PSW[6];
354 wire S2 = (D1|J1) & ps_PSW[7];
356 wire C1 = (L1|R1|U1|~D1) & ps_PSW[4];
358 wire L1 = ! I_PSW[2];
359 wire R1 = ! I_PSW[3];
360 wire U1 = ! I_PSW[0];
361 wire D1 = ! I_PSW[1];
362 wire J1 = ! I_PSW[4];
364 wire S1 = ! I_PSW[5];
365 wire S2 = ! I_PSW[7];
367 wire C1 = ! I_PSW[6];
369 wire C2 = ! I_PSW[8];
379 .I_COIN1(~C1), // ACTIVE HI
380 .I_COIN2(~C2), // ACTIVE HI
381 .I_1P_LE(~L1), // ACTIVE HI
382 .I_1P_RI(~R1), // ACTIVE HI
383 .I_1P_SH(~J1), // ACTIVE HI
384 .I_2P_LE(~L2), // ACTIVE HI
385 .I_2P_RI(~R2), // ACTIVE HI
386 .I_2P_SH(~J2), // ACTIVE HI
387 .I_1P_START(~S1), // ACTIVE HI
388 .I_2P_START(~S2), // ACTIVE HI
390 .I_SW0_OEn(W_SW0_OEn),
391 .I_SW1_OEn(W_SW1_OEn),
392 .I_DIP_OEn(W_DIP_OEn),
398 //-----------------------------------------------------------------------------
399 //------- ROM -------------------------------------------------------
402 wire [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;
403 reg [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;
408 .I_ROM_CLK(W_CLK_12M),
409 .I_ADDR({3'h0,W_A[15:0]}),
413 always@(posedge W_CLK_12M)
415 W_CPU_ROM_DO <= ROM_D;
418 //-----------------------------------------------------------------------------
438 //------ VIDEO -----------------------------
449 .I_CLK_18M(W_CLK_18M),
450 .I_CLK_12M(W_CLK_12M),
460 .I_OBJ_SUB_A(3'b000),
462 .I_OBJ_RAM_RQn(W_OBJ_RAM_RQn),
463 .I_OBJ_RAM_RDn(W_OBJ_RAM_RDn),
464 .I_OBJ_RAM_WRn(W_OBJ_RAM_WRn),
465 .I_VID_RAM_RDn(W_VID_RAM_RDn),
466 .I_VID_RAM_WRn(W_VID_RAM_WRn),
472 .O_MISSILEn(W_MISSILEn),
486 mc_col_pal MC_COL_PAL(
488 .I_CLK_12M(W_CLK_12M),
495 .O_STARS_OFFn(W_STARS_OFFn),
508 .I_CLK_18M(W_CLK_18M),
509 `ifdef DEVICE_CYCLONE
510 .I_CLK_6M(~WB_CLK_6M),
512 `ifdef DEVICE_SPARTAN2E
513 .I_CLK_6M(WB_CLK_6M),
521 .I_STARS_ON(W_STARS_ON),
522 .I_STARS_OFFn(W_STARS_OFFn),
544 .I_C_BLnXX(~W_C_BLX),
545 .I_C_BLX(W_C_BLX | ~W_V_BL2n),
546 .I_MISSILEn(W_MISSILEn),
574 .O_H_SYNCn(O_VGA_H_SYNCn),
575 .O_V_SYNCn(O_VGA_V_SYNCn)
581 assign W_VGA_R[2:0] = W_R;
583 assign W_VGA_G[2:0] = W_G;
585 assign W_VGA_B[1:0] = W_B;
587 //assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ; // AKIDUKI LCD USED
588 assign O_VGA_H_SYNCn = ~W_H_SYNC ;
589 assign O_VGA_V_SYNCn = ~W_V_SYNC ;
593 assign O_VGA_R[3:0] = {W_VGA_R[0], W_VGA_R[1], W_VGA_R[2], 1'b0};
595 assign O_VGA_G[3:0] = {W_VGA_G[0], W_VGA_G[1], W_VGA_G[2], 1'b0};
597 assign O_VGA_B[3:0] = {W_VGA_B[0], W_VGA_B[1], 2'b0};
601 mc_sound_a MC_SOUND_A(
603 .I_CLK_12M(W_CLK_12M),
605 .I_H_CNT1(W_H_CNT[1]),
618 mc_sound_b MC_SOUND_B(
622 .I_RSTn(rst_count[3]),
623 .I_SW({&on_game[1:0],W_HIT,W_FIRE}),
639 assign O_SOUND_OUT_L = W_DAC_A;
640 assign O_SOUND_OUT_R = W_DAC_B;