git.zerfleddert.de Git - fpga-games/blob - galaxian/src/mc_hv_count.v

   1 //---------------------------------------------------------------------
   2 // FPGA MOONCRESTA   H & V COUNTER
   3 //
   4 // Version : 2.00
   5 //
   6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
   7 //
   8 // Important !
   9 //
  10 // This program is freeware for non-commercial use.
  11 // An author does no guarantee about this program.
  12 // You can use this under your own risk.
  13 //
  14 // 2004- 9-22
  15 //---------------------------------------------------------------------
  16 //  MoonCrest hv_count
  17 //  H_CNT   0 - 255 , 384 - 511  Total 384 count
  18 //  V_CNT   0 - 255 , 504 - 511  Total 264 count
  19 //-----------------------------------------------------------------------------------------
  20 // H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8],
  21 //    1 H     2 H      4H       8H       16 H     32H      64 H     128 H   256 H
  22 //-----------------------------------------------------------------------------------------
  23 // V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]
  24 //    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V
  25 //-----------------------------------------------------------------------------------------
  26
  27 module mc_hv_count(
  28
  29 I_CLK,     //  6MHz
  30 I_RSTn,
  31
  32 O_H_CNT,
  33 O_H_SYNC,
  34 O_H_BL,
  35 O_V_CNT,
  36 O_V_SYNC,
  37 O_V_BLn,
  38 O_V_BL2n,
  39 O_C_BLn
  40
  41 );
  42
  43 input  I_CLK,I_RSTn;
  44 output [8:0]O_H_CNT;
  45 output O_H_SYNC;
  46 output O_H_BL;
  47 output O_V_BL2n;
  48 output [7:0]O_V_CNT;
  49 output O_V_SYNC;
  50 output O_V_BLn;
  51
  52 output O_C_BLn;
  53
  54 //-------   H_COUNT   ----------------------------------------
  55 reg    [8:0]H_CNT;
  56 always@(posedge I_CLK)
  57 begin
  58    H_CNT <= H_CNT==255 ? 384 : H_CNT +1 ;
  59 end
  60 assign O_H_CNT  = H_CNT[8:0];
  61
  62 //-------   H_SYNC     ----------------------------------------
  63
  64 reg     H_SYNC;
  65 always@(posedge H_CNT[4] or negedge H_CNT[8])
  66 begin
  67    if(H_CNT[8]==1'b0) H_SYNC <= 1'b0;
  68    else   H_SYNC <= (~H_CNT[6]& H_CNT[5]);
  69 end
  70
  71 assign O_H_SYNC = H_SYNC;
  72 //-------   H_BL     ------------------------------------------
  73
  74 reg    H_BL;
  75
  76 always@(posedge I_CLK)
  77 begin
  78    case(H_CNT[8:0])
  79       387:H_BL<=1'b1;
  80       503:H_BL<=1'b0;
  81     default:;
  82    endcase
  83 end
  84
  85 assign O_H_BL = H_BL;
  86 //-------   V_COUNT   ----------------------------------------
  87 reg    [8:0]V_CNT;
  88 always@(posedge H_SYNC or negedge I_RSTn)
  89 begin
  90    if(I_RSTn==1'b0)
  91       V_CNT <= 0;
  92    else
  93       V_CNT <= V_CNT==255 ? 504 : V_CNT +1 ;
  94 end
  95 assign O_V_CNT  = V_CNT[7:0];
  96 assign O_V_SYNC = V_CNT[8];
  97
  98 //-------   V_BLn    ------------------------------------------
  99
 100 reg    V_BLn;
 101 always@(posedge H_SYNC)
 102 begin
 103    case(V_CNT[7:0])
 104     239: V_BLn <= 0;
 105      15: V_BLn <= 1;
 106     default:;
 107    endcase
 108 end
 109
 110 reg    V_BL2n;
 111 always@(posedge H_SYNC)
 112 begin
 113    case(V_CNT[7:0])
 114     239: V_BL2n <= 0;
 115      16: V_BL2n <= 1;
 116     default:;
 117    endcase
 118 end
 119
 120 assign O_V_BLn  = V_BLn;
 121 assign O_V_BL2n = V_BL2n;
 122 //-------   C_BLn     ------------------------------------------
 123
 124 assign O_C_BLn = ~(~V_BLn | H_CNT[8]);
 125
 126 endmodule