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   1 //===============================================================================
   2 // FPGA MOONCRESTA STARS
   3 //
   4 // Version : 2.00
   5 //
   6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
   7 //
   8 // Important !
   9 //
  10 // This program is freeware for non-commercial use.
  11 // An author does no guarantee about this program.
  12 // You can use this under your own risk.
  13 //
  14 // 2004- 9-22
  15 //================================================================================
  16
  17
  18 module mc_stars(
  19
  20 I_CLK_18M,
  21 I_CLK_6M,
  22 I_H_FLIP,
  23 I_V_SYNC,
  24 I_8HF,
  25 I_256HnX,
  26 I_1VF,
  27 I_2V,
  28 I_STARS_ON,
  29 I_STARS_OFFn,
  30
  31 O_R,
  32 O_G,
  33 O_B,
  34 O_NOISE
  35
  36 );
  37
  38 input  I_CLK_18M;
  39 input  I_CLK_6M;
  40 input  I_H_FLIP;
  41 input  I_V_SYNC;
  42 input  I_8HF;
  43 input  I_256HnX;
  44 input  I_1VF;
  45 input  I_2V;
  46 input  I_STARS_ON;
  47 input  I_STARS_OFFn;
  48
  49 output [2:0]O_R;
  50 output [2:0]O_G;
  51 output [1:0]O_B;
  52 output O_NOISE;
  53
  54 wire    W_V_SYNCn = ~I_V_SYNC;
  55
  56 wire    CLK_1C = ~(I_CLK_18M & I_CLK_6M & W_V_SYNCn & I_256HnX);
  57
  58 reg     W_1C_Q1,W_1C_Q2;
  59 always@(posedge CLK_1C or negedge W_V_SYNCn)
  60 begin
  61    if(W_V_SYNCn==1'b0)begin
  62       W_1C_Q1 <= 1'b0;
  63       W_1C_Q2 <= 1'b0;
  64    end
  65    else begin
  66       W_1C_Q1 <= 1'b1;
  67       W_1C_Q2 <= W_1C_Q1;
  68    end
  69 end
  70
  71 wire    CLK_1AB = ~(CLK_1C |(~(I_H_FLIP|W_1C_Q2))) ;
  72
  73 reg     [15:0]W_1AB_Q;
  74 reg     W_2D_Qn;
  75 wire    W_3B = W_2D_Qn^W_1AB_Q[4];
  76
  77 always@(posedge CLK_1AB or negedge I_STARS_ON)
  78 begin
  79    if(I_STARS_ON==1'b0)begin
  80       W_1AB_Q <= 0;
  81       W_2D_Qn <= 1'b1;
  82    end
  83    else begin
  84       W_1AB_Q <= {W_1AB_Q[14:0],W_3B};
  85       W_2D_Qn <= ~W_1AB_Q[15];
  86    end
  87 end
  88
  89 wire    W_2A = ~(& W_1AB_Q[7:0]);
  90 wire    W_4P = ~(( I_8HF ^ I_1VF ) & W_2D_Qn & I_STARS_OFFn);
  91
  92 assign  O_R[2] = 1'b0 ;
  93 assign  O_R[1] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[8] ;
  94 assign  O_R[0] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[9] ;
  95
  96 assign  O_G[2] = 1'b0 ;
  97 assign  O_G[1] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[10] ;
  98 assign  O_G[0] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[11] ;
  99
 100 assign  O_B[1] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[12] ;
 101 assign  O_B[0] = (W_2A|W_4P) ? 1'b0 : W_1AB_Q[13] ;
 102
 103 reg     noise;
 104 always@(posedge I_2V) noise <= W_2D_Qn ;
 105 assign  O_NOISE = noise ;
 106
 107
 108 endmodule