// // Daniel Wallner's T80 header file for verilog // // Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved // // Important ! // // This program is freeware for non-commercial use. // An author does no guarantee about this program. // You can use this under your own risk. // // module T80as( RESET_n,CLK_n,WAIT_n,INT_n,NMI_n,BUSRQ_n, M1_n,MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,HALT_n,BUSAK_n, A,DI,DO,DOE); input RESET_n,CLK_n,WAIT_n,INT_n,NMI_n,BUSRQ_n; output M1_n,MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,HALT_n,BUSAK_n; output [15:0] A; input [7:0] DI; output [7:0] DO; output DOE; endmodule