### UCF file for FPGA-MOONCRST on XC2S200E # #---------- MasterClock 18.432MHz ---------- NET "I_CLK_125M" LOC = "F13" | IOSTANDARD = LVCMOS33; #------------------------------------------- #---------- SW I/F ------------------------- NET "I_PSW<0>" LOC = "K19" | IOSTANDARD = LVTTL | PULLUP; NET "I_PSW<1>" LOC = "F22" | IOSTANDARD = LVTTL | PULLUP; NET "I_PSW<2>" LOC = "G22" | IOSTANDARD = LVTTL | PULLUP; NET "I_PSW<3>" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP; NET "I_PSW<4>" LOC = "F23" | IOSTANDARD = LVTTL | PULLUP; #------------------------------------------- #--------- EEPROM I/F ---------------------- #NET "I_ROM_DB<0>" LOC = "P70"; #NET "I_ROM_DB<1>" LOC = "P68"; #NET "I_ROM_DB<2>" LOC = "P63"; #NET "I_ROM_DB<3>" LOC = "P58"; #NET "I_ROM_DB<4>" LOC = "P60"; #NET "I_ROM_DB<5>" LOC = "P62"; #NET "I_ROM_DB<6>" LOC = "P57"; #NET "I_ROM_DB<7>" LOC = "P59"; #NET "O_ROM_AB<0>" LOC = "P71"; #NET "O_ROM_AB<1>" LOC = "P74"; #NET "O_ROM_AB<2>" LOC = "P73"; #NET "O_ROM_AB<3>" LOC = "P75"; #NET "O_ROM_AB<4>" LOC = "P81"; #NET "O_ROM_AB<5>" LOC = "P82"; #NET "O_ROM_AB<6>" LOC = "P84"; #NET "O_ROM_AB<7>" LOC = "P86"; #NET "O_ROM_AB<8>" LOC = "P89"; #NET "O_ROM_AB<9>" LOC = "P87"; #NET "O_ROM_AB<10>" LOC = "P64"; #NET "O_ROM_AB<11>" LOC = "P83"; #NET "O_ROM_AB<12>" LOC = "P88"; #NET "O_ROM_AB<13>" LOC = "P95"; #NET "O_ROM_AB<14>" LOC = "P97"; #NET "O_ROM_AB<15>" LOC = "P93"; #NET "O_ROM_AB<16>" LOC = "P96"; #NET "O_ROM_AB<17>" LOC = "P98"; #NET "O_ROM_AB<18>" LOC = "P94"; #NET "O_ROM_CSn" LOC = "P61"; #NET "O_ROM_OEn" LOC = "P69"; #NET "O_ROM_WEn" LOC = "P100"; #------------------------------------------- #--------- SOUND I/F ----------------------- NET "O_SOUND_OUT_L" LOC = "AA22" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; NET "O_SOUND_OUT_R" LOC = "V19" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; #------------------------------------------- #--------- VIDEO I/F ----------------------- NET "O_VGA_R<4>" LOC = "V18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_R<3>" LOC = "F24" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_R<2>" LOC = "F25" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_R<1>" LOC = "K20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_R<0>" LOC = "L20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_G<4>" LOC = "T17" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_G<3>" LOC = "J22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_G<2>" LOC = "J23" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_G<1>" LOC = "M18" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_G<0>" LOC = "M19" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_B<4>" LOC = "Y25" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_B<3>" LOC = "G24" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_B<2>" LOC = "G23" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_B<1>" LOC = "K21" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_B<0>" LOC = "L22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_H_SYNCn" LOC = "K26" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "O_VGA_V_SYNCn" LOC = "K25" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; #------------------------------------------- # #---------- Build-in ROM ------------------------------------------------------------------------------- #INST "col_rom00" INIT_00 = c6077600f007f6000700000007a0c00007c4c0003f07d8003fc01600f6000000;