// megafunction wizard: %RAM: 1-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: alt_ram_256_5.v // Megafunction Name(s): // altsyncram // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // ************************************************************ //Copyright (C) 1991-2003 Altera Corporation //Any megafunction design, and related netlist (encrypted or decrypted), //support information, device programming or simulation file, and any other //associated documentation or information provided by Altera or a partner //under Altera's Megafunction Partnership Program may be used only //to program PLD devices (but not masked PLD devices) from Altera. Any //other use of such megafunction design, netlist, support information, //device programming or simulation file, or any other related documentation //or information is prohibited for any other purpose, including, but not //limited to modification, reverse engineering, de-compiling, or use with //any other silicon devices, unless such use is explicitly licensed under //a separate agreement with Altera or a megafunction partner. Title to the //intellectual property, including patents, copyrights, trademarks, trade //secrets, or maskworks, embodied in any such megafunction design, netlist, //support information, device programming or simulation file, or any other //related documentation or information provided by Altera or a megafunction //partner, remains with Altera, the megafunction partner, or their respective //licensors. No other licenses, including any licenses needed under any third //party's intellectual property, are provided herein. module alt_ram_256_5 ( address, inclock, outclock, data, wren, q); input [7:0] address; input inclock; input outclock; input [4:0] data; input wren; output [4:0] q; wire [4:0] sub_wire0; wire [4:0] q = sub_wire0[4:0]; altsyncram altsyncram_component ( .wren_a (wren), .clock0 (inclock), .clock1 (outclock), .address_a (address), .data_a (data), .q_a (sub_wire0)); defparam altsyncram_component.intended_device_family = "Cyclone", altsyncram_component.width_a = 5, altsyncram_component.widthad_a = 8, altsyncram_component.numwords_a = 256, altsyncram_component.operation_mode = "SINGLE_PORT", altsyncram_component.outdata_reg_a = "CLOCK1", altsyncram_component.indata_aclr_a = "NONE", altsyncram_component.wrcontrol_aclr_a = "NONE", altsyncram_component.address_aclr_a = "NONE", altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.width_byteena_a = 1, altsyncram_component.ram_block_type = "AUTO", altsyncram_component.use_eab = "ON", altsyncram_component.lpm_type = "altsyncram"; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: WidthData NUMERIC "5" // Retrieval info: PRIVATE: WidthAddr NUMERIC "8" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: PRIVATE: SingleClock NUMERIC "0" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" // Retrieval info: PRIVATE: RegData NUMERIC "1" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "1" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: AclrByte NUMERIC "0" // Retrieval info: PRIVATE: AclrData NUMERIC "0" // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" // Retrieval info: PRIVATE: MIFfilename STRING "" // Retrieval info: PRIVATE: UseLCs NUMERIC "0" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "5" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK1" // Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO" // Retrieval info: CONSTANT: USE_EAB STRING "ON" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0] // Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0] // Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock // Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL outclock // Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0] // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren // Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 // Retrieval info: CONNECT: q 0 0 5 0 @q_a 0 0 5 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0 // Retrieval info: CONNECT: @clock1 0 0 0 0 outclock 0 0 0 0 // Retrieval info: CONNECT: @data_a 0 0 5 0 data 0 0 5 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all