fix clock for LRAM

[fpga-games] / galaxian / src / mc_clock.v

diff --git a/galaxian/src/mc_clock.v b/galaxian/src/mc_clock.v
index 5ccfbd606fe31e7d7637cb7141e420caf9bc3b7e..36925f3f3bee4be56cd942b2ad9688b126676fbe 100644 (file)
--- a/galaxian/src/mc_clock.v
+++ b/galaxian/src/mc_clock.v
@@ -20,7 +20,8 @@ module mc_clock(
 I_CLK_36M,\r
 O_CLK_18M,\r
 O_CLK_12M,\r
 I_CLK_36M,\r
 O_CLK_18M,\r
 O_CLK_12M,\r

-O_CLK_06M\r
+O_CLK_06M,\r
+O_CLK_06Mn\r

 \r
 );\r
 \r
 \r
 );\r
 \r


@@ -28,6 +29,7 @@ input I_CLK_36M;
 output O_CLK_18M;\r
 output O_CLK_12M;\r
 output O_CLK_06M;\r
 output O_CLK_18M;\r
 output O_CLK_12M;\r
 output O_CLK_06M;\r

+output O_CLK_06Mn;\r

 \r
 // 2/3 clock divider(duty 33%)\r
 //I_CLK   1010101010101010101\r
 \r
 // 2/3 clock divider(duty 33%)\r
 //I_CLK   1010101010101010101\r


@@ -68,10 +70,15 @@ assign O_CLK_18M = CLK_18M;
 \r
 // 1/3 clock divider (duty 50%)\r
 reg CLK_6M;\r
 \r
 // 1/3 clock divider (duty 50%)\r
 reg CLK_6M;\r

+reg CLK_6Mn;\r
+\r

 always @(posedge O_CLK_12M)\r
 begin\r
    CLK_6M  <= ~CLK_6M;\r
 always @(posedge O_CLK_12M)\r
 begin\r
    CLK_6M  <= ~CLK_6M;\r

+   CLK_6Mn <= CLK_6M;\r

 end\r
 end\r

+\r

 assign O_CLK_06M = CLK_6M;\r
 assign O_CLK_06M = CLK_6M;\r

+assign O_CLK_06Mn = CLK_6Mn;\r

 \r
 endmodule\r
 \r
 endmodule\r