fix clock for LRAM

[fpga-games] / galaxian / src / mc_top.v

diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v
index 99a4a6aa911479a125de90de30e64aa00dccc672..99206f367ab52db4aab5ed63f99d91ed33da776e 100644 (file)
--- a/galaxian/src/mc_top.v
+++ b/galaxian/src/mc_top.v
@@ -89,15 +89,17 @@ output O_VGA_V_SYNCn;
 \r
 wire   W_RESETn = |(~I_PSW[8:5]);\r
 //------ CLOCK GEN ---------------------------\r
 \r
 wire   W_RESETn = |(~I_PSW[8:5]);\r
 //------ CLOCK GEN ---------------------------\r

-wire   I_CLK_18432M;\r
+wire   W_CLK_18M;\r
+wire   W_CLK_36M;\r

 wire   W_CLK_12M,WB_CLK_12M;\r
 wire   W_CLK_6M,WB_CLK_6M;\r
 wire   W_CLK_12M,WB_CLK_12M;\r
 wire   W_CLK_6M,WB_CLK_6M;\r

+wire   W_CLK_6Mn;\r

 wire   W_STARS_CLK;\r
 \r
 mc_dcm clockgen(\r
 .CLKIN_IN(I_CLK_125M),\r
 .RST_IN(! W_RESETn),\r
 wire   W_STARS_CLK;\r
 \r
 mc_dcm clockgen(\r
 .CLKIN_IN(I_CLK_125M),\r
 .RST_IN(! W_RESETn),\r

-.CLKFX_OUT(I_CLK_18432M)\r
+.CLKFX_OUT(W_CLK_36M)\r

 );\r
 \r
 //------ H&V COUNTER -------------------------\r
 );\r
 \r
 //------ H&V COUNTER -------------------------\r


@@ -144,20 +146,16 @@ wire   [7:0]W_VID_DO;
 \r
 mc_clock MC_CLK(\r
 \r
 \r
 mc_clock MC_CLK(\r
 \r

-.I_CLK_18M(I_CLK_18432M),\r
+.I_CLK_36M(W_CLK_36M),\r
+.O_CLK_18M(W_CLK_18M),\r

 .O_CLK_12M(WB_CLK_12M),\r
 .O_CLK_12M(WB_CLK_12M),\r

-.O_CLK_06M(WB_CLK_6M)\r
+.O_CLK_06M(WB_CLK_6M),\r
+.O_CLK_06Mn(W_CLK_6Mn)\r

 \r
 );\r
 \r
 \r
 );\r
 \r

-`ifdef DEVICE_CYCLONE\r

 assign W_CLK_12M = WB_CLK_12M;\r
 assign W_CLK_6M  = WB_CLK_6M;\r
 assign W_CLK_12M = WB_CLK_12M;\r
 assign W_CLK_6M  = WB_CLK_6M;\r

-`endif\r
-`ifdef DEVICE_SPARTAN2E\r
-BUFG   BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) );\r
-BUFG   BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) );\r
-`endif\r

 //---  DATA I/F -------------------------------------\r
 reg    [7:0]W_CPU_ROM_DO;\r
 wire   [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;\r
 //---  DATA I/F -------------------------------------\r
 reg    [7:0]W_CPU_ROM_DO;\r
 wire   [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;\r


@@ -329,7 +327,7 @@ wire        VIB_SW = died & (&on_game[1:0]);
 \r
 fpga_arcade_if pspad(\r
 \r
 \r
 fpga_arcade_if pspad(\r
 \r

-.CLK_18M432(I_CLK_18432M),\r
+.CLK_18M432(W_CLK_18M),\r

 .I_RSTn(W_RESETn),\r
 .psCLK(psCLK),\r
 .psSEL(psSEL),\r
 .I_RSTn(W_RESETn),\r
 .psCLK(psCLK),\r
 .psSEL(psSEL),\r


@@ -444,9 +442,10 @@ wire   [1:0]W_VID;
 wire   [2:0]W_COL;\r
 \r
 mc_video MC_VID(\r
 wire   [2:0]W_COL;\r
 \r
 mc_video MC_VID(\r

-.I_CLK_18M(I_CLK_18432M),\r
+.I_CLK_18M(W_CLK_18M),\r

 .I_CLK_12M(W_CLK_12M),\r
 .I_CLK_6M(W_CLK_6M),\r
 .I_CLK_12M(W_CLK_12M),\r
 .I_CLK_6M(W_CLK_6M),\r

+.I_CLK_6Mn(W_CLK_6Mn),\r

 .I_H_CNT(W_H_CNT),\r
 .I_V_CNT(W_V_CNT),\r
 .I_H_FLIP(W_H_FLIP),\r
 .I_H_CNT(W_H_CNT),\r
 .I_V_CNT(W_V_CNT),\r
 .I_H_FLIP(W_H_FLIP),\r


@@ -503,7 +502,7 @@ wire   [1:0]W_STARS_B;
 \r
 mc_stars MC_STARS( \r
 \r
 \r
 mc_stars MC_STARS( \r
 \r

-.I_CLK_18M(I_CLK_18432M),\r
+.I_CLK_18M(W_CLK_18M),\r

 `ifdef DEVICE_CYCLONE\r
 .I_CLK_6M(~WB_CLK_6M),\r
 `endif\r
 `ifdef DEVICE_CYCLONE\r
 .I_CLK_6M(~WB_CLK_6M),\r
 `endif\r


@@ -615,7 +614,7 @@ wire   [7:0]W_SDAT_B;
 \r
 mc_sound_b MC_SOUND_B(\r
 \r
 \r
 mc_sound_b MC_SOUND_B(\r
 \r

-.I_CLK1(I_CLK_18432M),\r
+.I_CLK1(W_CLK_18M),\r

 .I_CLK2(W_CLK_6M),\r
 .I_RSTn(rst_count[3]),\r
 .I_SW({&on_game[1:0],W_HIT,W_FIRE}),\r
 .I_CLK2(W_CLK_6M),\r
 .I_RSTn(rst_count[3]),\r
 .I_SW({&on_game[1:0],W_HIT,W_FIRE}),\r


@@ -639,7 +638,7 @@ assign  O_SOUND_OUT_R = W_DAC_B;
 \r
 dac wav_dac_a(\r
 \r
 \r
 dac wav_dac_a(\r
 \r

-.Clk(I_CLK_18432M), \r
+.Clk(W_CLK_18M), \r

 .Reset(~W_RESETn),\r
 .DACin(W_SDAT_A),\r
 .DACout(W_DAC_A)\r
 .Reset(~W_RESETn),\r
 .DACin(W_SDAT_A),\r
 .DACout(W_DAC_A)\r


@@ -648,7 +647,7 @@ dac wav_dac_a(
 \r
 dac wav_dac_b(\r
 \r
 \r
 dac wav_dac_b(\r
 \r

-.Clk(I_CLK_18432M), \r
+.Clk(W_CLK_18M), \r

 .Reset(~W_RESETn),\r
 .DACin(W_SDAT_B),\r
 .DACout(W_DAC_B)\r
 .Reset(~W_RESETn),\r
 .DACin(W_SDAT_B),\r
 .DACout(W_DAC_B)\r