fix clock for LRAM

[fpga-games] / galaxian / src / mc_video.v

diff --git a/galaxian/src/mc_video.v b/galaxian/src/mc_video.v
index c184923475107e739e9da4a4ad66d58fcc862f0a..84f23976161634881be90447402da1a573820001 100644 (file)
--- a/galaxian/src/mc_video.v
+++ b/galaxian/src/mc_video.v
@@ -29,6 +29,7 @@ module mc_video(
 I_CLK_18M,\r
 I_CLK_12M,\r
 I_CLK_6M,\r
 I_CLK_18M,\r
 I_CLK_12M,\r
 I_CLK_6M,\r

+I_CLK_6Mn,\r

 I_H_CNT,\r
 I_V_CNT,\r
 I_H_FLIP,\r
 I_H_CNT,\r
 I_V_CNT,\r
 I_H_FLIP,\r


@@ -60,6 +61,7 @@ O_COL
 input  I_CLK_18M;\r
 input  I_CLK_12M;\r
 input  I_CLK_6M;\r
 input  I_CLK_18M;\r
 input  I_CLK_12M;\r
 input  I_CLK_6M;\r

+input  I_CLK_6Mn;\r

 input  [8:0]I_H_CNT;\r
 input  [7:0]I_V_CNT;\r
 input  I_H_FLIP;\r
 input  [8:0]I_H_CNT;\r
 input  [7:0]I_V_CNT;\r
 input  I_H_FLIP;\r


@@ -119,7 +121,7 @@ end
 \r
 mc_ld_pls LD_PLS(\r
 \r
 \r
 mc_ld_pls LD_PLS(\r
 \r

-.I_CLK_6M(~I_CLK_6M),\r
+.I_CLK_6M(I_CLK_6M),\r

 .I_H_CNT(I_H_CNT),\r
 .I_3D_DI(W_3D),\r
 \r
 .I_H_CNT(I_H_CNT),\r
 .I_3D_DI(W_3D),\r
 \r


@@ -339,16 +341,14 @@ begin
 end\r
 \r
 wire   [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};\r
 end\r
 \r
 wire   [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};\r

-wire   W_LRAM_WE = ~I_CLK_6M;\r

 \r
 wire   [4:0]W_LRAM_DI;\r
 wire   [4:0]W_LRAM_DO;\r
 \r
 reg    [1:0]W_RV;\r
 reg    [2:0]W_RC;\r
 \r
 wire   [4:0]W_LRAM_DI;\r
 wire   [4:0]W_LRAM_DO;\r
 \r
 reg    [1:0]W_RV;\r
 reg    [2:0]W_RC;\r

-wire   W_1U_CLK = ~I_CLK_6M;\r

 \r
 \r

-always@(posedge W_1U_CLK)\r
+always@(negedge I_CLK_6M)\r

 begin\r
       W_RV <= W_LRAM_DO[1:0];    \r
       W_RC <= W_LRAM_DO[4:2];\r
 begin\r
       W_RV <= W_LRAM_DO[1:0];    \r
       W_RC <= W_LRAM_DO[4:2];\r


@@ -379,7 +379,7 @@ mc_lram LRAM(
 \r
 .I_CLK(I_CLK_18M),\r
 .I_ADDR(W_LRAM_A),\r
 \r
 .I_CLK(I_CLK_18M),\r
 .I_ADDR(W_LRAM_A),\r

-.I_WE(W_LRAM_WE),\r
+.I_WE(I_CLK_6Mn),\r

 .I_D(W_LRAM_DI),\r
 .O_Dn(W_LRAM_DO)\r
 \r
 .I_D(W_LRAM_DI),\r
 .O_Dn(W_LRAM_DO)\r
 \r