fix clock for LRAM

[fpga-games] / galaxian / src / mc_top.v

diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v
index 5f123fda4d1f0a97d212e1f26ce1e2b74e11f5e5..99206f367ab52db4aab5ed63f99d91ed33da776e 100644 (file)
--- a/galaxian/src/mc_top.v
+++ b/galaxian/src/mc_top.v
@@ -33,13 +33,6 @@ psTXD,
 psRXD,\r
 `endif\r
 \r
-//    ROM IF\r
-//O_ROM_AB,\r
-//I_ROM_DB,\r
-//O_ROM_OEn,\r
-//O_ROM_CSn,\r
-//O_ROM_WEn,\r
-\r
 //    INPORT SW IF\r
 I_PSW,\r
 \r
@@ -80,13 +73,6 @@ input        psRXD;
 output psTXD,psCLK,psSEL;\r
 `endif\r
 \r
-//    ROM IF\r
-//output [18:0]O_ROM_AB;\r
-//input  [7:0]I_ROM_DB;\r
-//output O_ROM_OEn;\r
-//output O_ROM_CSn;\r
-//output O_ROM_WEn;\r
-\r
 //    INPORT SW IF\r
 input  [8:0]I_PSW;\r
 \r
@@ -95,23 +81,25 @@ output  O_SOUND_OUT_L;
 output  O_SOUND_OUT_R;\r
 \r
 //    VGA (VIDEO) IF\r
-output [2:0]O_VGA_R;\r
-output [2:0]O_VGA_G;\r
-output [1:0]O_VGA_B;\r
+output [3:0]O_VGA_R;\r
+output [3:0]O_VGA_G;\r
+output [3:0]O_VGA_B;\r
 output O_VGA_H_SYNCn;\r
 output O_VGA_V_SYNCn;\r
 \r
 wire   W_RESETn = |(~I_PSW[8:5]);\r
 //------ CLOCK GEN ---------------------------\r
-wire   I_CLK_18432M;\r
+wire   W_CLK_18M;\r
+wire   W_CLK_36M;\r
 wire   W_CLK_12M,WB_CLK_12M;\r
 wire   W_CLK_6M,WB_CLK_6M;\r
+wire   W_CLK_6Mn;\r
 wire   W_STARS_CLK;\r
 \r
 mc_dcm clockgen(\r
 .CLKIN_IN(I_CLK_125M),\r
 .RST_IN(! W_RESETn),\r
-.CLKFX_OUT(I_CLK_18432M)\r
+.CLKFX_OUT(W_CLK_36M)\r
 );\r
 \r
 //------ H&V COUNTER -------------------------\r
@@ -158,20 +146,16 @@ wire   [7:0]W_VID_DO;
 \r
 mc_clock MC_CLK(\r
 \r
-.I_CLK_18M(I_CLK_18432M),\r
+.I_CLK_36M(W_CLK_36M),\r
+.O_CLK_18M(W_CLK_18M),\r
 .O_CLK_12M(WB_CLK_12M),\r
-.O_CLK_06M(WB_CLK_6M)\r
+.O_CLK_06M(WB_CLK_6M),\r
+.O_CLK_06Mn(W_CLK_6Mn)\r
 \r
 );\r
 \r
-`ifdef DEVICE_CYCLONE\r
 assign W_CLK_12M = WB_CLK_12M;\r
 assign W_CLK_6M  = WB_CLK_6M;\r
-`endif\r
-`ifdef DEVICE_SPARTAN2E\r
-BUFG   BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) );\r
-BUFG   BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) );\r
-`endif\r
 //---  DATA I/F -------------------------------------\r
 reg    [7:0]W_CPU_ROM_DO;\r
 wire   [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;\r
@@ -343,7 +327,7 @@ wire        VIB_SW = died & (&on_game[1:0]);
 \r
 fpga_arcade_if pspad(\r
 \r
-.CLK_18M432(I_CLK_18432M),\r
+.CLK_18M432(W_CLK_18M),\r
 .I_RSTn(W_RESETn),\r
 .psCLK(psCLK),\r
 .psSEL(psSEL),\r
@@ -410,76 +394,23 @@ mc_inport MC_INPORT(
 //-----------------------------------------------------------------------------\r
 //------- ROM           -------------------------------------------------------\r
 reg    [18:0]ROM_A;\r
-wire   [10:0]W_OBJ_ROM_A;\r
-reg    [7:0]W_OBJ_ROM_A_D;\r
-reg    [7:0]W_OBJ_ROM_B_D;\r
 \r
 wire   [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2;\r
 reg    [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2;\r
 \r
-wire   [7:0]ROM_D; // = I_ROM_DB;\r
-//assign O_ROM_AB  = ROM_A;\r
-\r
-//assign O_ROM_OEn = 1'b0;\r
-//assign O_ROM_CSn = 1'b0;\r
-//assign O_ROM_WEn = 1'b1;\r
+wire   [7:0]ROM_D;\r
 \r
 galaxian_roms ROMS(\r
-.I_CLK_18432M(I_CLK_18432M),\r
-.I_CLK_12M(WB_CLK_12M),\r
-.I_ADDR(ROM_A),\r
+.I_ROM_CLK(W_CLK_12M),\r
+.I_ADDR({3'h0,W_A[15:0]}),\r
 .O_DATA(ROM_D)\r
 );\r
 \r
-\r
-reg    [1:0]clk_d;\r
-reg    [4:0]seq;\r
-always @(posedge I_CLK_18432M)\r
+always@(posedge W_CLK_12M)\r
 begin\r
-  // 24 phase generator\r
-   clk_d[0] <= W_H_CNT[0] & W_H_CNT[1] & W_H_CNT[2];\r
-   clk_d[1] <= clk_d[0];\r
-   seq <= (~clk_d[1] & clk_d[0]) ? 0 : seq+1;\r
-   case(seq)\r
-      0:begin\r
-        //sound\r
-        ROM_A <= W_WAV_A0;\r
-        W_CPU_ROM_DO <= ROM_D;\r
-        end\r
-      2:begin\r
-        //sound\r
-        ROM_A <= W_WAV_A1;\r
-        W_WAV_D0 <= ROM_D;\r
-        end\r
-      4:begin\r
-        //sound\r
-        ROM_A <= {3'h0,W_A[15:0]};\r
-        W_WAV_D1 <= ROM_D;\r
-        end\r
-      6:begin\r
-        //sound\r
-        ROM_A <= W_WAV_A2;\r
-        W_CPU_ROM_DO <= ROM_D;\r
-        end\r
-      8:W_WAV_D2 <= ROM_D; //sound\r
-     10:ROM_A <= {3'h0,W_A[15:0]};\r
-     12:W_CPU_ROM_DO <= ROM_D;\r
-     16:ROM_A <= {3'h0,W_A[15:0]};\r
-     18:begin\r
-        ROM_A <= {3'h0,4'h4,1'b0,W_OBJ_ROM_A};\r
-        W_CPU_ROM_DO <= ROM_D;\r
-        end\r
-     20:begin\r
-        ROM_A <= {3'h0,4'h5,1'b0,W_OBJ_ROM_A};\r
-        W_OBJ_ROM_A_D <= ROM_D;\r
-        end\r
-     22:begin\r
-        ROM_A <= {3'h0,W_A[15:0]};\r
-        W_OBJ_ROM_B_D <= ROM_D;\r
-        end\r
-     default:;\r
-   endcase\r
+       W_CPU_ROM_DO <= ROM_D;\r
 end\r
+\r
 //-----------------------------------------------------------------------------\r
 \r
 wire   W_V_BL2n;\r
@@ -511,9 +442,10 @@ wire   [1:0]W_VID;
 wire   [2:0]W_COL;\r
 \r
 mc_video MC_VID(\r
-.I_CLK_18M(I_CLK_18432M),\r
+.I_CLK_18M(W_CLK_18M),\r
 .I_CLK_12M(W_CLK_12M),\r
 .I_CLK_6M(W_CLK_6M),\r
+.I_CLK_6Mn(W_CLK_6Mn),\r
 .I_H_CNT(W_H_CNT),\r
 .I_V_CNT(W_V_CNT),\r
 .I_H_FLIP(W_H_FLIP),\r
@@ -530,10 +462,6 @@ mc_video MC_VID(
 .I_VID_RAM_RDn(W_VID_RAM_RDn),\r
 .I_VID_RAM_WRn(W_VID_RAM_WRn),\r
 \r
-.O_OBJ_ROM_A(W_OBJ_ROM_A),\r
-.I_OBJ_ROM_A_D(W_OBJ_ROM_A_D),\r
-.I_OBJ_ROM_B_D(W_OBJ_ROM_B_D),\r
-\r
 .O_C_BLnX(W_C_BLnX),\r
 .O_8HF(W_8HF),\r
 .O_256HnX(W_256HnX),\r
@@ -574,7 +502,7 @@ wire   [1:0]W_STARS_B;
 \r
 mc_stars MC_STARS( \r
 \r
-.I_CLK_18M(I_CLK_18432M),\r
+.I_CLK_18M(W_CLK_18M),\r
 `ifdef DEVICE_CYCLONE\r
 .I_CLK_6M(~WB_CLK_6M),\r
 `endif\r
@@ -621,6 +549,10 @@ mc_vedio_mix MIX(
 \r
 );\r
 \r
+wire [2:0]W_VGA_R;\r
+wire [2:0]W_VGA_G;\r
+wire [1:0]W_VGA_B;\r
+\r
 `ifdef VGA_USE\r
 mc_vga_if  VGA(\r
 \r
@@ -633,9 +565,9 @@ mc_vga_if  VGA(
 .I_H_SYNC(W_H_SYNC),\r
 .I_V_SYNC(W_V_SYNC),\r
 // output\r
-.O_R(O_VGA_R),\r
-.O_G(O_VGA_G),\r
-.O_B(O_VGA_B),\r
+.O_R(W_VGA_R),\r
+.O_G(W_VGA_G),\r
+.O_B(W_VGA_B),\r
 .O_H_SYNCn(O_VGA_H_SYNCn),\r
 .O_V_SYNCn(O_VGA_V_SYNCn)\r
 \r
@@ -643,11 +575,11 @@ mc_vga_if  VGA(
 \r
 `else\r
 \r
-assign O_VGA_R[2:0] = W_R;\r
+assign W_VGA_R[2:0] = W_R;\r
 \r
-assign O_VGA_G[2:0] = W_G;\r
+assign W_VGA_G[2:0] = W_G;\r
 \r
-assign O_VGA_B[1:0] = W_B;\r
+assign W_VGA_B[1:0] = W_B;\r
 \r
 //assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ;  //  AKIDUKI LCD USED\r
 assign O_VGA_H_SYNCn = ~W_H_SYNC ;\r
@@ -655,6 +587,12 @@ assign O_VGA_V_SYNCn = ~W_V_SYNC ;
 \r
 `endif\r
 \r
+assign O_VGA_R[3:0] = {W_VGA_R[0], W_VGA_R[1], W_VGA_R[2], 1'b0};\r
+\r
+assign O_VGA_G[3:0] = {W_VGA_G[0], W_VGA_G[1], W_VGA_G[2], 1'b0};\r
+\r
+assign O_VGA_B[3:0] = {W_VGA_B[0], W_VGA_B[1], 2'b0};\r
+\r
 wire   [7:0]W_SDAT_A;\r
 \r
 mc_sound_a MC_SOUND_A(\r
@@ -676,7 +614,7 @@ wire   [7:0]W_SDAT_B;
 \r
 mc_sound_b MC_SOUND_B(\r
 \r
-.I_CLK1(I_CLK_18432M),\r
+.I_CLK1(W_CLK_18M),\r
 .I_CLK2(W_CLK_6M),\r
 .I_RSTn(rst_count[3]),\r
 .I_SW({&on_game[1:0],W_HIT,W_FIRE}),\r
@@ -700,7 +638,7 @@ assign  O_SOUND_OUT_R = W_DAC_B;
 \r
 dac wav_dac_a(\r
 \r
-.Clk(I_CLK_18432M), \r
+.Clk(W_CLK_18M), \r
 .Reset(~W_RESETn),\r
 .DACin(W_SDAT_A),\r
 .DACout(W_DAC_A)\r
@@ -709,7 +647,7 @@ dac wav_dac_a(
 \r
 dac wav_dac_b(\r
 \r
-.Clk(I_CLK_18432M), \r
+.Clk(W_CLK_18M), \r
 .Reset(~W_RESETn),\r
 .DACin(W_SDAT_B),\r
 .DACout(W_DAC_B)\r