-// Module dcm
+// Module mc_dcm
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI
// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.89 ns
`timescale 1ns / 1ps
-module dcm(CLKIN_IN,
+module mc_dcm(CLKIN_IN,
RST_IN,
CLKFX_OUT,
CLKIN_IBUFG_OUT,