fix clock for LRAM
[fpga-games] / galaxian / src / mc_top.v
index 4cabd744bd9af09ff10b09f4be993047ba89da7c..99206f367ab52db4aab5ed63f99d91ed33da776e 100644 (file)
@@ -93,6 +93,7 @@ wire   W_CLK_18M;
 wire   W_CLK_36M;\r
 wire   W_CLK_12M,WB_CLK_12M;\r
 wire   W_CLK_6M,WB_CLK_6M;\r
+wire   W_CLK_6Mn;\r
 wire   W_STARS_CLK;\r
 \r
 mc_dcm clockgen(\r
@@ -148,18 +149,13 @@ mc_clock MC_CLK(
 .I_CLK_36M(W_CLK_36M),\r
 .O_CLK_18M(W_CLK_18M),\r
 .O_CLK_12M(WB_CLK_12M),\r
-.O_CLK_06M(WB_CLK_6M)\r
+.O_CLK_06M(WB_CLK_6M),\r
+.O_CLK_06Mn(W_CLK_6Mn)\r
 \r
 );\r
 \r
-`ifdef DEVICE_CYCLONE\r
 assign W_CLK_12M = WB_CLK_12M;\r
 assign W_CLK_6M  = WB_CLK_6M;\r
-`endif\r
-`ifdef DEVICE_SPARTAN2E\r
-BUFG   BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) );\r
-BUFG   BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) );\r
-`endif\r
 //---  DATA I/F -------------------------------------\r
 reg    [7:0]W_CPU_ROM_DO;\r
 wire   [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;\r
@@ -449,6 +445,7 @@ mc_video MC_VID(
 .I_CLK_18M(W_CLK_18M),\r
 .I_CLK_12M(W_CLK_12M),\r
 .I_CLK_6M(W_CLK_6M),\r
+.I_CLK_6Mn(W_CLK_6Mn),\r
 .I_H_CNT(W_H_CNT),\r
 .I_V_CNT(W_V_CNT),\r
 .I_H_FLIP(W_H_FLIP),\r
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