X-Git-Url: http://git.zerfleddert.de/cgi-bin/gitweb.cgi/fpga-games/blobdiff_plain/782690d0b2046d5fa0ae296c2fb3f411d668b5dc..0a770302362dc726e170ba3245d086d506230b05:/galaxian/src/mc_clock.v

diff --git a/galaxian/src/mc_clock.v b/galaxian/src/mc_clock.v
index 43cadb4..5ccfbd6 100644
--- a/galaxian/src/mc_clock.v
+++ b/galaxian/src/mc_clock.v
@@ -17,47 +17,61 @@
 
 module mc_clock(
 
-I_CLK_18M,
+I_CLK_36M,
+O_CLK_18M,
 O_CLK_12M,
-O_CLK_06M,
-O_CLK_06Mn
+O_CLK_06M
 
 );
 
-input  I_CLK_18M;
+input I_CLK_36M;
+output O_CLK_18M;
 output O_CLK_12M;
 output O_CLK_06M;
-output O_CLK_06Mn;
 
 // 2/3 clock divider(duty 33%)
-reg [1:0] clk_ff1,clk_ff2;
 //I_CLK   1010101010101010101
 //c_ff10  0011110011110011110
 //c_ff11  0011000011000011000
 //c_ff20  0000110000110000110
 //c_ff21  0110000110000110000
 //O_12M   0000110110110110110
-always @(posedge I_CLK_18M)
+reg [1:0] state;
+reg clk_12m;
+initial state = 0;
+initial clk_12m = 0;
+
+// 2/3 clock         (duty 66%)
+always @(posedge I_CLK_36M)
 begin
-   clk_ff1[0] <= ~clk_ff1[0] | clk_ff1[1];
-   clk_ff1[1] <= ~clk_ff1[0] & ~clk_ff1[1];
-   clk_ff2[0] <= clk_ff1[0] & clk_ff1[1];
+   case (state)
+      2'd0: state <= 2'd1;
+      2'd1: state <= 2'd2;
+      2'd2: state <= 2'd0;
+      2'd3: state <= 2'd0;
+   endcase
+
+   if (state == 2'd2)
+      clk_12m = 0;
+   else
+      clk_12m = 1;
 end
-always @(negedge I_CLK_18M)
-   clk_ff2[1] <= ~clk_ff1[0] & ~clk_ff1[1];
 
-// 2/3 clock         (duty 66%)
-assign O_CLK_12M = clk_ff2[0]| clk_ff2[1];
- 
+assign O_CLK_12M = clk_12m;
+
+reg CLK_18M;
+always @(posedge I_CLK_36M)
+begin
+   CLK_18M <= ~ CLK_18M;
+end
+assign O_CLK_18M = CLK_18M;
+
 // 1/3 clock divider (duty 50%)
-reg CLK_6M , CLK_6Mn;
+reg CLK_6M;
 always @(posedge O_CLK_12M)
 begin
-   CLK_6Mn <=  CLK_6M;
    CLK_6M  <= ~CLK_6M;
 end
 assign O_CLK_06M = CLK_6M;
-assign O_CLK_06Mn = CLK_6Mn;
-
 
-endmodule
\ No newline at end of file
+endmodule