X-Git-Url: http://git.zerfleddert.de/cgi-bin/gitweb.cgi/fpga-games/blobdiff_plain/b884ab49c82cc350e3d74264cff4b9da0d664878..4b3ff7d86485dea579af0d8fd983a36a1e9295ea:/galaxian/src/mc_top.v diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v index d8508d1..99206f3 100644 --- a/galaxian/src/mc_top.v +++ b/galaxian/src/mc_top.v @@ -33,13 +33,6 @@ psTXD, psRXD, `endif -// ROM IF -//O_ROM_AB, -//I_ROM_DB, -//O_ROM_OEn, -//O_ROM_CSn, -//O_ROM_WEn, - // INPORT SW IF I_PSW, @@ -80,13 +73,6 @@ input psRXD; output psTXD,psCLK,psSEL; `endif -// ROM IF -//output [18:0]O_ROM_AB; -//input [7:0]I_ROM_DB; -//output O_ROM_OEn; -//output O_ROM_CSn; -//output O_ROM_WEn; - // INPORT SW IF input [8:0]I_PSW; @@ -95,23 +81,25 @@ output O_SOUND_OUT_L; output O_SOUND_OUT_R; // VGA (VIDEO) IF -output [2:0]O_VGA_R; -output [2:0]O_VGA_G; -output [1:0]O_VGA_B; +output [3:0]O_VGA_R; +output [3:0]O_VGA_G; +output [3:0]O_VGA_B; output O_VGA_H_SYNCn; output O_VGA_V_SYNCn; wire W_RESETn = |(~I_PSW[8:5]); //------ CLOCK GEN --------------------------- -wire I_CLK_18432M; +wire W_CLK_18M; +wire W_CLK_36M; wire W_CLK_12M,WB_CLK_12M; wire W_CLK_6M,WB_CLK_6M; +wire W_CLK_6Mn; wire W_STARS_CLK; mc_dcm clockgen( .CLKIN_IN(I_CLK_125M), .RST_IN(! W_RESETn), -.CLKFX_OUT(I_CLK_18432M) +.CLKFX_OUT(W_CLK_36M) ); //------ H&V COUNTER ------------------------- @@ -158,20 +146,16 @@ wire [7:0]W_VID_DO; mc_clock MC_CLK( -.I_CLK_18M(I_CLK_18432M), +.I_CLK_36M(W_CLK_36M), +.O_CLK_18M(W_CLK_18M), .O_CLK_12M(WB_CLK_12M), -.O_CLK_06M(WB_CLK_6M) +.O_CLK_06M(WB_CLK_6M), +.O_CLK_06Mn(W_CLK_6Mn) ); -`ifdef DEVICE_CYCLONE assign W_CLK_12M = WB_CLK_12M; assign W_CLK_6M = WB_CLK_6M; -`endif -`ifdef DEVICE_SPARTAN2E -BUFG BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) ); -BUFG BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) ); -`endif //--- DATA I/F ------------------------------------- reg [7:0]W_CPU_ROM_DO; wire [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ; @@ -343,7 +327,7 @@ wire VIB_SW = died & (&on_game[1:0]); fpga_arcade_if pspad( -.CLK_18M432(I_CLK_18432M), +.CLK_18M432(W_CLK_18M), .I_RSTn(W_RESETn), .psCLK(psCLK), .psSEL(psSEL), @@ -410,75 +394,23 @@ mc_inport MC_INPORT( //----------------------------------------------------------------------------- //------- ROM ------------------------------------------------------- reg [18:0]ROM_A; -wire [10:0]W_OBJ_ROM_A; -reg [7:0]W_OBJ_ROM_A_D; -reg [7:0]W_OBJ_ROM_B_D; wire [18:0]W_WAV_A0,W_WAV_A1,W_WAV_A2; reg [7:0]W_WAV_D0,W_WAV_D1,W_WAV_D2; -wire [7:0]ROM_D; // = I_ROM_DB; -//assign O_ROM_AB = ROM_A; - -//assign O_ROM_OEn = 1'b0; -//assign O_ROM_CSn = 1'b0; -//assign O_ROM_WEn = 1'b1; +wire [7:0]ROM_D; galaxian_roms ROMS( -.I_CLK_12M(WB_CLK_12M), -.I_ADDR(ROM_A), +.I_ROM_CLK(W_CLK_12M), +.I_ADDR({3'h0,W_A[15:0]}), .O_DATA(ROM_D) ); - -reg [1:0]clk_d; -reg [4:0]seq; -always @(posedge I_CLK_18432M) +always@(posedge W_CLK_12M) begin - // 24 phase generator - clk_d[0] <= W_H_CNT[0] & W_H_CNT[1] & W_H_CNT[2]; - clk_d[1] <= clk_d[0]; - seq <= (~clk_d[1] & clk_d[0]) ? 0 : seq+1; - case(seq) - 0:begin - //sound - ROM_A <= W_WAV_A0; - W_CPU_ROM_DO <= ROM_D; - end - 2:begin - //sound - ROM_A <= W_WAV_A1; - W_WAV_D0 <= ROM_D; - end - 4:begin - //sound - ROM_A <= {3'h0,W_A[15:0]}; - W_WAV_D1 <= ROM_D; - end - 6:begin - //sound - ROM_A <= W_WAV_A2; - W_CPU_ROM_DO <= ROM_D; - end - 8:W_WAV_D2 <= ROM_D; //sound - 10:ROM_A <= {3'h0,W_A[15:0]}; - 12:W_CPU_ROM_DO <= ROM_D; - 16:ROM_A <= {3'h0,W_A[15:0]}; - 18:begin - ROM_A <= {3'h0,4'h4,1'b0,W_OBJ_ROM_A}; - W_CPU_ROM_DO <= ROM_D; - end - 20:begin - ROM_A <= {3'h0,4'h5,1'b0,W_OBJ_ROM_A}; - W_OBJ_ROM_A_D <= ROM_D; - end - 22:begin - ROM_A <= {3'h0,W_A[15:0]}; - W_OBJ_ROM_B_D <= ROM_D; - end - default:; - endcase + W_CPU_ROM_DO <= ROM_D; end + //----------------------------------------------------------------------------- wire W_V_BL2n; @@ -510,9 +442,10 @@ wire [1:0]W_VID; wire [2:0]W_COL; mc_video MC_VID( -.I_CLK_18M(I_CLK_18432M), +.I_CLK_18M(W_CLK_18M), .I_CLK_12M(W_CLK_12M), .I_CLK_6M(W_CLK_6M), +.I_CLK_6Mn(W_CLK_6Mn), .I_H_CNT(W_H_CNT), .I_V_CNT(W_V_CNT), .I_H_FLIP(W_H_FLIP), @@ -529,10 +462,6 @@ mc_video MC_VID( .I_VID_RAM_RDn(W_VID_RAM_RDn), .I_VID_RAM_WRn(W_VID_RAM_WRn), -.O_OBJ_ROM_A(W_OBJ_ROM_A), -.I_OBJ_ROM_A_D(W_OBJ_ROM_A_D), -.I_OBJ_ROM_B_D(W_OBJ_ROM_B_D), - .O_C_BLnX(W_C_BLnX), .O_8HF(W_8HF), .O_256HnX(W_256HnX), @@ -573,7 +502,7 @@ wire [1:0]W_STARS_B; mc_stars MC_STARS( -.I_CLK_18M(I_CLK_18432M), +.I_CLK_18M(W_CLK_18M), `ifdef DEVICE_CYCLONE .I_CLK_6M(~WB_CLK_6M), `endif @@ -620,6 +549,10 @@ mc_vedio_mix MIX( ); +wire [2:0]W_VGA_R; +wire [2:0]W_VGA_G; +wire [1:0]W_VGA_B; + `ifdef VGA_USE mc_vga_if VGA( @@ -632,9 +565,9 @@ mc_vga_if VGA( .I_H_SYNC(W_H_SYNC), .I_V_SYNC(W_V_SYNC), // output -.O_R(O_VGA_R), -.O_G(O_VGA_G), -.O_B(O_VGA_B), +.O_R(W_VGA_R), +.O_G(W_VGA_G), +.O_B(W_VGA_B), .O_H_SYNCn(O_VGA_H_SYNCn), .O_V_SYNCn(O_VGA_V_SYNCn) @@ -642,11 +575,11 @@ mc_vga_if VGA( `else -assign O_VGA_R[2:0] = W_R; +assign W_VGA_R[2:0] = W_R; -assign O_VGA_G[2:0] = W_G; +assign W_VGA_G[2:0] = W_G; -assign O_VGA_B[1:0] = W_B; +assign W_VGA_B[1:0] = W_B; //assign O_VGA_H_SYNCn = W_H_SYNC | W_V_SYNC ; // AKIDUKI LCD USED assign O_VGA_H_SYNCn = ~W_H_SYNC ; @@ -654,6 +587,12 @@ assign O_VGA_V_SYNCn = ~W_V_SYNC ; `endif +assign O_VGA_R[3:0] = {W_VGA_R[0], W_VGA_R[1], W_VGA_R[2], 1'b0}; + +assign O_VGA_G[3:0] = {W_VGA_G[0], W_VGA_G[1], W_VGA_G[2], 1'b0}; + +assign O_VGA_B[3:0] = {W_VGA_B[0], W_VGA_B[1], 2'b0}; + wire [7:0]W_SDAT_A; mc_sound_a MC_SOUND_A( @@ -675,7 +614,7 @@ wire [7:0]W_SDAT_B; mc_sound_b MC_SOUND_B( -.I_CLK1(I_CLK_18432M), +.I_CLK1(W_CLK_18M), .I_CLK2(W_CLK_6M), .I_RSTn(rst_count[3]), .I_SW({&on_game[1:0],W_HIT,W_FIRE}), @@ -699,7 +638,7 @@ assign O_SOUND_OUT_R = W_DAC_B; dac wav_dac_a( -.Clk(I_CLK_18432M), +.Clk(W_CLK_18M), .Reset(~W_RESETn), .DACin(W_SDAT_A), .DACout(W_DAC_A) @@ -708,7 +647,7 @@ dac wav_dac_a( dac wav_dac_b( -.Clk(I_CLK_18432M), +.Clk(W_CLK_18M), .Reset(~W_RESETn), .DACin(W_SDAT_B), .DACout(W_DAC_B)