From: Michael Gernoth <michael@gernoth.net>
Date: Wed, 30 Apr 2008 23:31:10 +0000 (+0200)
Subject: fix rom address decoder
X-Git-Url: http://git.zerfleddert.de/cgi-bin/gitweb.cgi/fpga-games/commitdiff_plain/b884ab49c82cc350e3d74264cff4b9da0d664878

fix rom address decoder
---

diff --git a/galaxian/galaxian.ucf b/galaxian/galaxian.ucf
index 3a8e011..44165bb 100644
--- a/galaxian/galaxian.ucf
+++ b/galaxian/galaxian.ucf
@@ -1,5 +1,11 @@
-### UCF file for FPGA-MOONCRST on XC2S200E
-#
+CONFIG PART = XC3SD1800A-FG676-4;
+
+NET I_CLK_125M	TNM_NET = clk_ref_grp;
+TIMESPEC TS01 = PERIOD : clk_ref_grp : 8.00 : PRIORITY 1; #125 MHz
+
+TIMESPEC TS11=FROM:PADS:TO:FFS : 30 ns;
+TIMESPEC TS12=FROM:FFS:TO:PADS : 30 ns;
+
 #---------- MasterClock 18.432MHz ----------
 NET "I_CLK_125M" LOC = "F13" | IOSTANDARD = LVCMOS33;
 #-------------------------------------------
diff --git a/galaxian/src/dcm.v b/galaxian/src/dcm.v
index 13f9f5f..64541bc 100644
--- a/galaxian/src/dcm.v
+++ b/galaxian/src/dcm.v
@@ -1,11 +1,11 @@
-// Module dcm
+// Module mc_dcm
 // Generated by Xilinx Architecture Wizard
 // Written for synthesis tool: XST
 // Period Jitter (unit interval) for block DCM_SP_INST = 0.02 UI
 // Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.89 ns
 `timescale 1ns / 1ps
 
-module dcm(CLKIN_IN, 
+module mc_dcm(CLKIN_IN, 
            RST_IN, 
            CLKFX_OUT, 
            CLKIN_IBUFG_OUT, 
diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v
index c382b64..d8508d1 100644
--- a/galaxian/src/mc_top.v
+++ b/galaxian/src/mc_top.v
@@ -108,7 +108,7 @@ wire   W_CLK_12M,WB_CLK_12M;
 wire   W_CLK_6M,WB_CLK_6M;
 wire   W_STARS_CLK;
 
-dcm clockgen(
+mc_dcm clockgen(
 .CLKIN_IN(I_CLK_125M),
 .RST_IN(! W_RESETn),
 .CLKFX_OUT(I_CLK_18432M)
@@ -425,7 +425,6 @@ wire   [7:0]ROM_D; // = I_ROM_DB;
 //assign O_ROM_WEn = 1'b1;
 
 galaxian_roms ROMS(
-.I_CLK_18432M(I_CLK_18432M),
 .I_CLK_12M(WB_CLK_12M),
 .I_ADDR(ROM_A),
 .O_DATA(ROM_D)
diff --git a/galaxian/src/mc_video.v b/galaxian/src/mc_video.v
index aafdcd3..c93b557 100644
--- a/galaxian/src/mc_video.v
+++ b/galaxian/src/mc_video.v
@@ -148,7 +148,7 @@ wire   [7:3]W_HF_CNT = I_H_CNT[7:3]^{5{W_H_FLIP1}};
 wire   [7:0]W_VF_CNT = I_V_CNT[7:0]^{8{I_V_FLIP}};
 
 assign O_8HF = W_HF_CNT[3];
-assign O_1VF = I_V_CNT[0]^1'b1; //XXX: breaks when flipped
+assign O_1VF = W_VF_CNT[0];
 
 reg    [7:0]W_OBJ_D;
 wire   [3:0]W_6J_DA = {I_H_FLIP  ,           W_HF_CNT[7],W_HF_CNT[3],I_H_CNT[2]};
diff --git a/galaxian/src/roms.v b/galaxian/src/roms.v
index 02c0bd2..2ca0d07 100644
--- a/galaxian/src/roms.v
+++ b/galaxian/src/roms.v
@@ -1,85 +1,76 @@
 module galaxian_roms(
-I_CLK_18432M,
 I_CLK_12M,
 I_ADDR,
 O_DATA
 );
 
 input I_CLK_12M;
-input I_CLK_18432M;
 input [18:0]I_ADDR;
 output [7:0]O_DATA;
 
 //CPU-Roms
 wire [7:0]U_ROM_D;
-reg [10:0]U_ROM_A;
 
 GALAXIAN_U U_ROM(
 .CLK(I_CLK_12M),
-.ADDR(U_ROM_A),
+.ADDR(I_ADDR[10:0]),
 .DATA(U_ROM_D),
 .ENA(1'b1)
 );
 
 wire [7:0]V_ROM_D;
-reg [10:0]V_ROM_A;
 
 GALAXIAN_V V_ROM(
 .CLK(I_CLK_12M),
-.ADDR(V_ROM_A),
+.ADDR(I_ADDR[10:0]),
 .DATA(V_ROM_D),
 .ENA(1'b1)
 );
 
 wire [7:0]W_ROM_D;
-reg [10:0]W_ROM_A;
 
 GALAXIAN_W W_ROM(
 .CLK(I_CLK_12M),
-.ADDR(W_ROM_A),
+.ADDR(I_ADDR[10:0]),
 .DATA(W_ROM_D),
 .ENA(1'b1)
 );
 
 wire [7:0]Y_ROM_D;
-reg [10:0]Y_ROM_A;
 
 GALAXIAN_Y Y_ROM(
 .CLK(I_CLK_12M),
-.ADDR(Y_ROM_A),
+.ADDR(I_ADDR[10:0]),
 .DATA(Y_ROM_D),
 .ENA(1'b1)
 );
 
 //7L CPU-Rom
 wire [7:0]L_ROM_D;
-reg [10:0]L_ROM_A;
 
 GALAXIAN_7L L_ROM(
 .CLK(I_CLK_12M),
-.ADDR(L_ROM_A),
+.ADDR(I_ADDR[10:0]),
 .DATA(L_ROM_D),
 .ENA(1'b1)
 );
 
 //1K VID-Rom
 wire [7:0]K_ROM_D;
-reg [10:0]K_ROM_A;
 
 GALAXIAN_1K K_ROM(
 .CLK(I_CLK_12M),
-.ADDR(K_ROM_A),
+.ADDR(I_ADDR[10:0]),
 .DATA(K_ROM_D),
 .ENA(1'b1)
 );
 
 //1H VID-Rom
 wire [7:0]H_ROM_D;
-reg [10:0]H_ROM_A;
 
 GALAXIAN_1H H_ROM(
 .CLK(I_CLK_12M),
-.ADDR(H_ROM_A),
+.ADDR(I_ADDR[10:0]),
 .DATA(H_ROM_D),
 .ENA(1'b1)
 );
@@ -96,47 +87,43 @@ reg [7:0]DATA_OUT;
 // 0x04000 - 0x047FF       1k.bin           VID-ROM
 // 0x05000 - 0x057FF       1h.bin           VID-ROM
 // 0x10000 - 0x3FFFF       mc_wav_2.bin     Sound(Wav)Data
-always
+always@(I_ADDR or U_ROM_D or V_ROM_D or W_ROM_D or Y_ROM_D or L_ROM_D or K_ROM_D or H_ROM_D)
 begin
 	if (I_ADDR <= 18'h7ff) begin
 		//u
-		U_ROM_A <= I_ADDR[10:0];
 		DATA_OUT <= U_ROM_D;
 	end
-	if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
+	else if (I_ADDR >= 18'h800 && I_ADDR <= 18'hfff) begin
 		//v
-		V_ROM_A <= I_ADDR[10:0];
 		DATA_OUT <= V_ROM_D;
 	end
-	if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
+	else if (I_ADDR >= 18'h1000 && I_ADDR <= 18'h17ff) begin
 		//w
-		W_ROM_A <= I_ADDR[10:0];
 		DATA_OUT <= W_ROM_D;
 	end
-	if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
+	else if (I_ADDR >= 18'h1800 && I_ADDR <= 18'h1fff) begin
 		//y
-		Y_ROM_A <= I_ADDR[10:0];
 		DATA_OUT <= Y_ROM_D;
 	end
-	if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
+	else if (I_ADDR >= 18'h2000 && I_ADDR <= 18'h27ff) begin
 		//7l
-		L_ROM_A <= I_ADDR[10:0];
 		DATA_OUT <= L_ROM_D;
 	end
-	if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
+	else if (I_ADDR >= 18'h4000 && I_ADDR <= 18'h47ff) begin
 		//1k
-		K_ROM_A <= I_ADDR[10:0];
 		DATA_OUT <= K_ROM_D;
 	end
-	if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
+	else if (I_ADDR >= 18'h5000 && I_ADDR <= 18'h57ff) begin
 		//1h
-		H_ROM_A <= I_ADDR[10:0];
 		DATA_OUT <= H_ROM_D;
 	end
-	if (I_ADDR >= 18'h10000 && I_ADDR <= 18'h3fff) begin
+	else if (I_ADDR >= 18'h10000 && I_ADDR <= 18'h3fff) begin
 		//sound
 		DATA_OUT <= 8'h00;
 	end
+	else begin
+		DATA_OUT <= 8'h00;
+	end
 end
 
 assign O_DATA = DATA_OUT;