[linexec-j720] / asm / asm-wince.asm

	TTL	C:\pocket\test\asm.cpp\r\r
\r\r
	AREA	|.drectve|, DRECTVE\r\r
	DCB	"-defaultlib:coredll.lib "\r\r
	DCB	"-defaultlib:corelibc.lib "\r\r
\r\r
	EXPORT	|?do_it@@YAXXZ|				; do_it\r\r
	AREA	|.pdata|, PDATA\r\r
|$T222|	DCD	|?do_it@@YAXXZ|\r\r
	DCD	0x40000100\r\r
	AREA	|.text|, CODE\r\r
|?do_it@@YAXXZ| PROC					; do_it\r\r
|$M220|\r\r
	\r\r
	mcr     p15, 0, r0, c7, c5, 0 		;/* invalidate i cache & BTB */\r\r
										;	CPWAIT  r0\r\r
	mrc	p15, 0, r0, c2, c0, 0\r\r
	mov	r0, r0\r\r
	sub 	pc, pc, #4		\r\r
										;	ldr	r9, =0xa1300100\r\r
\r\r
		mov		r9, r1					;	add		r9, r1, #0x100	\r\r
		ldr		r5, =0xa0000100			;	ldr		r5, =0xa0000100\r\r
		ldr		r7, =0xa0100000\r\r
label   ldr     r8, [r9]\r\r
        str     r8, [r5]\r\r
		add     r9, r9, #4 \r\r
		add     r5, r5, #4 \r\r
		cmp		r5, r7\r\r
		blt		label\r\r
\r\r
crash	b crash\r\r
\r\r
	MOV		r4, #0xA0000000\r\r
	add		r2,r4,#0x8000\r\r
	\r\r
	mov 	r11,r2\r\r
	ldr		r10,=337\r\r
\r\r
;	mcr     p15, 0, r0, c7, c10, 4 ;/* drain the write buffer*/\r\r
\r\r
;	CPWAIT  r0\r\r
;	mrc	p15, 0, r0, c2, c0, 0\r\r
;	mov	r0, r0\r\r
;	sub 	pc, pc, #4		\r\r
\r\r
\r\r
	mcr	p15, 0, r0, c8, c7, 0x00 	;/* invalidate I+D TLB */\r\r
;	CPWAIT  r0\r\r
	mrc	p15, 0, r0, c2, c0, 0\r\r
	mov	r0, r0\r\r
	sub 	pc, pc, #4		\r\r
\r\r
;	//; they skipped this, unnecessary? seems like we need to do this\r\r
	mcr     p15, 0, r0, c7, c5, 0 		;/* invalidate i cache & BTB */\r\r
	\r\r
; S bit set, p and d bit set (no 26 bit mode)\r\r
;	mov     r3, #0x120 	; xscale says p needs to be 0 ???\r\r
;	mcr     p15, 0, r3, c1, c0, 0   ;/* disable the MMU */\r\r
\r\r
;	CPWAIT  r0\r\r
;	mrc	p15, 0, r0, c2, c0, 0\r\r
;	mov	r0, r0\r\r
;	sub 	pc, pc, #4		\r\r
\r\r
\r\r
;        /*; make sure the pipeline is emptied*/\r\r
        mov     r0,#0\r\r
        mov     r0,r0\r\r
        mov     r0,r0\r\r
        mov     r0,r0\r\r
\r\r
;	/* zero PID in Process ID Virtual Address Map register. */\r\r
;	mov	r0, #0\r\r
	mcr	p15, 0, r0, c13, c0, 0\r\r
\r\r
\r\r
;	CPWAIT  r0\r\r
	mrc	p15, 0, r0, c2, c0, 0\r\r
	mov	r0, r0\r\r
	sub 	pc, pc, #4		\r\r
\r\r
;	ldr	r5, =0xA00512F5\r\r
;	ldr	r8, =0xefef0000\r\r
;	str     r8, [r5] \r\r
\r\r
\r\r
	mov     r0, #0\r\r
    mov     r1, r10\r\r
	ldr     r2, [r2, #0]\r\r
	mov     r2, #0\r\r
	mov	pc, r11	\r\r
\r\r
\r\r
|$M221|\r\r
\r\r
	ENDP  ; |?do_it@@YAXXZ|, do_it\r\r
\r\r
	END\r\r
Commit	Line	Data
77a37381	1	TTL C:\pocket\test\asm.cpp\r\r
	2	\r\r
	3	AREA \|.drectve\|, DRECTVE\r\r
	4	DCB "-defaultlib:coredll.lib "\r\r
	5	DCB "-defaultlib:corelibc.lib "\r\r
	6	\r\r
	7	EXPORT \|?do_it@@YAXXZ\| ; do_it\r\r
	8	AREA \|.pdata\|, PDATA\r\r
	9	\|$T222\| DCD \|?do_it@@YAXXZ\|\r\r
	10	DCD 0x40000100\r\r
	11	AREA \|.text\|, CODE\r\r
	12	\|?do_it@@YAXXZ\| PROC ; do_it\r\r
	13	\|$M220\|\r\r
	14	\r\r
	15	mcr p15, 0, r0, c7, c5, 0 ;/* invalidate i cache & BTB */\r\r
	16	; CPWAIT r0\r\r
	17	mrc p15, 0, r0, c2, c0, 0\r\r
	18	mov r0, r0\r\r
	19	sub pc, pc, #4 \r\r
	20	; ldr r9, =0xa1300100\r\r
	21	\r\r
	22	mov r9, r1 ; add r9, r1, #0x100 \r\r
	23	ldr r5, =0xa0000100 ; ldr r5, =0xa0000100\r\r
	24	ldr r7, =0xa0100000\r\r
	25	label ldr r8, [r9]\r\r
	26	str r8, [r5]\r\r
	27	add r9, r9, #4 \r\r
	28	add r5, r5, #4 \r\r
	29	cmp r5, r7\r\r
	30	blt label\r\r
	31	\r\r
	32	crash b crash\r\r
	33	\r\r
	34	MOV r4, #0xA0000000\r\r
	35	add r2,r4,#0x8000\r\r
	36	\r\r
	37	mov r11,r2\r\r
	38	ldr r10,=337\r\r
	39	\r\r
	40	; mcr p15, 0, r0, c7, c10, 4 ;/* drain the write buffer*/\r\r
	41	\r\r
	42	; CPWAIT r0\r\r
	43	; mrc p15, 0, r0, c2, c0, 0\r\r
	44	; mov r0, r0\r\r
	45	; sub pc, pc, #4 \r\r
	46	\r\r
	47	\r\r
	48	mcr p15, 0, r0, c8, c7, 0x00 ;/* invalidate I+D TLB */\r\r
	49	; CPWAIT r0\r\r
	50	mrc p15, 0, r0, c2, c0, 0\r\r
	51	mov r0, r0\r\r
	52	sub pc, pc, #4 \r\r
	53	\r\r
	54	; //; they skipped this, unnecessary? seems like we need to do this\r\r
	55	mcr p15, 0, r0, c7, c5, 0 ;/* invalidate i cache & BTB */\r\r
	56	\r\r
	57	; S bit set, p and d bit set (no 26 bit mode)\r\r
	58	; mov r3, #0x120 ; xscale says p needs to be 0 ???\r\r
	59	; mcr p15, 0, r3, c1, c0, 0 ;/* disable the MMU */\r\r
	60	\r\r
	61	; CPWAIT r0\r\r
	62	; mrc p15, 0, r0, c2, c0, 0\r\r
	63	; mov r0, r0\r\r
	64	; sub pc, pc, #4 \r\r
65	\r\r
66	\r\r
67	; /; make sure the pipeline is emptied/\r\r
68	mov r0,#0\r\r
69	mov r0,r0\r\r
70	mov r0,r0\r\r
71	mov r0,r0\r\r
72	\r\r
73	; /* zero PID in Process ID Virtual Address Map register. */\r\r
74	; mov r0, #0\r\r
75	mcr p15, 0, r0, c13, c0, 0\r\r
76	\r\r
77	\r\r
78	; CPWAIT r0\r\r
79	mrc p15, 0, r0, c2, c0, 0\r\r
80	mov r0, r0\r\r
81	sub pc, pc, #4 \r\r
82	\r\r
83	; ldr r5, =0xA00512F5\r\r
84	; ldr r8, =0xefef0000\r\r
85	; str r8, [r5] \r\r
86	\r\r
87	\r\r
88	mov r0, #0\r\r
89	mov r1, r10\r\r
90	ldr r2, [r2, #0]\r\r
91	mov r2, #0\r\r
92	mov pc, r11 \r\r
93	\r\r
94	\r\r
95	\|$M221\|\r\r
96	\r\r
97	ENDP ; \|?do_it@@YAXXZ\|, do_it\r\r
98	\r\r
99	END\r\r