[ms2-kexec] / assembler.h

/*
 *  arch/arm/include/asm/assembler.h
 *
 *  Copyright (C) 1996-2000 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This file contains arm architecture specific defines
 *  for the different processors.
 *
 *  Do not include any C declarations in this file - it is included by
 *  assembler source.
 */
#ifndef __ASSEMBLY__
#error "Only include this from assembly code"
#endif

#include <asm/ptrace.h>
#include <asm/domain.h>

/*
 * Endian independent macros for shifting bytes within registers.
 */
#ifndef __ARMEB__
#define pull            lsr
#define push            lsl
#define get_byte_0      lsl #0
#define get_byte_1	lsr #8
#define get_byte_2	lsr #16
#define get_byte_3	lsr #24
#define put_byte_0      lsl #0
#define put_byte_1	lsl #8
#define put_byte_2	lsl #16
#define put_byte_3	lsl #24
#else
#define pull            lsl
#define push            lsr
#define get_byte_0	lsr #24
#define get_byte_1	lsr #16
#define get_byte_2	lsr #8
#define get_byte_3      lsl #0
#define put_byte_0	lsl #24
#define put_byte_1	lsl #16
#define put_byte_2	lsl #8
#define put_byte_3      lsl #0
#endif

/*
 * Data preload for architectures that support it
 */
#if __LINUX_ARM_ARCH__ >= 5
#define PLD(code...)	code
#else
#define PLD(code...)
#endif

/*
 * This can be used to enable code to cacheline align the destination
 * pointer when bulk writing to memory.  Experiments on StrongARM and
 * XScale didn't show this a worthwhile thing to do when the cache is not
 * set to write-allocate (this would need further testing on XScale when WA
 * is used).
 *
 * On Feroceon there is much to gain however, regardless of cache mode.
 */
#ifdef CONFIG_CPU_FEROCEON
#define CALGN(code...) code
#else
#define CALGN(code...)
#endif

/*
 * Enable and disable interrupts
 */
#if __LINUX_ARM_ARCH__ >= 6
	.macro	disable_irq_notrace
	cpsid	i
	.endm

	.macro	enable_irq_notrace
	cpsie	i
	.endm
#else
	.macro	disable_irq_notrace
	msr	cpsr_c, #PSR_I_BIT | SVC_MODE
	.endm

	.macro	enable_irq_notrace
	msr	cpsr_c, #SVC_MODE
	.endm
#endif

	.macro asm_trace_hardirqs_off
#if defined(CONFIG_TRACE_IRQFLAGS)
	stmdb   sp!, {r0-r3, ip, lr}
	bl	trace_hardirqs_off
	ldmia	sp!, {r0-r3, ip, lr}
#endif
	.endm

	.macro asm_trace_hardirqs_on_cond, cond
#if defined(CONFIG_TRACE_IRQFLAGS)
	/*
	 * actually the registers should be pushed and pop'd conditionally, but
	 * after bl the flags are certainly clobbered
	 */
	stmdb   sp!, {r0-r3, ip, lr}
	bl\cond	trace_hardirqs_on
	ldmia	sp!, {r0-r3, ip, lr}
#endif
	.endm

	.macro asm_trace_hardirqs_on
	asm_trace_hardirqs_on_cond al
	.endm

	.macro disable_irq
	disable_irq_notrace
	asm_trace_hardirqs_off
	.endm

	.macro enable_irq
	asm_trace_hardirqs_on
	enable_irq_notrace
	.endm
/*
 * Save the current IRQ state and disable IRQs.  Note that this macro
 * assumes FIQs are enabled, and that the processor is in SVC mode.
 */
	.macro	save_and_disable_irqs, oldcpsr
	mrs	\oldcpsr, cpsr
	disable_irq
	.endm

/*
 * Restore interrupt state previously stored in a register.  We don't
 * guarantee that this will preserve the flags.
 */
	.macro	restore_irqs_notrace, oldcpsr
	msr	cpsr_c, \oldcpsr
	.endm

	.macro restore_irqs, oldcpsr
	tst	\oldcpsr, #PSR_I_BIT
	asm_trace_hardirqs_on_cond eq
	restore_irqs_notrace \oldcpsr
	.endm

#define USER(x...)				\
9999:	x;					\
	.pushsection __ex_table,"a";		\
	.align	3;				\
	.long	9999b,9001f;			\
	.popsection

#ifdef CONFIG_SMP
#define ALT_SMP(instr...)					\
9998:	instr
/*
 * Note: if you get assembler errors from ALT_UP() when building with
 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
 * ALT_SMP( W(instr) ... )
 */
#define ALT_UP(instr...)					\
	.pushsection ".alt.smp.init", "a"			;\
	.long	9998b						;\
9997:	instr							;\
	.if . - 9997b != 4					;\
		.error "ALT_UP() content must assemble to exactly 4 bytes";\
	.endif							;\
	.popsection
#define ALT_UP_B(label)					\
	.equ	up_b_offset, label - 9998b			;\
	.pushsection ".alt.smp.init", "a"			;\
	.long	9998b						;\
	W(b)	. + up_b_offset					;\
	.popsection
#else
#define ALT_SMP(instr...)
#define ALT_UP(instr...) instr
#define ALT_UP_B(label) b label
#endif

/*
 * SMP data memory barrier
 */
	.macro	smp_dmb mode
#ifdef CONFIG_SMP
#if __LINUX_ARM_ARCH__ >= 7
	.ifeqs "\mode","arm"
	ALT_SMP(dmb)
	.else
	ALT_SMP(W(dmb))
	.endif
#elif __LINUX_ARM_ARCH__ == 6
	ALT_SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
#else
#error Incompatible SMP platform
#endif
	.ifeqs "\mode","arm"
	ALT_UP(nop)
	.else
	ALT_UP(W(nop))
	.endif
#endif
	.endm

#ifdef CONFIG_THUMB2_KERNEL
	.macro	setmode, mode, reg
	mov	\reg, #\mode
	msr	cpsr_c, \reg
	.endm
#else
	.macro	setmode, mode, reg
	msr	cpsr_c, #\mode
	.endm
#endif

/*
 * STRT/LDRT access macros with ARM and Thumb-2 variants
 */
#ifdef CONFIG_THUMB2_KERNEL

	.macro	usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T()
9999:
	.if	\inc == 1
	\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
	.elseif	\inc == 4
	\instr\cond\()\t\().w \reg, [\ptr, #\off]
	.else
	.error	"Unsupported inc macro argument"
	.endif

	.pushsection __ex_table,"a"
	.align	3
	.long	9999b, \abort
	.popsection
	.endm

	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort
	@ explicit IT instruction needed because of the label
	@ introduced by the USER macro
	.ifnc	\cond,al
	.if	\rept == 1
	itt	\cond
	.elseif	\rept == 2
	ittt	\cond
	.else
	.error	"Unsupported rept macro argument"
	.endif
	.endif

	@ Slightly optimised to avoid incrementing the pointer twice
	usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
	.if	\rept == 2
	usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
	.endif

	add\cond \ptr, #\rept * \inc
	.endm

#else	/* !CONFIG_THUMB2_KERNEL */

	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort, t=T()
	.rept	\rept
9999:
	.if	\inc == 1
	\instr\cond\()b\()\t \reg, [\ptr], #\inc
	.elseif	\inc == 4
	\instr\cond\()\t \reg, [\ptr], #\inc
	.else
	.error	"Unsupported inc macro argument"
	.endif

	.pushsection __ex_table,"a"
	.align	3
	.long	9999b, \abort
	.popsection
	.endr
	.endm

#endif	/* CONFIG_THUMB2_KERNEL */

	.macro	strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
	usracc	str, \reg, \ptr, \inc, \cond, \rept, \abort
	.endm

	.macro	ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
	usracc	ldr, \reg, \ptr, \inc, \cond, \rept, \abort
	.endm
Commit	Line	Data
0c549ba1 MG	1	/*
	2	* arch/arm/include/asm/assembler.h
	3	*
	4	* Copyright (C) 1996-2000 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This file contains arm architecture specific defines
	11	* for the different processors.
	12	*
	13	* Do not include any C declarations in this file - it is included by
	14	* assembler source.
	15	*/
	16	#ifndef __ASSEMBLY__
	17	#error "Only include this from assembly code"
	18	#endif
	19
	20	#include <asm/ptrace.h>
	21	#include <asm/domain.h>
	22
	23	/*
	24	* Endian independent macros for shifting bytes within registers.
	25	*/
	26	#ifndef __ARMEB__
	27	#define pull lsr
	28	#define push lsl
	29	#define get_byte_0 lsl #0
	30	#define get_byte_1 lsr #8
	31	#define get_byte_2 lsr #16
	32	#define get_byte_3 lsr #24
	33	#define put_byte_0 lsl #0
	34	#define put_byte_1 lsl #8
	35	#define put_byte_2 lsl #16
	36	#define put_byte_3 lsl #24
	37	#else
	38	#define pull lsl
	39	#define push lsr
	40	#define get_byte_0 lsr #24
	41	#define get_byte_1 lsr #16
	42	#define get_byte_2 lsr #8
	43	#define get_byte_3 lsl #0
	44	#define put_byte_0 lsl #24
	45	#define put_byte_1 lsl #16
	46	#define put_byte_2 lsl #8
	47	#define put_byte_3 lsl #0
	48	#endif
	49
	50	/*
	51	* Data preload for architectures that support it
	52	*/
	53	#if __LINUX_ARM_ARCH__ >= 5
	54	#define PLD(code...) code
	55	#else
	56	#define PLD(code...)
	57	#endif
	58
	59	/*
	60	* This can be used to enable code to cacheline align the destination
	61	* pointer when bulk writing to memory. Experiments on StrongARM and
	62	* XScale didn't show this a worthwhile thing to do when the cache is not
	63	* set to write-allocate (this would need further testing on XScale when WA
	64	* is used).
65	*
66	* On Feroceon there is much to gain however, regardless of cache mode.
67	*/
68	#ifdef CONFIG_CPU_FEROCEON
69	#define CALGN(code...) code
70	#else
71	#define CALGN(code...)
72	#endif
73
74	/*
75	* Enable and disable interrupts
76	*/
77	#if __LINUX_ARM_ARCH__ >= 6
78	.macro disable_irq_notrace
79	cpsid i
80	.endm
81
82	.macro enable_irq_notrace
83	cpsie i
84	.endm
85	#else
86	.macro disable_irq_notrace
87	msr cpsr_c, #PSR_I_BIT \| SVC_MODE
88	.endm
89
90	.macro enable_irq_notrace
91	msr cpsr_c, #SVC_MODE
92	.endm
93	#endif
94
95	.macro asm_trace_hardirqs_off
96	#if defined(CONFIG_TRACE_IRQFLAGS)
97	stmdb sp!, {r0-r3, ip, lr}
98	bl trace_hardirqs_off
99	ldmia sp!, {r0-r3, ip, lr}
100	#endif
101	.endm
102
103	.macro asm_trace_hardirqs_on_cond, cond
104	#if defined(CONFIG_TRACE_IRQFLAGS)
105	/*
106	* actually the registers should be pushed and pop'd conditionally, but
107	* after bl the flags are certainly clobbered
108	*/
109	stmdb sp!, {r0-r3, ip, lr}
110	bl\cond trace_hardirqs_on
111	ldmia sp!, {r0-r3, ip, lr}
112	#endif
113	.endm
114
115	.macro asm_trace_hardirqs_on
116	asm_trace_hardirqs_on_cond al
117	.endm
118
119	.macro disable_irq
120	disable_irq_notrace
121	asm_trace_hardirqs_off
122	.endm
123
124	.macro enable_irq
125	asm_trace_hardirqs_on
126	enable_irq_notrace
127	.endm
128	/*
129	* Save the current IRQ state and disable IRQs. Note that this macro
130	* assumes FIQs are enabled, and that the processor is in SVC mode.
131	*/
132	.macro save_and_disable_irqs, oldcpsr
133	mrs \oldcpsr, cpsr
134	disable_irq
135	.endm
136
137	/*
138	* Restore interrupt state previously stored in a register. We don't
139	* guarantee that this will preserve the flags.
140	*/
141	.macro restore_irqs_notrace, oldcpsr
142	msr cpsr_c, \oldcpsr
143	.endm
144
145	.macro restore_irqs, oldcpsr
146	tst \oldcpsr, #PSR_I_BIT
147	asm_trace_hardirqs_on_cond eq
148	restore_irqs_notrace \oldcpsr
149	.endm
150
151	#define USER(x...) \
152	9999: x; \
153	.pushsection __ex_table,"a"; \
154	.align 3; \
155	.long 9999b,9001f; \
156	.popsection
157
158	#ifdef CONFIG_SMP
159	#define ALT_SMP(instr...) \
160	9998: instr
161	/*
162	* Note: if you get assembler errors from ALT_UP() when building with
163	* CONFIG_THUMB2_KERNEL, you almost certainly need to use
164	* ALT_SMP( W(instr) ... )
165	*/
166	#define ALT_UP(instr...) \
167	.pushsection ".alt.smp.init", "a" ;\
168	.long 9998b ;\
169	9997: instr ;\
170	.if . - 9997b != 4 ;\
171	.error "ALT_UP() content must assemble to exactly 4 bytes";\
172	.endif ;\
173	.popsection
174	#define ALT_UP_B(label) \
175	.equ up_b_offset, label - 9998b ;\
176	.pushsection ".alt.smp.init", "a" ;\
177	.long 9998b ;\
178	W(b) . + up_b_offset ;\
179	.popsection
180	#else
181	#define ALT_SMP(instr...)
182	#define ALT_UP(instr...) instr
183	#define ALT_UP_B(label) b label
184	#endif
185
186	/*
187	* SMP data memory barrier
188	*/
189	.macro smp_dmb mode
190	#ifdef CONFIG_SMP
191	#if __LINUX_ARM_ARCH__ >= 7
192	.ifeqs "\mode","arm"
193	ALT_SMP(dmb)
194	.else
195	ALT_SMP(W(dmb))
196	.endif
197	#elif __LINUX_ARM_ARCH__ == 6
198	ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
199	#else
200	#error Incompatible SMP platform
201	#endif
202	.ifeqs "\mode","arm"
203	ALT_UP(nop)
204	.else
205	ALT_UP(W(nop))
206	.endif
207	#endif
208	.endm
209
210	#ifdef CONFIG_THUMB2_KERNEL
211	.macro setmode, mode, reg
212	mov \reg, #\mode
213	msr cpsr_c, \reg
214	.endm
215	#else
216	.macro setmode, mode, reg
217	msr cpsr_c, #\mode
218	.endm
219	#endif
220
221	/*
222	* STRT/LDRT access macros with ARM and Thumb-2 variants
223	*/
224	#ifdef CONFIG_THUMB2_KERNEL
225
226	.macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T()
227	9999:
228	.if \inc == 1
229	\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
230	.elseif \inc == 4
231	\instr\cond\()\t\().w \reg, [\ptr, #\off]
232	.else
233	.error "Unsupported inc macro argument"
234	.endif
235
236	.pushsection __ex_table,"a"
237	.align 3
238	.long 9999b, \abort
239	.popsection
240	.endm
241
242	.macro usracc, instr, reg, ptr, inc, cond, rept, abort
243	@ explicit IT instruction needed because of the label
244	@ introduced by the USER macro
245	.ifnc \cond,al
246	.if \rept == 1
247	itt \cond
248	.elseif \rept == 2
249	ittt \cond
250	.else
251	.error "Unsupported rept macro argument"
252	.endif
253	.endif
254
255	@ Slightly optimised to avoid incrementing the pointer twice
256	usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
257	.if \rept == 2
258	usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
259	.endif
260
261	add\cond \ptr, #\rept * \inc
262	.endm
263
264	#else /* !CONFIG_THUMB2_KERNEL */
265
266	.macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=T()
267	.rept \rept
268	9999:
269	.if \inc == 1
270	\instr\cond\()b\()\t \reg, [\ptr], #\inc
271	.elseif \inc == 4
272	\instr\cond\()\t \reg, [\ptr], #\inc
273	.else
274	.error "Unsupported inc macro argument"
275	.endif
276
277	.pushsection __ex_table,"a"
278	.align 3
279	.long 9999b, \abort
280	.popsection
281	.endr
282	.endm
283
284	#endif /* CONFIG_THUMB2_KERNEL */
285
286	.macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
287	usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
288	.endm
289
290	.macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
291	usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
292	.endm