[ms2-kexec] / proc-v7.S

/*
 *  linux/arch/arm/mm/proc-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include "hwcap.h"
#include "assembler.h"
#include <asm/asm-offsets.h>
#include <asm/pgtable-hwdef.h>
#include "pgtable.h"

#include "proc-macros.S"

#define TTB_S		(1 << 1)
#define TTB_RGN_NC	(0 << 3)
#define TTB_RGN_OC_WBWA	(1 << 3)
#define TTB_RGN_OC_WT	(2 << 3)
#define TTB_RGN_OC_WB	(3 << 3)
#define TTB_NOS		(1 << 5)
#define TTB_IRGN_NC	((0 << 0) | (0 << 6))
#define TTB_IRGN_WBWA	((0 << 0) | (1 << 6))
#define TTB_IRGN_WT	((1 << 0) | (0 << 6))
#define TTB_IRGN_WB	((1 << 0) | (1 << 6))

/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
#define PMD_FLAGS_UP	PMD_SECT_WB

/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S

ENTRY(cpu_v7_proc_init)
	mov	pc, lr
ENDPROC(cpu_v7_proc_init)

ENTRY(cpu_v7_proc_fin)
	stmfd   sp!, {lr}
	bl      v7_flush_kern_cache_all
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x0006			@ .............ca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
	ldmfd   sp!, {pc}
	mov	pc, lr
ENDPROC(cpu_v7_proc_fin)

/*
 *	cpu_v7_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_v7_reset)
	mov	pc, r0
ENDPROC(cpu_v7_reset)

/*
 *	cpu_v7_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v7_do_idle)
	dsb					@ WFI may enter a low-power mode
	wfi
	mov	pc, lr
ENDPROC(cpu_v7_do_idle)

ENTRY(cpu_v7_dcache_clean_area)
#ifndef TLB_CAN_READ_FROM_L1_CACHE
	dcache_line_size r2, r3
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, r2
	subs	r1, r1, r2
	bhi	1b
	dsb
#endif
	mov	pc, lr
ENDPROC(cpu_v7_dcache_clean_area)

/*
 *	cpu_v7_switch_mm(pgd_phys, tsk)
 *
 *	Set the translation table base pointer to be pgd_phys
 *
 *	- pgd_phys - physical address of new TTB
 *
 *	It is assumed that:
 *	- we are not using split page tables
 */
ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_MMU
	mov	r2, #0
	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)
	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)
#ifdef CONFIG_ARM_ERRATA_430973
	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
#endif
#ifdef CONFIG_ARM_ERRATA_754322
	dsb
#endif
	mcr	p15, 0, r2, c13, c0, 1		@ set reserved context ID
	isb
1:	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
	isb
#ifdef CONFIG_ARM_ERRATA_754322
	dsb
#endif
	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
	isb
#endif
	mov	pc, lr
ENDPROC(cpu_v7_switch_mm)

/*
 *	cpu_v7_set_pte_ext(ptep, pte)
 *
 *	Set a level 2 translation table entry.
 *
 *	- ptep  - pointer to level 2 translation table entry
 *		  (hardware version is stored at +2048 bytes)
 *	- pte   - PTE value to store
 *	- ext	- value for extended PTE bits
 */
ENTRY(cpu_v7_set_pte_ext)
#ifdef CONFIG_MMU
	str	r1, [r0]			@ linux version

	bic	r3, r1, #0x000003f0
	bic	r3, r3, #PTE_TYPE_MASK
	orr	r3, r3, r2
	orr	r3, r3, #PTE_EXT_AP0 | 2

	tst	r1, #1 << 4
	orrne	r3, r3, #PTE_EXT_TEX(1)

	eor	r1, r1, #L_PTE_DIRTY
	tst	r1, #L_PTE_RDONLY | L_PTE_DIRTY
	orrne	r3, r3, #PTE_EXT_APX

	tst	r1, #L_PTE_USER
	orrne	r3, r3, #PTE_EXT_AP1
#ifdef CONFIG_CPU_USE_DOMAINS
	@ allow kernel read/write access to read-only user pages
	tstne	r3, #PTE_EXT_APX
	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
#endif

	tst	r1, #L_PTE_XN
	orrne	r3, r3, #PTE_EXT_XN

	tst	r1, #L_PTE_YOUNG
	tstne	r1, #L_PTE_PRESENT
	moveq	r3, #0

 ARM(	str	r3, [r0, #2048]! )
 THUMB(	add	r0, r0, #2048 )
 THUMB(	str	r3, [r0] )
	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
#endif
	mov	pc, lr
ENDPROC(cpu_v7_set_pte_ext)

cpu_v7_name:
	.ascii	"ARMv7 Processor"
	.align

	/*
	 * Memory region attributes with SCTLR.TRE=1
	 *
	 *   n = TEX[0],C,B
	 *   TR = PRRR[2n+1:2n]		- memory type
	 *   IR = NMRR[2n+1:2n]		- inner cacheable property
	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property
	 *
	 *			n	TR	IR	OR
	 *   UNCACHED		000	00
	 *   BUFFERABLE		001	10	00	00
	 *   WRITETHROUGH	010	10	10	10
	 *   WRITEBACK		011	10	11	11
	 *   reserved		110
	 *   WRITEALLOC		111	10	01	01
	 *   DEV_SHARED		100	01
	 *   DEV_NONSHARED	100	01
	 *   DEV_WC		001	10
	 *   DEV_CACHED		011	10
	 *
	 * Other attributes:
	 *
	 *   DS0 = PRRR[16] = 0		- device shareable property
	 *   DS1 = PRRR[17] = 1		- device shareable property
	 *   NS0 = PRRR[18] = 0		- normal shareable property
	 *   NS1 = PRRR[19] = 1		- normal shareable property
	 *   NOS = PRRR[24+n] = 1	- not outer shareable
	 */
.equ	PRRR,	0xff0a81a8
.equ	NMRR,	0x40e040e0

/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
.globl	cpu_v7_suspend_size
.equ	cpu_v7_suspend_size, 4 * 8
#if 0
ENTRY(cpu_v7_do_suspend)
	stmfd	sp!, {r4 - r11, lr}
	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mrc	p15, 0, r5, c13, c0, 1	@ Context ID
	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
	mrc	p15, 0, r7, c2, c0, 0	@ TTB 0
	mrc	p15, 0, r8, c2, c0, 1	@ TTB 1
	mrc	p15, 0, r9, c1, c0, 0	@ Control register
	mrc	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
	mrc	p15, 0, r11, c1, c0, 2	@ Co-processor access control
	stmia	r0, {r4 - r11}
	ldmfd	sp!, {r4 - r11, pc}
ENDPROC(cpu_v7_do_suspend)

ENTRY(cpu_v7_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
	ldmia	r0, {r4 - r11}
	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mcr	p15, 0, r5, c13, c0, 1	@ Context ID
	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
	mcr	p15, 0, r7, c2, c0, 0	@ TTB 0
	mcr	p15, 0, r8, c2, c0, 1	@ TTB 1
	mcr	p15, 0, ip, c2, c0, 2	@ TTB control register
	mcr	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
	mcr	p15, 0, r11, c1, c0, 2	@ Co-processor access control
	ldr	r4, =PRRR		@ PRRR
	ldr	r5, =NMRR		@ NMRR
	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
	isb
	mov	r0, r9			@ control register
	mov	r2, r7, lsr #14		@ get TTB0 base
	mov	r2, r2, lsl #14
	ldr	r3, cpu_resume_l1_flags
	b	cpu_resume_mmu
ENDPROC(cpu_v7_do_resume)
cpu_resume_l1_flags:
	ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
	ALT_UP(.long  PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
#else
#define cpu_v7_do_suspend	0
#define cpu_v7_do_resume	0
#endif

	__CPUINIT

/*
 *	__v7_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	We automatically detect if we have a Harvard cache, and use the
 *	Harvard cache control instructions insead of the unified cache
 *	control instructions.
 *
 *	This should be able to cover all ARMv7 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
__v7_ca9mp_setup:
#ifdef CONFIG_SMP
	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
#endif
__v7_setup:
	adr	r12, __v7_setup_stack		@ the local stack
	stmia	r12, {r0-r5, r7, r9, r11, lr}
	bl	v7_flush_dcache_all
	ldmia	r12, {r0-r5, r7, r9, r11, lr}

	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
	and	r10, r0, #0xff000000		@ ARM?
	teq	r10, #0x41000000
	bne	3f
	and	r5, r0, #0x00f00000		@ variant
	and	r6, r0, #0x0000000f		@ revision
	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
	ubfx	r0, r0, #4, #12			@ primary part number

	/* Cortex-A8 Errata */
	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
	teq	r0, r10
	bne	2f
#ifdef CONFIG_ARM_ERRATA_430973
	teq	r5, #0x00100000			@ only present in r1p*
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_458693
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_460075
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
	tsteq	r10, #1 << 22
	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
#endif
	b	3f

	/* Cortex-A9 Errata */
2:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
	teq	r0, r10
	bne	3f
#ifdef CONFIG_ARM_ERRATA_742230
	cmp	r6, #0x22			@ only present up to r2p2
	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrle	r10, r10, #1 << 4		@ set bit #4
	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_742231
	teq	r6, #0x20			@ present in r2p0
	teqne	r6, #0x21			@ present in r2p1
	teqne	r6, #0x22			@ present in r2p2
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 12		@ set bit #12
	orreq	r10, r10, #1 << 22		@ set bit #22
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_743622
	teq	r6, #0x20			@ present in r2p0
	teqne	r6, #0x21			@ present in r2p1
	teqne	r6, #0x22			@ present in r2p2
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 6		@ set bit #6
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_751472
	cmp	r6, #0x30			@ present prior to r3p0
	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrlt	r10, r10, #1 << 11		@ set bit #11
	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif

3:	mov	r10, #0
#ifdef HARVARD_CACHE
	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
#endif
	dsb
#ifdef CONFIG_MMU
	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
	ALT_SMP(orr	r4, r4, #TTB_FLAGS_SMP)
	ALT_UP(orr	r4, r4, #TTB_FLAGS_UP)
	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
	ldr	r5, =PRRR			@ PRRR
	ldr	r6, =NMRR			@ NMRR
	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
#endif
	adr	r5, v7_crval
	ldmia	r5, {r5, r6}
#ifdef CONFIG_CPU_ENDIAN_BE8
	orr	r6, r6, #1 << 25		@ big-endian page tables
#endif
#ifdef CONFIG_SWP_EMULATE
	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
#endif
   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
	mov	pc, lr				@ return to head.S:__ret
ENDPROC(__v7_setup)

	/*   AT
	 *  TFR   EV X F   I D LR    S
	 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
	 *    1    0 110       0011 1100 .111 1101 < we want
	 */
	.type	v7_crval, #object
v7_crval:
	crval	clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c

__v7_setup_stack:
	.space	4 * 11				@ 11 registers

	__INITDATA

	.type	v7_processor_functions, #object
ENTRY(v7_processor_functions)
	.word	v7_early_abort
	.word	v7_pabort
	.word	cpu_v7_proc_init
	.word	cpu_v7_proc_fin
	.word	cpu_v7_reset
	.word	cpu_v7_do_idle
	.word	cpu_v7_dcache_clean_area
	.word	cpu_v7_switch_mm
	.word	cpu_v7_set_pte_ext
	.word	0
	.word	0
	.word	0
	.size	v7_processor_functions, . - v7_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv7"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v7"
	.size	cpu_elf_name, . - cpu_elf_name
	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type   __v7_ca9mp_proc_info, #object
__v7_ca9mp_proc_info:
	.long	0x410fc090		@ Required ID value
	.long	0xff0ffff0		@ Mask for ID
	ALT_SMP(.long \
		PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS_SMP)
	ALT_UP(.long \
		PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS_UP)
	.long   PMD_TYPE_SECT | \
		PMD_SECT_XN | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	W(b)	__v7_ca9mp_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
	.long	cpu_v7_name
	.long	v7_processor_functions
	.long	v7wbi_tlb_fns
	.long	v6_user_fns
	.long	v7_cache_fns
	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info

	/*
	 * Match any ARMv7 processor core.
	 */
	.type	__v7_proc_info, #object
__v7_proc_info:
	.long	0x000f0000		@ Required ID value
	.long	0x000f0000		@ Mask for ID
	ALT_SMP(.long \
		PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS_SMP)
	ALT_UP(.long \
		PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS_UP)
	.long   PMD_TYPE_SECT | \
		PMD_SECT_XN | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	W(b)	__v7_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
	.long	cpu_v7_name
	.long	v7_processor_functions
	.long	v7wbi_tlb_fns
	.long	v6_user_fns
	.long	v7_cache_fns
	.size	__v7_proc_info, . - __v7_proc_info
Commit	Line	Data
4e93cb00 MG	1	/*
	2	* linux/arch/arm/mm/proc-v7.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
4e93cb00 MG	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This is the "shell" of the ARMv7 processor support.
	11	*/
5db3fe53	12	#include <linux/init.h>
4e93cb00	13	#include <linux/linkage.h>
0c549ba1 MG	14	#include "hwcap.h"
0c549ba1 MG	15	#include "assembler.h"
4e93cb00	16	#include <asm/asm-offsets.h>
4e93cb00	17	#include <asm/pgtable-hwdef.h>
0c549ba1	18	#include "pgtable.h"
4e93cb00 MG	19
	20	#include "proc-macros.S"
	21
4e93cb00 MG	22	#define TTB_S (1 << 1)
	23	#define TTB_RGN_NC (0 << 3)
	24	#define TTB_RGN_OC_WBWA (1 << 3)
	25	#define TTB_RGN_OC_WT (2 << 3)
	26	#define TTB_RGN_OC_WB (3 << 3)
5db3fe53 MG	27	#define TTB_NOS (1 << 5)
	28	#define TTB_IRGN_NC ((0 << 0) \| (0 << 6))
	29	#define TTB_IRGN_WBWA ((0 << 0) \| (1 << 6))
	30	#define TTB_IRGN_WT ((1 << 0) \| (0 << 6))
	31	#define TTB_IRGN_WB ((1 << 0) \| (1 << 6))
4e93cb00	32
5db3fe53	33	/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
0c549ba1 MG	34	#define TTB_FLAGS_UP TTB_IRGN_WB\|TTB_RGN_OC_WB
	35	#define PMD_FLAGS_UP PMD_SECT_WB
	36
5db3fe53	37	/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
0c549ba1 MG	38	#define TTB_FLAGS_SMP TTB_IRGN_WBWA\|TTB_S\|TTB_NOS\|TTB_RGN_OC_WBWA
0c549ba1 MG	39	#define PMD_FLAGS_SMP PMD_SECT_WBWA\|PMD_SECT_S
4e93cb00 MG	40
	41	ENTRY(cpu_v7_proc_init)
	42	mov pc, lr
	43	ENDPROC(cpu_v7_proc_init)
	44
	45	ENTRY(cpu_v7_proc_fin)
1109a23f MG	46	stmfd sp!, {lr}
1109a23f MG	47	bl v7_flush_kern_cache_all
1b28cbdb MG	48	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	49	bic r0, r0, #0x1000 @ ...i............
	50	bic r0, r0, #0x0006 @ .............ca.
	51	mcr p15, 0, r0, c1, c0, 0 @ disable caches
1109a23f MG	52	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
1109a23f MG	53	ldmfd sp!, {pc}
0c549ba1	54	mov pc, lr
4e93cb00 MG	55	ENDPROC(cpu_v7_proc_fin)
	56
	57	/*
	58	* cpu_v7_reset(loc)
	59	*
	60	* Perform a soft reset of the system. Put the CPU into the
	61	* same state as it would be if it had been reset, and branch
	62	* to what would be the reset vector.
	63	*
	64	* - loc - location to jump to for soft reset
4e93cb00 MG	65	*/
	66	.align 5
	67	ENTRY(cpu_v7_reset)
	68	mov pc, r0
	69	ENDPROC(cpu_v7_reset)
	70
	71	/*
	72	* cpu_v7_do_idle()
	73	*
	74	* Idle the processor (eg, wait for interrupt).
	75	*
	76	* IRQs are already disabled.
	77	*/
	78	ENTRY(cpu_v7_do_idle)
	79	dsb @ WFI may enter a low-power mode
	80	wfi
	81	mov pc, lr
	82	ENDPROC(cpu_v7_do_idle)
	83
	84	ENTRY(cpu_v7_dcache_clean_area)
	85	#ifndef TLB_CAN_READ_FROM_L1_CACHE
	86	dcache_line_size r2, r3
	87	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	88	add r0, r0, r2
	89	subs r1, r1, r2
	90	bhi 1b
	91	dsb
	92	#endif
	93	mov pc, lr
	94	ENDPROC(cpu_v7_dcache_clean_area)
	95
	96	/*
	97	* cpu_v7_switch_mm(pgd_phys, tsk)
	98	*
	99	* Set the translation table base pointer to be pgd_phys
	100	*
	101	* - pgd_phys - physical address of new TTB
	102	*
	103	* It is assumed that:
	104	* - we are not using split page tables
	105	*/
	106	ENTRY(cpu_v7_switch_mm)
	107	#ifdef CONFIG_MMU
	108	mov r2, #0
	109	ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
0c549ba1 MG	110	ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
0c549ba1 MG	111	ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
4e93cb00	112	#ifdef CONFIG_ARM_ERRATA_430973
5db3fe53	113	mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
0c549ba1 MG	114	#endif
	115	#ifdef CONFIG_ARM_ERRATA_754322
	116	dsb
4e93cb00 MG	117	#endif
	118	mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
	119	isb
	120	1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
	121	isb
0c549ba1 MG	122	#ifdef CONFIG_ARM_ERRATA_754322
	123	dsb
	124	#endif
4e93cb00 MG	125	mcr p15, 0, r1, c13, c0, 1 @ set context ID
	126	isb
	127	#endif
	128	mov pc, lr
	129	ENDPROC(cpu_v7_switch_mm)
	130
	131	/*
	132	* cpu_v7_set_pte_ext(ptep, pte)
	133	*
	134	* Set a level 2 translation table entry.
	135	*
	136	* - ptep - pointer to level 2 translation table entry
0c549ba1	137	* (hardware version is stored at +2048 bytes)
4e93cb00 MG	138	* - pte - PTE value to store
	139	* - ext - value for extended PTE bits
	140	*/
	141	ENTRY(cpu_v7_set_pte_ext)
	142	#ifdef CONFIG_MMU
0c549ba1	143	str r1, [r0] @ linux version
4e93cb00 MG	144
	145	bic r3, r1, #0x000003f0
	146	bic r3, r3, #PTE_TYPE_MASK
	147	orr r3, r3, r2
	148	orr r3, r3, #PTE_EXT_AP0 \| 2
	149
	150	tst r1, #1 << 4
	151	orrne r3, r3, #PTE_EXT_TEX(1)
	152
0c549ba1 MG	153	eor r1, r1, #L_PTE_DIRTY
	154	tst r1, #L_PTE_RDONLY \| L_PTE_DIRTY
	155	orrne r3, r3, #PTE_EXT_APX
4e93cb00 MG	156
	157	tst r1, #L_PTE_USER
	158	orrne r3, r3, #PTE_EXT_AP1
0c549ba1 MG	159	#ifdef CONFIG_CPU_USE_DOMAINS
0c549ba1 MG	160	@ allow kernel read/write access to read-only user pages
4e93cb00 MG	161	tstne r3, #PTE_EXT_APX
4e93cb00 MG	162	bicne r3, r3, #PTE_EXT_APX \| PTE_EXT_AP0
0c549ba1	163	#endif
4e93cb00	164
0c549ba1 MG	165	tst r1, #L_PTE_XN
0c549ba1 MG	166	orrne r3, r3, #PTE_EXT_XN
4e93cb00 MG	167
	168	tst r1, #L_PTE_YOUNG
	169	tstne r1, #L_PTE_PRESENT
	170	moveq r3, #0
	171
0c549ba1 MG	172	ARM( str r3, [r0, #2048]! )
	173	THUMB( add r0, r0, #2048 )
	174	THUMB( str r3, [r0] )
4e93cb00 MG	175	mcr p15, 0, r0, c7, c10, 1 @ flush_pte
	176	#endif
	177	mov pc, lr
	178	ENDPROC(cpu_v7_set_pte_ext)
	179
	180	cpu_v7_name:
	181	.ascii "ARMv7 Processor"
	182	.align
	183
0c549ba1 MG	184	/*
	185	* Memory region attributes with SCTLR.TRE=1
	186	*
	187	* n = TEX[0],C,B
	188	* TR = PRRR[2n+1:2n] - memory type
	189	* IR = NMRR[2n+1:2n] - inner cacheable property
	190	* OR = NMRR[2n+17:2n+16] - outer cacheable property
	191	*
	192	* n TR IR OR
	193	* UNCACHED 000 00
	194	* BUFFERABLE 001 10 00 00
	195	* WRITETHROUGH 010 10 10 10
	196	* WRITEBACK 011 10 11 11
	197	* reserved 110
	198	* WRITEALLOC 111 10 01 01
	199	* DEV_SHARED 100 01
	200	* DEV_NONSHARED 100 01
	201	* DEV_WC 001 10
	202	* DEV_CACHED 011 10
	203	*
	204	* Other attributes:
	205	*
	206	* DS0 = PRRR[16] = 0 - device shareable property
	207	* DS1 = PRRR[17] = 1 - device shareable property
	208	* NS0 = PRRR[18] = 0 - normal shareable property
	209	* NS1 = PRRR[19] = 1 - normal shareable property
	210	* NOS = PRRR[24+n] = 1 - not outer shareable
	211	*/
	212	.equ PRRR, 0xff0a81a8
	213	.equ NMRR, 0x40e040e0
	214
	215	/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
	216	.globl cpu_v7_suspend_size
	217	.equ cpu_v7_suspend_size, 4 * 8
	218	#if 0
	219	ENTRY(cpu_v7_do_suspend)
	220	stmfd sp!, {r4 - r11, lr}
	221	mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
	222	mrc p15, 0, r5, c13, c0, 1 @ Context ID
	223	mrc p15, 0, r6, c3, c0, 0 @ Domain ID
	224	mrc p15, 0, r7, c2, c0, 0 @ TTB 0
	225	mrc p15, 0, r8, c2, c0, 1 @ TTB 1
	226	mrc p15, 0, r9, c1, c0, 0 @ Control register
	227	mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
	228	mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control
	229	stmia r0, {r4 - r11}
	230	ldmfd sp!, {r4 - r11, pc}
	231	ENDPROC(cpu_v7_do_suspend)
	232
	233	ENTRY(cpu_v7_do_resume)
	234	mov ip, #0
	235	mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
	236	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	237	ldmia r0, {r4 - r11}
	238	mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
	239	mcr p15, 0, r5, c13, c0, 1 @ Context ID
	240	mcr p15, 0, r6, c3, c0, 0 @ Domain ID
	241	mcr p15, 0, r7, c2, c0, 0 @ TTB 0
	242	mcr p15, 0, r8, c2, c0, 1 @ TTB 1
	243	mcr p15, 0, ip, c2, c0, 2 @ TTB control register
	244	mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
	245	mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control
	246	ldr r4, =PRRR @ PRRR
	247	ldr r5, =NMRR @ NMRR
248	mcr p15, 0, r4, c10, c2, 0 @ write PRRR
249	mcr p15, 0, r5, c10, c2, 1 @ write NMRR
250	isb
251	mov r0, r9 @ control register
252	mov r2, r7, lsr #14 @ get TTB0 base
253	mov r2, r2, lsl #14
254	ldr r3, cpu_resume_l1_flags
255	b cpu_resume_mmu
256	ENDPROC(cpu_v7_do_resume)
257	cpu_resume_l1_flags:
258	ALT_SMP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_FLAGS_SMP)
259	ALT_UP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_FLAGS_UP)
260	#else
261	#define cpu_v7_do_suspend 0
262	#define cpu_v7_do_resume 0
263	#endif
264
265	__CPUINIT
4e93cb00 MG	266
	267	/*
	268	* __v7_setup
	269	*
	270	* Initialise TLB, Caches, and MMU state ready to switch the MMU
	271	* on. Return in r0 the new CP15 C1 control register setting.
	272	*
	273	* We automatically detect if we have a Harvard cache, and use the
	274	* Harvard cache control instructions insead of the unified cache
	275	* control instructions.
	276	*
	277	* This should be able to cover all ARMv7 cores.
	278	*
	279	* It is assumed that:
	280	* - cache type register is implemented
	281	*/
0c549ba1	282	__v7_ca9mp_setup:
4e93cb00	283	#ifdef CONFIG_SMP
0c549ba1 MG	284	ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
0c549ba1 MG	285	ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
5db3fe53 MG	286	tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
	287	orreq r0, r0, #(1 << 6) \| (1 << 0) @ Enable SMP/nAMP mode and
	288	mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
4e93cb00	289	#endif
0c549ba1	290	__v7_setup:
4e93cb00 MG	291	adr r12, __v7_setup_stack @ the local stack
	292	stmia r12, {r0-r5, r7, r9, r11, lr}
	293	bl v7_flush_dcache_all
	294	ldmia r12, {r0-r5, r7, r9, r11, lr}
5db3fe53 MG	295
	296	mrc p15, 0, r0, c0, c0, 0 @ read main ID register
	297	and r10, r0, #0xff000000 @ ARM?
	298	teq r10, #0x41000000
0c549ba1	299	bne 3f
5db3fe53 MG	300	and r5, r0, #0x00f00000 @ variant
5db3fe53 MG	301	and r6, r0, #0x0000000f @ revision
0c549ba1 MG	302	orr r6, r6, r5, lsr #20-4 @ combine variant and revision
0c549ba1 MG	303	ubfx r0, r0, #4, #12 @ primary part number
5db3fe53	304
0c549ba1 MG	305	/* Cortex-A8 Errata */
	306	ldr r10, =0x00000c08 @ Cortex-A8 primary part number
	307	teq r0, r10
	308	bne 2f
4e93cb00	309	#ifdef CONFIG_ARM_ERRATA_430973
5db3fe53 MG	310	teq r5, #0x00100000 @ only present in r1p*
	311	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	312	orreq r10, r10, #(1 << 6) @ set IBE to 1
	313	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
	314	#endif
	315	#ifdef CONFIG_ARM_ERRATA_458693
0c549ba1	316	teq r6, #0x20 @ only present in r2p0
5db3fe53 MG	317	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	318	orreq r10, r10, #(1 << 5) @ set L1NEON to 1
	319	orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
	320	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
4e93cb00	321	#endif
5db3fe53	322	#ifdef CONFIG_ARM_ERRATA_460075
0c549ba1	323	teq r6, #0x20 @ only present in r2p0
5db3fe53 MG	324	mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
	325	tsteq r10, #1 << 22
	326	orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
	327	mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
	328	#endif
0c549ba1 MG	329	b 3f
	330
	331	/* Cortex-A9 Errata */
	332	2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
	333	teq r0, r10
	334	bne 3f
	335	#ifdef CONFIG_ARM_ERRATA_742230
	336	cmp r6, #0x22 @ only present up to r2p2
	337	mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
	338	orrle r10, r10, #1 << 4 @ set bit #4
	339	mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
	340	#endif
	341	#ifdef CONFIG_ARM_ERRATA_742231
	342	teq r6, #0x20 @ present in r2p0
	343	teqne r6, #0x21 @ present in r2p1
	344	teqne r6, #0x22 @ present in r2p2
	345	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	346	orreq r10, r10, #1 << 12 @ set bit #12
	347	orreq r10, r10, #1 << 22 @ set bit #22
	348	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	349	#endif
	350	#ifdef CONFIG_ARM_ERRATA_743622
	351	teq r6, #0x20 @ present in r2p0
	352	teqne r6, #0x21 @ present in r2p1
	353	teqne r6, #0x22 @ present in r2p2
	354	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	355	orreq r10, r10, #1 << 6 @ set bit #6
	356	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	357	#endif
	358	#ifdef CONFIG_ARM_ERRATA_751472
	359	cmp r6, #0x30 @ present prior to r3p0
	360	mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
	361	orrlt r10, r10, #1 << 11 @ set bit #11
	362	mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
	363	#endif
5db3fe53	364
0c549ba1	365	3: mov r10, #0
4e93cb00 MG	366	#ifdef HARVARD_CACHE
	367	mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
	368	#endif
	369	dsb
	370	#ifdef CONFIG_MMU
	371	mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
	372	mcr p15, 0, r10, c2, c0, 2 @ TTB control register
0c549ba1 MG	373	ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
0c549ba1 MG	374	ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
4e93cb00	375	mcr p15, 0, r4, c2, c0, 1 @ load TTB1
0c549ba1 MG	376	ldr r5, =PRRR @ PRRR
0c549ba1 MG	377	ldr r6, =NMRR @ NMRR
4e93cb00 MG	378	mcr p15, 0, r5, c10, c2, 0 @ write PRRR
4e93cb00 MG	379	mcr p15, 0, r6, c10, c2, 1 @ write NMRR
5db3fe53	380	#endif
4e93cb00 MG	381	adr r5, v7_crval
4e93cb00 MG	382	ldmia r5, {r5, r6}
5db3fe53 MG	383	#ifdef CONFIG_CPU_ENDIAN_BE8
5db3fe53 MG	384	orr r6, r6, #1 << 25 @ big-endian page tables
0c549ba1 MG	385	#endif
	386	#ifdef CONFIG_SWP_EMULATE
	387	orr r5, r5, #(1 << 10) @ set SW bit in "clear"
	388	bic r6, r6, #(1 << 10) @ clear it in "mmuset"
5db3fe53	389	#endif
4e93cb00 MG	390	mrc p15, 0, r0, c1, c0, 0 @ read control register
	391	bic r0, r0, r5 @ clear bits them
	392	orr r0, r0, r6 @ set them
5db3fe53	393	THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
4e93cb00 MG	394	mov pc, lr @ return to head.S:__ret
	395	ENDPROC(__v7_setup)
	396
	397	/* AT
5db3fe53 MG	398	* TFR EV X F I D LR S
5db3fe53 MG	399	* .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
4e93cb00	400	* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
5db3fe53	401	* 1 0 110 0011 1100 .111 1101 < we want
4e93cb00 MG	402	*/
	403	.type v7_crval, #object
	404	v7_crval:
5db3fe53	405	crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
4e93cb00 MG	406
	407	__v7_setup_stack:
	408	.space 4 * 11 @ 11 registers
	409
0c549ba1 MG	410	__INITDATA
0c549ba1 MG	411
4e93cb00 MG	412	.type v7_processor_functions, #object
	413	ENTRY(v7_processor_functions)
	414	.word v7_early_abort
5db3fe53	415	.word v7_pabort
4e93cb00 MG	416	.word cpu_v7_proc_init
	417	.word cpu_v7_proc_fin
	418	.word cpu_v7_reset
	419	.word cpu_v7_do_idle
	420	.word cpu_v7_dcache_clean_area
	421	.word cpu_v7_switch_mm
	422	.word cpu_v7_set_pte_ext
0c549ba1 MG	423	.word 0
	424	.word 0
	425	.word 0
4e93cb00 MG	426	.size v7_processor_functions, . - v7_processor_functions
4e93cb00 MG	427
0c549ba1 MG	428	.section ".rodata"
0c549ba1 MG	429
4e93cb00 MG	430	.type cpu_arch_name, #object
	431	cpu_arch_name:
	432	.asciz "armv7"
	433	.size cpu_arch_name, . - cpu_arch_name
	434
	435	.type cpu_elf_name, #object
	436	cpu_elf_name:
	437	.asciz "v7"
	438	.size cpu_elf_name, . - cpu_elf_name
	439	.align
	440
	441	.section ".proc.info.init", #alloc, #execinstr
	442
0c549ba1 MG	443	.type __v7_ca9mp_proc_info, #object
	444	__v7_ca9mp_proc_info:
	445	.long 0x410fc090 @ Required ID value
	446	.long 0xff0ffff0 @ Mask for ID
	447	ALT_SMP(.long \
	448	PMD_TYPE_SECT \| \
	449	PMD_SECT_AP_WRITE \| \
	450	PMD_SECT_AP_READ \| \
	451	PMD_FLAGS_SMP)
	452	ALT_UP(.long \
	453	PMD_TYPE_SECT \| \
	454	PMD_SECT_AP_WRITE \| \
	455	PMD_SECT_AP_READ \| \
	456	PMD_FLAGS_UP)
	457	.long PMD_TYPE_SECT \| \
	458	PMD_SECT_XN \| \
	459	PMD_SECT_AP_WRITE \| \
	460	PMD_SECT_AP_READ
	461	W(b) __v7_ca9mp_setup
	462	.long cpu_arch_name
	463	.long cpu_elf_name
	464	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_TLS
	465	.long cpu_v7_name
	466	.long v7_processor_functions
	467	.long v7wbi_tlb_fns
	468	.long v6_user_fns
	469	.long v7_cache_fns
	470	.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
	471
4e93cb00 MG	472	/*
	473	* Match any ARMv7 processor core.
	474	*/
	475	.type __v7_proc_info, #object
	476	__v7_proc_info:
	477	.long 0x000f0000 @ Required ID value
	478	.long 0x000f0000 @ Mask for ID
0c549ba1 MG	479	ALT_SMP(.long \
	480	PMD_TYPE_SECT \| \
	481	PMD_SECT_AP_WRITE \| \
	482	PMD_SECT_AP_READ \| \
	483	PMD_FLAGS_SMP)
	484	ALT_UP(.long \
	485	PMD_TYPE_SECT \| \
4e93cb00	486	PMD_SECT_AP_WRITE \| \
5db3fe53	487	PMD_SECT_AP_READ \| \
0c549ba1	488	PMD_FLAGS_UP)
4e93cb00 MG	489	.long PMD_TYPE_SECT \| \
	490	PMD_SECT_XN \| \
	491	PMD_SECT_AP_WRITE \| \
	492	PMD_SECT_AP_READ
0c549ba1	493	W(b) __v7_setup
4e93cb00 MG	494	.long cpu_arch_name
4e93cb00 MG	495	.long cpu_elf_name
0c549ba1	496	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_TLS
4e93cb00 MG	497	.long cpu_v7_name
	498	.long v7_processor_functions
	499	.long v7wbi_tlb_fns
	500	.long v6_user_fns
	501	.long v7_cache_fns
	502	.size __v7_proc_info, . - __v7_proc_info