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8eb83dc7 MG |
1 | /* |
2 | * arch/arm/mach-omap2/serial.c | |
3 | * | |
4 | * OMAP2 serial support. | |
5 | * | |
6 | * Copyright (C) 2005-2008 Nokia Corporation | |
7 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
8 | * | |
9 | * Major rework for PM support by Kevin Hilman | |
10 | * | |
11 | * Based off of arch/arm/mach-omap/omap1/serial.c | |
12 | * | |
13 | * This file is subject to the terms and conditions of the GNU General Public | |
14 | * License. See the file "COPYING" in the main directory of this archive | |
15 | * for more details. | |
16 | */ | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/serial_reg.h> | |
20 | #include <linux/clk.h> | |
21 | #ifdef CONFIG_SERIAL_OMAP | |
22 | #include <linux/platform_device.h> | |
23 | #endif | |
24 | #include <linux/io.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/debugfs.h> | |
27 | ||
28 | #include <plat/common.h> | |
29 | #include <plat/board.h> | |
30 | #include <plat/clock.h> | |
31 | #include <plat/control.h> | |
32 | #include <mach/gpio.h> | |
33 | #include <plat/omap-serial.h> | |
34 | ||
35 | #include <asm/mach/serial_omap.h> | |
36 | ||
37 | #include "prm.h" | |
38 | #include "pm.h" | |
39 | #include "prm-regbits-34xx.h" | |
40 | ||
41 | #define OMAP_CTRL_REGADDR(reg) (OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE) + (reg)) | |
42 | ||
a18588b1 MG |
43 | static int (*my_pwrdm_clkdm_state_switch)(struct clockdomain *) = (int (*)(struct clockdomain *))0xc0041370; |
44 | static int (*add_preferred_console)(char *, int, char*) = (int (*)(char*, int, char*))0xc0069208; | |
45 | ||
46 | ||
8eb83dc7 MG |
47 | void omap_ctrl_writew(u16 val, u16 offset) |
48 | { | |
49 | __raw_writew(val, OMAP_CTRL_REGADDR(offset)); | |
50 | } | |
51 | ||
52 | u16 omap_ctrl_readw(u16 offset) | |
53 | { | |
54 | return __raw_readw(OMAP_CTRL_REGADDR(offset)); | |
55 | } | |
56 | ||
57 | #define DEFAULT_TIMEOUT HZ | |
58 | ||
59 | struct omap_uart_state { | |
60 | int num; | |
61 | int can_sleep; | |
62 | struct timer_list timer; | |
63 | u32 timeout; | |
64 | ||
65 | void __iomem *wk_st; | |
66 | void __iomem *wk_en; | |
67 | u32 wk_mask; | |
68 | u32 padconf; | |
69 | ||
70 | u32 rts_padconf; | |
71 | int rts_override; | |
72 | u16 rts_padvalue; | |
73 | ||
74 | struct clk *ick; | |
75 | struct clk *fck; | |
76 | int clocked; | |
77 | ||
78 | struct plat_serialomap_port *p; | |
79 | struct list_head node; | |
80 | ||
81 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) | |
82 | int context_valid; | |
83 | ||
84 | /* Registers to be saved/restored for OFF-mode */ | |
85 | u16 dll; | |
86 | u16 dlh; | |
87 | u16 ier; | |
88 | u16 sysc; | |
89 | u16 scr; | |
90 | u16 wer; | |
91 | #endif | |
92 | }; | |
93 | ||
94 | static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS]; | |
95 | static LIST_HEAD(uart_list); | |
96 | static unsigned int fifo_idleblks = 0; | |
97 | static int uart0_padconf = 0x180; | |
98 | ||
99 | static struct plat_serialomap_port serial_platform_data[] = { | |
100 | { | |
101 | .membase = OMAP2_L4_IO_ADDRESS(OMAP_UART1_BASE), | |
102 | .irq = 72, | |
103 | .regshift = 2, | |
104 | #ifdef CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL | |
105 | .ctsrts = UART_EFR_CTS | UART_EFR_RTS, | |
106 | #endif | |
107 | .flags = UPF_BOOT_AUTOCONF, | |
108 | }, | |
109 | { | |
110 | .membase = OMAP2_L4_IO_ADDRESS(OMAP_UART2_BASE), | |
111 | .irq = 73, | |
112 | .regshift = 2, | |
113 | #ifdef CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL | |
114 | .ctsrts = UART_EFR_CTS | UART_EFR_RTS, | |
115 | #endif | |
116 | .flags = UPF_BOOT_AUTOCONF, | |
117 | }, | |
118 | { | |
119 | .membase = OMAP2_L4_IO_ADDRESS(OMAP_UART3_BASE), | |
120 | .irq = 74, | |
121 | .regshift = 2, | |
122 | #ifdef CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL | |
123 | .ctsrts = UART_EFR_RTS, | |
124 | #endif | |
125 | .flags = UPF_BOOT_AUTOCONF, | |
126 | }, | |
127 | }; | |
128 | ||
129 | #if 0 | |
130 | static struct resource omap2_uart1_resources[] = { | |
131 | { | |
132 | .start = OMAP_UART1_BASE, | |
133 | .end = OMAP_UART1_BASE + 0x3ff, | |
134 | .flags = IORESOURCE_MEM, | |
135 | }, { | |
136 | .start = 72, | |
137 | .flags = IORESOURCE_IRQ, | |
138 | } | |
139 | }; | |
140 | ||
141 | static struct resource omap2_uart2_resources[] = { | |
142 | { | |
143 | .start = OMAP_UART2_BASE, | |
144 | .end = OMAP_UART2_BASE + 0x3ff, | |
145 | .flags = IORESOURCE_MEM, | |
146 | }, { | |
147 | .start = 73, | |
148 | .flags = IORESOURCE_IRQ, | |
149 | } | |
150 | }; | |
151 | #endif | |
152 | ||
153 | static struct resource omap2_uart3_resources[] = { | |
154 | { | |
155 | .start = OMAP_UART3_BASE, | |
156 | .end = OMAP_UART3_BASE + 0x3ff, | |
157 | .flags = IORESOURCE_MEM, | |
158 | }, { | |
159 | .start = 74, | |
160 | .flags = IORESOURCE_IRQ, | |
161 | } | |
162 | }; | |
163 | ||
164 | #ifdef CONFIG_MACH_OMAP_ZOOM2 | |
165 | static struct resource omap2_quaduart_resources[] = { | |
166 | { | |
167 | .start = 0x10000000, | |
168 | .end = 0x10000000 + (0x16 << 1), | |
169 | .flags = IORESOURCE_MEM, | |
170 | }, { | |
171 | .start = OMAP_GPIO_IRQ(102), | |
172 | .flags = IORESOURCE_IRQ, | |
173 | } | |
174 | }; | |
175 | #endif | |
176 | ||
177 | #if 0 | |
178 | /* OMAP UART platform structure */ | |
179 | static struct platform_device uart1_device = { | |
180 | .name = "omap-uart", | |
181 | .id = 1, | |
182 | .num_resources = ARRAY_SIZE(omap2_uart1_resources), | |
183 | .resource = omap2_uart1_resources, | |
184 | .dev.platform_data = &serial_platform_data[0], | |
185 | }; | |
186 | static struct platform_device uart2_device = { | |
187 | .name = "omap-uart", | |
188 | .id = 2, | |
189 | .num_resources = ARRAY_SIZE(omap2_uart2_resources), | |
190 | .resource = omap2_uart2_resources, | |
191 | .dev.platform_data = &serial_platform_data[1], | |
192 | }; | |
193 | #endif | |
194 | static struct platform_device uart3_device = { | |
e14c6eae MG |
195 | .name = "omap-hs-uart", |
196 | .id = 3, | |
8eb83dc7 MG |
197 | .num_resources = ARRAY_SIZE(omap2_uart3_resources), |
198 | .resource = omap2_uart3_resources, | |
199 | .dev.platform_data = &serial_platform_data[2], | |
200 | }; | |
201 | ||
202 | static struct platform_device *uart_devices[] = { | |
203 | &uart3_device, | |
204 | }; | |
205 | ||
206 | static inline unsigned int serial_read_reg(struct plat_serialomap_port *up, | |
207 | int offset) | |
208 | { | |
209 | offset <<= up->regshift; | |
210 | return (unsigned int)__raw_readb(up->membase + offset); | |
211 | } | |
212 | ||
213 | static inline void serial_write_reg(struct plat_serialomap_port *p, int offset, | |
214 | int value) | |
215 | { | |
216 | offset <<= p->regshift; | |
217 | __raw_writeb(value, p->membase + offset); | |
218 | } | |
219 | ||
220 | /* | |
221 | * Internal UARTs need to be initialized for the 8250 autoconfig to work | |
222 | * properly. Note that the TX watermark initialization may not be needed | |
223 | * once the 8250.c watermark handling code is merged. | |
224 | */ | |
225 | static inline void omap_uart_reset(struct omap_uart_state *uart) | |
226 | { | |
227 | struct plat_serialomap_port *p = uart->p; | |
228 | ||
229 | serial_write_reg(p, UART_OMAP_MDR1, 0x07); | |
230 | serial_write_reg(p, UART_OMAP_SCR, 0x08); | |
231 | serial_write_reg(p, UART_OMAP_MDR1, 0x00); | |
232 | serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); | |
233 | } | |
234 | ||
235 | static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) | |
236 | { | |
237 | if (uart->clocked) | |
238 | return; | |
239 | ||
240 | clk_enable(uart->ick); | |
241 | clk_enable(uart->fck); | |
a18588b1 MG |
242 | |
243 | if (uart->ick->clkdm != NULL) | |
244 | my_pwrdm_clkdm_state_switch(uart->ick->clkdm); | |
245 | ||
246 | if (uart->fck->clkdm != NULL) | |
247 | my_pwrdm_clkdm_state_switch(uart->fck->clkdm); | |
248 | ||
8eb83dc7 MG |
249 | uart->clocked = 1; |
250 | } | |
251 | ||
252 | #ifdef CONFIG_PM | |
253 | #ifdef CONFIG_ARCH_OMAP3 | |
254 | ||
255 | static void omap_uart_save_context(struct omap_uart_state *uart) | |
256 | { | |
257 | u16 lcr = 0; | |
258 | struct plat_serialomap_port *p = uart->p; | |
259 | ||
260 | if (!enable_off_mode) | |
261 | return; | |
262 | ||
263 | /* FIXME | |
264 | * For omap3430 CORE/PERR OFF isn't temporarily supported, | |
265 | * so no need to save&restore the context of serial. | |
266 | */ | |
267 | if (cpu_is_omap34xx()) | |
268 | return; | |
269 | ||
270 | lcr = serial_read_reg(p, UART_LCR); | |
271 | serial_write_reg(p, UART_LCR, 0xBF); | |
272 | uart->dll = serial_read_reg(p, UART_DLL); | |
273 | uart->dlh = serial_read_reg(p, UART_DLM); | |
274 | serial_write_reg(p, UART_LCR, lcr); | |
275 | uart->ier = serial_read_reg(p, UART_IER); | |
276 | uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); | |
277 | uart->scr = serial_read_reg(p, UART_OMAP_SCR); | |
278 | uart->wer = serial_read_reg(p, UART_OMAP_WER); | |
279 | ||
280 | uart->context_valid = 1; | |
281 | } | |
282 | ||
283 | static void omap_uart_restore_context(struct omap_uart_state *uart) | |
284 | { | |
285 | u16 efr = 0; | |
286 | struct plat_serialomap_port *p = uart->p; | |
287 | ||
288 | if (!enable_off_mode) | |
289 | return; | |
290 | ||
291 | if (!uart->context_valid) | |
292 | return; | |
293 | ||
294 | /* FIXME | |
295 | * For omap3430 CORE/PERR OFF isn't temporarily supported, | |
296 | * so no need to save&restore the context of serial. | |
297 | */ | |
298 | if (cpu_is_omap34xx()) | |
299 | return; | |
300 | ||
301 | uart->context_valid = 0; | |
302 | ||
303 | serial_write_reg(p, UART_OMAP_MDR1, 0x7); | |
304 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ | |
305 | efr = serial_read_reg(p, UART_EFR); | |
306 | serial_write_reg(p, UART_EFR, UART_EFR_ECB); | |
307 | serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ | |
308 | serial_write_reg(p, UART_IER, 0x0); | |
309 | #ifdef CONFIG_SERIAL_OMAP | |
310 | serial_write_reg(p, UART_FCR, fcr[uart->num]); | |
311 | #else | |
312 | serial_write_reg(p, UART_FCR, 0xA1); | |
313 | #endif | |
314 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ | |
315 | serial_write_reg(p, UART_DLL, uart->dll); | |
316 | serial_write_reg(p, UART_DLM, uart->dlh); | |
317 | serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ | |
318 | serial_write_reg(p, UART_IER, uart->ier); | |
319 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ | |
320 | serial_write_reg(p, UART_EFR, efr); | |
321 | serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); | |
322 | serial_write_reg(p, UART_OMAP_SCR, uart->scr); | |
323 | serial_write_reg(p, UART_OMAP_WER, uart->wer); | |
324 | serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); | |
325 | serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ | |
326 | } | |
327 | #else | |
328 | static inline void omap_uart_save_context(struct omap_uart_state *uart) {} | |
329 | static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} | |
330 | #endif /* CONFIG_ARCH_OMAP3 */ | |
331 | ||
332 | static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, | |
333 | int enable) | |
334 | { | |
335 | struct plat_serialomap_port *p = uart->p; | |
336 | u16 sysc; | |
337 | ||
338 | sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7; | |
339 | if (enable) | |
340 | sysc |= 0x2 << 3; | |
341 | else | |
342 | sysc |= 0x1 << 3; | |
343 | ||
344 | serial_write_reg(p, UART_OMAP_SYSC, sysc); | |
345 | } | |
346 | ||
347 | static inline void omap_uart_disable_rtspullup(struct omap_uart_state *uart) | |
348 | { | |
349 | if (!uart->rts_padconf || !uart->rts_override) | |
350 | return; | |
351 | omap_ctrl_writew(uart->rts_padvalue, uart->rts_padconf); | |
352 | uart->rts_override = 0; | |
353 | } | |
354 | ||
355 | static inline void omap_uart_enable_rtspullup(struct omap_uart_state *uart) | |
356 | { | |
357 | if (!uart->rts_padconf || uart->rts_override) | |
358 | return; | |
359 | ||
360 | uart->rts_padvalue = omap_ctrl_readw(uart->rts_padconf); | |
361 | omap_ctrl_writew(0x18 | 0x7, uart->rts_padconf); | |
362 | uart->rts_override = 1; | |
363 | } | |
364 | ||
365 | static inline void omap_uart_restore(struct omap_uart_state *uart) | |
366 | { | |
367 | omap_uart_enable_clocks(uart); | |
368 | omap_uart_restore_context(uart); | |
369 | } | |
370 | ||
371 | static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) | |
372 | { | |
373 | if (!uart->clocked) | |
374 | return; | |
375 | omap_uart_save_context(uart); | |
376 | uart->clocked = 0; | |
377 | clk_disable(uart->ick); | |
378 | clk_disable(uart->fck); | |
379 | } | |
380 | ||
381 | static void _omap_uart_block_sleep(struct omap_uart_state *uart) | |
382 | { | |
383 | omap_uart_restore(uart); | |
384 | ||
385 | omap_uart_smart_idle_enable(uart, 0); | |
386 | uart->can_sleep = 0; | |
387 | if (uart->timeout) | |
388 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
389 | else | |
390 | del_timer(&uart->timer); | |
391 | } | |
392 | ||
393 | #if 0 | |
394 | static void omap_uart_block_sleep(int num) | |
395 | { | |
396 | struct omap_uart_state *uart; | |
397 | ||
398 | list_for_each_entry(uart, &uart_list, node) { | |
399 | if (num == uart->num) | |
400 | _omap_uart_block_sleep(uart); | |
401 | return; | |
402 | } | |
403 | } | |
404 | EXPORT_SYMBOL(omap_uart_block_sleep); | |
405 | #endif | |
406 | ||
407 | static void omap_uart_allow_sleep(struct omap_uart_state *uart) | |
408 | { | |
409 | if (!uart->clocked) | |
410 | return; | |
411 | ||
412 | omap_uart_smart_idle_enable(uart, 1); | |
413 | uart->can_sleep = 1; | |
414 | del_timer(&uart->timer); | |
415 | } | |
416 | ||
417 | static void omap_uart_idle_timer(unsigned long data) | |
418 | { | |
419 | struct omap_uart_state *uart = (struct omap_uart_state *)data; | |
420 | ||
421 | omap_uart_allow_sleep(uart); | |
422 | } | |
423 | ||
424 | void omap_uart_prepare_idle(int num) | |
425 | { | |
426 | struct omap_uart_state *uart; | |
427 | ||
428 | list_for_each_entry(uart, &uart_list, node) { | |
429 | if (num == uart->num && uart->can_sleep) { | |
430 | ||
431 | omap_uart_enable_rtspullup(uart); | |
432 | /* | |
433 | * There seems to be a window here where | |
434 | * data could still be on the way to the | |
435 | * fifo. This delay is ~1 byte time @ 115.2k | |
436 | */ | |
437 | if (uart->num == 0) | |
438 | udelay(80); | |
439 | ||
440 | #ifdef CONFIG_SERIAL_OMAP | |
441 | if (are_driveromap_uarts_active(num)) { | |
442 | fifo_idleblks++; | |
443 | _omap_uart_block_sleep(uart); | |
444 | omap_uart_disable_rtspullup(uart); | |
445 | return; | |
446 | } | |
447 | #endif | |
448 | omap_uart_disable_clocks(uart); | |
449 | return; | |
450 | } | |
451 | } | |
452 | } | |
453 | ||
454 | void omap_uart_resume_idle(int num) | |
455 | { | |
456 | struct omap_uart_state *uart; | |
457 | ||
458 | list_for_each_entry(uart, &uart_list, node) { | |
459 | if (num == uart->num) { | |
460 | omap_uart_restore(uart); | |
461 | omap_uart_disable_rtspullup(uart); | |
462 | ||
463 | /* Check for IO pad wakeup */ | |
464 | if (cpu_is_omap34xx() && uart->padconf) { | |
465 | u16 p = omap_ctrl_readw(uart->padconf); | |
466 | ||
467 | if (p & OMAP3_PADCONF_WAKEUPEVENT0) | |
468 | _omap_uart_block_sleep(uart); | |
469 | } | |
470 | ||
471 | /* Check for normal UART wakeup */ | |
472 | if (__raw_readl(uart->wk_st) & uart->wk_mask) { | |
473 | _omap_uart_block_sleep(uart); | |
474 | } | |
475 | ||
476 | return; | |
477 | } | |
478 | } | |
479 | } | |
480 | ||
481 | void omap_uart_prepare_suspend(void) | |
482 | { | |
483 | struct omap_uart_state *uart; | |
484 | ||
485 | list_for_each_entry(uart, &uart_list, node) { | |
486 | omap_uart_allow_sleep(uart); | |
487 | } | |
488 | } | |
489 | ||
490 | int omap_uart_can_sleep(void) | |
491 | { | |
492 | struct omap_uart_state *uart; | |
493 | int can_sleep = 1; | |
494 | ||
495 | list_for_each_entry(uart, &uart_list, node) { | |
496 | if (!uart->clocked) | |
497 | continue; | |
498 | ||
499 | if (!uart->can_sleep) { | |
500 | can_sleep = 0; | |
501 | continue; | |
502 | } | |
503 | ||
504 | #ifdef CONFIG_SERIAL_OMAP | |
505 | if (are_driveromap_uarts_active(uart->num)) { | |
506 | can_sleep = 0; | |
507 | continue; | |
508 | } | |
509 | #endif | |
510 | ||
511 | /* This UART can now safely sleep. */ | |
512 | omap_uart_allow_sleep(uart); | |
513 | } | |
514 | ||
515 | return can_sleep; | |
516 | } | |
517 | ||
518 | /** | |
519 | * omap_uart_interrupt() | |
520 | * | |
521 | * This handler is used only to detect that *any* UART interrupt has | |
522 | * occurred. It does _nothing_ to handle the interrupt. Rather, | |
523 | * any UART interrupt will trigger the inactivity timer so the | |
524 | * UART will not idle or sleep for its timeout period. | |
525 | * | |
526 | **/ | |
527 | static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) | |
528 | { | |
529 | struct omap_uart_state *uart = dev_id; | |
530 | ||
531 | _omap_uart_block_sleep(uart); | |
532 | ||
533 | return IRQ_NONE; | |
534 | } | |
535 | ||
536 | static u32 sleep_timeout = DEFAULT_TIMEOUT; | |
537 | ||
538 | static void omap_uart_rtspad_init(struct omap_uart_state *uart) | |
539 | { | |
540 | if (!cpu_is_omap34xx()) | |
541 | return; | |
542 | switch(uart->num) { | |
543 | case 0: | |
544 | uart->rts_padconf = 0x17e; | |
545 | break; | |
546 | case 1: | |
547 | uart->rts_padconf = 0x176; | |
548 | break; | |
549 | case 2: | |
550 | /* uart->rts_padconf = 0x19c; */ | |
551 | break; | |
552 | default: | |
553 | uart->rts_padconf = 0; | |
554 | break; | |
555 | } | |
556 | } | |
557 | ||
558 | static void omap_uart_idle_init(struct omap_uart_state *uart) | |
559 | { | |
560 | u32 v; | |
561 | struct plat_serialomap_port *p = uart->p; | |
562 | int ret; | |
563 | ||
564 | uart->can_sleep = 0; | |
565 | uart->timeout = sleep_timeout; | |
566 | if (!uart->timeout) | |
567 | _omap_uart_block_sleep(uart); | |
568 | else { | |
569 | setup_timer(&uart->timer, omap_uart_idle_timer, | |
570 | (unsigned long) uart); | |
571 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
572 | omap_uart_smart_idle_enable(uart, 0); | |
573 | } | |
574 | ||
575 | if (cpu_is_omap34xx()) { | |
576 | u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD; | |
577 | u32 wk_mask = 0; | |
578 | u32 padconf = 0; | |
579 | ||
580 | uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); | |
581 | uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); | |
582 | switch (uart->num) { | |
583 | case 0: | |
584 | wk_mask = OMAP3430_ST_UART1_MASK; | |
585 | padconf = uart0_padconf; | |
586 | break; | |
587 | case 1: | |
588 | wk_mask = OMAP3430_ST_UART2_MASK; | |
589 | padconf = 0x17a; | |
590 | break; | |
591 | case 2: | |
592 | wk_mask = OMAP3430_ST_UART3_MASK; | |
593 | padconf = 0x19e; | |
594 | break; | |
595 | } | |
596 | uart->wk_mask = wk_mask; | |
597 | uart->padconf = padconf; | |
598 | } else if (cpu_is_omap24xx()) { | |
599 | u32 wk_mask = 0; | |
600 | ||
601 | if (cpu_is_omap2430()) { | |
602 | uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1); | |
603 | uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1); | |
604 | } else if (cpu_is_omap2420()) { | |
605 | uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1); | |
606 | uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1); | |
607 | } | |
608 | switch (uart->num) { | |
609 | case 0: | |
610 | wk_mask = OMAP24XX_ST_UART1_MASK; | |
611 | break; | |
612 | case 1: | |
613 | wk_mask = OMAP24XX_ST_UART2_MASK; | |
614 | break; | |
615 | case 2: | |
616 | wk_mask = OMAP24XX_ST_UART3_MASK; | |
617 | break; | |
618 | } | |
619 | uart->wk_mask = wk_mask; | |
620 | } else { | |
621 | uart->wk_en = 0; | |
622 | uart->wk_st = 0; | |
623 | uart->wk_mask = 0; | |
624 | uart->padconf = 0; | |
625 | } | |
626 | ||
627 | /* Set wake-enable bit */ | |
628 | if (uart->wk_en && uart->wk_mask) { | |
629 | v = __raw_readl(uart->wk_en); | |
630 | v |= uart->wk_mask; | |
631 | __raw_writel(v, uart->wk_en); | |
632 | } | |
633 | ||
634 | /* Ensure IOPAD wake-enables are set */ | |
635 | if (cpu_is_omap34xx() && uart->padconf) { | |
636 | u16 v; | |
637 | ||
638 | v = omap_ctrl_readw(uart->padconf); | |
639 | v |= OMAP3_PADCONF_WAKEUPENABLE0; | |
640 | omap_ctrl_writew(v, uart->padconf); | |
641 | } | |
642 | ||
643 | p->flags |= UPF_SHARE_IRQ; | |
644 | ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, | |
645 | "serial idle", (void *)uart); | |
646 | WARN_ON(ret); | |
647 | } | |
648 | ||
649 | void omap_uart_enable_irqs(int enable) | |
650 | { | |
651 | int ret; | |
652 | struct omap_uart_state *uart; | |
653 | ||
654 | list_for_each_entry(uart, &uart_list, node) { | |
655 | if (enable) | |
656 | ret = request_irq(uart->p->irq, omap_uart_interrupt, | |
657 | IRQF_SHARED, "serial idle", (void *)uart); | |
658 | else | |
659 | free_irq(uart->p->irq, (void *)uart); | |
660 | } | |
661 | } | |
662 | ||
663 | #if 0 | |
664 | static ssize_t sleep_timeout_show(struct kobject *kobj, | |
665 | struct kobj_attribute *attr, | |
666 | char *buf) | |
667 | { | |
668 | return sprintf(buf, "%u\n", sleep_timeout / HZ); | |
669 | } | |
670 | ||
671 | static ssize_t sleep_timeout_store(struct kobject *kobj, | |
672 | struct kobj_attribute *attr, | |
673 | const char *buf, size_t n) | |
674 | { | |
675 | struct omap_uart_state *uart; | |
676 | unsigned int value; | |
677 | ||
678 | if (sscanf(buf, "%u", &value) != 1) { | |
679 | printk(KERN_ERR "sleep_timeout_store: Invalid value\n"); | |
680 | return -EINVAL; | |
681 | } | |
682 | sleep_timeout = value * HZ; | |
683 | list_for_each_entry(uart, &uart_list, node) { | |
684 | uart->timeout = sleep_timeout; | |
685 | if (uart->timeout) | |
686 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
687 | else | |
688 | /* A zero value means disable timeout feature */ | |
689 | _omap_uart_block_sleep(uart); | |
690 | } | |
691 | return n; | |
692 | } | |
693 | ||
694 | static struct kobj_attribute sleep_timeout_attr = | |
695 | __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store); | |
696 | #endif | |
697 | ||
698 | #else | |
699 | static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} | |
700 | #endif /* CONFIG_PM */ | |
701 | ||
702 | static int fifo_idleblk_get(void *data, u64 *val) | |
703 | { | |
704 | *val = fifo_idleblks; | |
705 | return 0; | |
706 | } | |
707 | ||
708 | static int fifo_idleblk_set(void *data, u64 val) | |
709 | { | |
710 | fifo_idleblks = 0; | |
711 | return 0; | |
712 | } | |
713 | ||
714 | DEFINE_SIMPLE_ATTRIBUTE(fifo_idleblk_fops, fifo_idleblk_get, fifo_idleblk_set, "%llu\n"); | |
715 | void omap_serial_early_init(void) | |
716 | { | |
717 | } | |
718 | ||
719 | void omap_serial_ctsrts_init(unsigned char ctsrts[]) | |
720 | { | |
721 | #if defined(CONFIG_SERIAL_OMAP) && \ | |
722 | defined(CONFIG_SERIAL_OMAP3430_HW_FLOW_CONTROL) | |
723 | serial_platform_data[0].ctsrts = ctsrts[0]; | |
724 | serial_platform_data[1].ctsrts = ctsrts[1]; | |
725 | serial_platform_data[2].ctsrts = ctsrts[2]; | |
726 | #endif | |
727 | } | |
728 | ||
729 | void omap_uart_set_uart0_padconf(int padconf) | |
730 | { | |
731 | uart0_padconf = padconf; | |
732 | } | |
733 | ||
734 | void my_omap_serial_init(int wake_gpio_strobe, | |
735 | unsigned int wake_strobe_enable_mask) | |
736 | { | |
737 | int i; | |
738 | char name[16]; | |
739 | ||
740 | debugfs_create_file("fifo_idle_block_count", 0644, NULL, NULL, &fifo_idleblk_fops); | |
741 | /* | |
742 | * Make sure the serial ports are muxed on at this point. | |
743 | * You have to mux them off in device drivers later on | |
744 | * if not needed. | |
745 | */ | |
746 | ||
747 | i=2; | |
748 | { | |
749 | struct plat_serialomap_port *p = serial_platform_data + i; | |
750 | struct omap_uart_state *uart = &omap_uart[i]; | |
751 | ||
752 | if (wake_strobe_enable_mask & (1 << i)) | |
753 | p->wake_gpio_strobe = wake_gpio_strobe; | |
754 | ||
755 | sprintf(name, "uart%d_ick", i+1); | |
756 | uart->ick = clk_get(NULL, name); | |
757 | if (IS_ERR(uart->ick)) { | |
758 | printk(KERN_ERR "Could not get uart%d_ick\n", i+1); | |
759 | uart->ick = NULL; | |
760 | } | |
761 | ||
762 | sprintf(name, "uart%d_fck", i+1); | |
763 | uart->fck = clk_get(NULL, name); | |
764 | if (IS_ERR(uart->fck)) { | |
765 | printk(KERN_ERR "Could not get uart%d_fck\n", i+1); | |
766 | uart->fck = NULL; | |
767 | } | |
768 | ||
769 | if (!uart->ick || !uart->fck) | |
770 | return; | |
771 | ||
772 | uart->num = i; | |
773 | p->private_data = uart; | |
774 | uart->p = p; | |
775 | list_add(&uart->node, &uart_list); | |
776 | ||
777 | omap_uart_enable_clocks(uart); | |
778 | omap_uart_reset(uart); | |
779 | omap_uart_rtspad_init(uart); | |
780 | omap_uart_idle_init(uart); | |
781 | } | |
782 | } | |
783 | ||
784 | int my_omap_hs_init(void) | |
785 | { | |
786 | int ret = 0; | |
787 | ||
788 | ret = platform_add_devices(uart_devices, ARRAY_SIZE(uart_devices)); | |
789 | if (ret) { | |
790 | printk(KERN_ERR "Error adding uart devices (%d)\n", ret); | |
791 | return ret; | |
792 | } | |
793 | return ret; | |
794 | } |