git.zerfleddert.de Git - ms2-kexec/blob - proc-macros.S

   1 /*
   2  * We need constants.h for:
   3  *  VMA_VM_MM
   4  *  VMA_VM_FLAGS
   5  *  VM_EXEC
   6  */
   7 #include <asm/asm-offsets.h>
   8 #include <asm/thread_info.h>
   9
  10 /*
  11  * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
  12  */
  13         .macro  vma_vm_mm, rd, rn
  14         ldr     \rd, [\rn, #VMA_VM_MM]
  15         .endm
  16
  17 /*
  18  * vma_vm_flags - get vma->vm_flags
  19  */
  20         .macro  vma_vm_flags, rd, rn
  21         ldr     \rd, [\rn, #VMA_VM_FLAGS]
  22         .endm
  23
  24         .macro  tsk_mm, rd, rn
  25         ldr     \rd, [\rn, #TI_TASK]
  26         ldr     \rd, [\rd, #TSK_ACTIVE_MM]
  27         .endm
  28
  29 /*
  30  * act_mm - get current->active_mm
  31  */
  32         .macro  act_mm, rd
  33         bic     \rd, sp, #8128
  34         bic     \rd, \rd, #63
  35         ldr     \rd, [\rd, #TI_TASK]
  36         ldr     \rd, [\rd, #TSK_ACTIVE_MM]
  37         .endm
  38
  39 /*
  40  * mmid - get context id from mm pointer (mm->context.id)
  41  */
  42         .macro  mmid, rd, rn
  43         ldr     \rd, [\rn, #MM_CONTEXT_ID]
  44         .endm
  45
  46 /*
  47  * mask_asid - mask the ASID from the context ID
  48  */
  49         .macro  asid, rd, rn
  50         and     \rd, \rn, #255
  51         .endm
  52
  53         .macro  crval, clear, mmuset, ucset
  54 #ifdef CONFIG_MMU
  55         .word   \clear
  56         .word   \mmuset
  57 #else
  58         .word   \clear
  59         .word   \ucset
  60 #endif
  61         .endm
  62
  63 /*
  64  * dcache_line_size - get the minimum D-cache line size from the CTR register
  65  * on ARMv7.
  66  */
  67         .macro  dcache_line_size, reg, tmp
  68         mrc     p15, 0, \tmp, c0, c0, 1         @ read ctr
  69         lsr     \tmp, \tmp, #16
  70         and     \tmp, \tmp, #0xf                @ cache line size encoding
  71         mov     \reg, #4                        @ bytes per word
  72         mov     \reg, \reg, lsl \tmp            @ actual cache line size
  73         .endm
  74
  75 /*
  76  * icache_line_size - get the minimum I-cache line size from the CTR register
  77  * on ARMv7.
  78  */
  79         .macro  icache_line_size, reg, tmp
  80         mrc     p15, 0, \tmp, c0, c0, 1         @ read ctr
  81         and     \tmp, \tmp, #0xf                @ cache line size encoding
  82         mov     \reg, #4                        @ bytes per word
  83         mov     \reg, \reg, lsl \tmp            @ actual cache line size
  84         .endm
  85
  86 /*
  87  * Sanity check the PTE configuration for the code below - which makes
  88  * certain assumptions about how these bits are laid out.
  89  */
  90 #ifdef CONFIG_MMU
  91 #if L_PTE_SHARED != PTE_EXT_SHARED
  92 #error PTE shared bit mismatch
  93 #endif
  94 #if (L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
  95      L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
  96 #error Invalid Linux PTE bit settings
  97 #endif
  98 #endif  /* CONFIG_MMU */
  99
 100 /*
 101  * The ARMv6 and ARMv7 set_pte_ext translation function.
 102  *
 103  * Permission translation:
 104  *  YUWD  APX AP1 AP0   SVC     User
 105  *  0xxx   0   0   0    no acc  no acc
 106  *  100x   1   0   1    r/o     no acc
 107  *  10x0   1   0   1    r/o     no acc
 108  *  1011   0   0   1    r/w     no acc
 109  *  110x   0   1   0    r/w     r/o
 110  *  11x0   0   1   0    r/w     r/o
 111  *  1111   0   1   1    r/w     r/w
 112  *
 113  * If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
 114  *  110x   1   1   1    r/o     r/o
 115  *  11x0   1   1   1    r/o     r/o
 116  */
 117         .macro  armv6_mt_table pfx
 118 \pfx\()_mt_table:
 119         .long   0x00                                            @ L_PTE_MT_UNCACHED
 120         .long   PTE_EXT_TEX(1)                                  @ L_PTE_MT_BUFFERABLE
 121         .long   PTE_CACHEABLE                                   @ L_PTE_MT_WRITETHROUGH
 122         .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_WRITEBACK
 123         .long   PTE_BUFFERABLE                                  @ L_PTE_MT_DEV_SHARED
 124         .long   0x00                                            @ unused
 125         .long   0x00                                            @ L_PTE_MT_MINICACHE (not present)
 126         .long   PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
 127         .long   0x00                                            @ unused
 128         .long   PTE_EXT_TEX(1)                                  @ L_PTE_MT_DEV_WC
 129         .long   0x00                                            @ unused
 130         .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_DEV_CACHED
 131         .long   PTE_EXT_TEX(2)                                  @ L_PTE_MT_DEV_NONSHARED
 132         .long   0x00                                            @ unused
 133         .long   0x00                                            @ unused
 134         .long   0x00                                            @ unused
 135         .endm
 136
 137         .macro  armv6_set_pte_ext pfx
 138         str     r1, [r0], #2048                 @ linux version
 139
 140         bic     r3, r1, #0x000003fc
 141         bic     r3, r3, #PTE_TYPE_MASK
 142         orr     r3, r3, r2
 143         orr     r3, r3, #PTE_EXT_AP0 | 2
 144
 145         adr     ip, \pfx\()_mt_table
 146         and     r2, r1, #L_PTE_MT_MASK
 147         ldr     r2, [ip, r2]
 148
 149         eor     r1, r1, #L_PTE_DIRTY
 150         tst     r1, #L_PTE_DIRTY|L_PTE_RDONLY
 151         orrne   r3, r3, #PTE_EXT_APX
 152
 153         tst     r1, #L_PTE_USER
 154         orrne   r3, r3, #PTE_EXT_AP1
 155 #ifdef CONFIG_CPU_USE_DOMAINS
 156         @ allow kernel read/write access to read-only user pages
 157         tstne   r3, #PTE_EXT_APX
 158         bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
 159 #endif
 160
 161         tst     r1, #L_PTE_XN
 162         orrne   r3, r3, #PTE_EXT_XN
 163
 164         orr     r3, r3, r2
 165
 166         tst     r1, #L_PTE_YOUNG
 167         tstne   r1, #L_PTE_PRESENT
 168         moveq   r3, #0
 169
 170         str     r3, [r0]
 171         mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
 172         .endm
 173
 174
 175 /*
 176  * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
 177  * covering most CPUs except Xscale and Xscale 3.
 178  *
 179  * Permission translation:
 180  *  YUWD   AP   SVC     User
 181  *  0xxx  0x00  no acc  no acc
 182  *  100x  0x00  r/o     no acc
 183  *  10x0  0x00  r/o     no acc
 184  *  1011  0x55  r/w     no acc
 185  *  110x  0xaa  r/w     r/o
 186  *  11x0  0xaa  r/w     r/o
 187  *  1111  0xff  r/w     r/w
 188  */
 189         .macro  armv3_set_pte_ext wc_disable=1
 190         str     r1, [r0], #2048                 @ linux version
 191
 192         eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
 193
 194         bic     r2, r1, #PTE_SMALL_AP_MASK      @ keep C, B bits
 195         bic     r2, r2, #PTE_TYPE_MASK
 196         orr     r2, r2, #PTE_TYPE_SMALL
 197
 198         tst     r3, #L_PTE_USER                 @ user?
 199         orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
 200
 201         tst     r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
 202         orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
 203
 204         tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ present and young?
 205         movne   r2, #0
 206
 207         .if     \wc_disable
 208 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 209         tst     r2, #PTE_CACHEABLE
 210         bicne   r2, r2, #PTE_BUFFERABLE
 211 #endif
 212         .endif
 213         str     r2, [r0]                @ hardware version
 214         .endm
 215
 216
 217 /*
 218  * Xscale set_pte_ext translation, split into two halves to cope
 219  * with work-arounds.  r3 must be preserved by code between these
 220  * two macros.
 221  *
 222  * Permission translation:
 223  *  YUWD  AP    SVC     User
 224  *  0xxx  00    no acc  no acc
 225  *  100x  00    r/o     no acc
 226  *  10x0  00    r/o     no acc
 227  *  1011  01    r/w     no acc
 228  *  110x  10    r/w     r/o
 229  *  11x0  10    r/w     r/o
 230  *  1111  11    r/w     r/w
 231  */
 232         .macro  xscale_set_pte_ext_prologue
 233         str     r1, [r0]                        @ linux version
 234
 235         eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
 236
 237         bic     r2, r1, #PTE_SMALL_AP_MASK      @ keep C, B bits
 238         orr     r2, r2, #PTE_TYPE_EXT           @ extended page
 239
 240         tst     r3, #L_PTE_USER                 @ user?
 241         orrne   r2, r2, #PTE_EXT_AP_URO_SRW     @ yes -> user r/o, system r/w
 242
 243         tst     r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
 244         orreq   r2, r2, #PTE_EXT_AP_UNO_SRW     @ yes -> user n/a, system r/w
 245                                                 @ combined with user -> user r/w
 246         .endm
 247
 248         .macro  xscale_set_pte_ext_epilogue
 249         tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ present and young?
 250         movne   r2, #0                          @ no -> fault
 251
 252         str     r2, [r0, #2048]!                @ hardware version
 253         mov     ip, #0
 254         mcr     p15, 0, r0, c7, c10, 1          @ clean L1 D line
 255         mcr     p15, 0, ip, c7, c10, 4          @ data write barrier
 256         .endm