fix: introduced a stupid error when refactoring the start bit detector in MillerDecod...
[proxmark3-svn] / armsrc / iso14443a.c
CommitLineData
15c4dc5a 1//-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
12
e30c654b 13#include "proxmark3.h"
15c4dc5a 14#include "apps.h"
f7e3ed82 15#include "util.h"
9ab7a6c7 16#include "string.h"
902cb3c0 17#include "cmd.h"
9ab7a6c7 18
15c4dc5a 19#include "iso14443crc.h"
534983d7 20#include "iso14443a.h"
20f9a2a1
M
21#include "crapto1.h"
22#include "mifareutil.h"
3000dc4e 23#include "BigBuf.h"
534983d7 24static uint32_t iso14a_timeout;
1e262141 25int rsamples = 0;
1e262141 26uint8_t trigger = 0;
b0127e65 27// the block number for the ISO14443-4 PCB
28static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 29
7bc95e2e 30//
31// ISO14443 timing:
32//
33// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
34#define REQUEST_GUARD_TIME (7000/16 + 1)
35// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
36#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
37// bool LastCommandWasRequest = FALSE;
38
39//
40// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
41//
d714d3ef 42// When the PM acts as reader and is receiving tag data, it takes
43// 3 ticks delay in the AD converter
44// 16 ticks until the modulation detector completes and sets curbit
45// 8 ticks until bit_to_arm is assigned from curbit
46// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 47// 4*16 ticks until we measure the time
48// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 49#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 50
51// When the PM acts as a reader and is sending, it takes
52// 4*16 ticks until we can write data to the sending hold register
53// 8*16 ticks until the SHR is transferred to the Sending Shift Register
54// 8 ticks until the first transfer starts
55// 8 ticks later the FPGA samples the data
56// 1 tick to assign mod_sig_coil
57#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
58
59// When the PM acts as tag and is receiving it takes
d714d3ef 60// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 61// 3 ticks for the A/D conversion,
62// 8 ticks on average until the start of the SSC transfer,
63// 8 ticks until the SSC samples the first data
64// 7*16 ticks to complete the transfer from FPGA to ARM
65// 8 ticks until the next ssp_clk rising edge
d714d3ef 66// 4*16 ticks until we measure the time
7bc95e2e 67// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 68#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
7bc95e2e 69
70// The FPGA will report its internal sending delay in
71uint16_t FpgaSendQueueDelay;
72// the 5 first bits are the number of bits buffered in mod_sig_buf
73// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
74#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
75
76// When the PM acts as tag and is sending, it takes
d714d3ef 77// 4*16 ticks until we can write data to the sending hold register
7bc95e2e 78// 8*16 ticks until the SHR is transferred to the Sending Shift Register
79// 8 ticks until the first transfer starts
80// 8 ticks later the FPGA samples the data
81// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
82// + 1 tick to assign mod_sig_coil
d714d3ef 83#define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
7bc95e2e 84
85// When the PM acts as sniffer and is receiving tag data, it takes
86// 3 ticks A/D conversion
d714d3ef 87// 14 ticks to complete the modulation detection
88// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 89// + the delays in transferring data - which is the same for
90// sniffing reader and tag data and therefore not relevant
d714d3ef 91#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
7bc95e2e 92
d714d3ef 93// When the PM acts as sniffer and is receiving reader data, it takes
94// 2 ticks delay in analogue RF receiver (for the falling edge of the
95// start bit, which marks the start of the communication)
7bc95e2e 96// 3 ticks A/D conversion
d714d3ef 97// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 98// + the delays in transferring data - which is the same for
99// sniffing reader and tag data and therefore not relevant
d714d3ef 100#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 101
102//variables used for timing purposes:
103//these are in ssp_clk cycles:
6a1f2d82 104static uint32_t NextTransferTime;
105static uint32_t LastTimeProxToAirStart;
106static uint32_t LastProxToAirDuration;
7bc95e2e 107
108
109
8f51ddb0 110// CARD TO READER - manchester
72934aa3 111// Sequence D: 11110000 modulation with subcarrier during first half
112// Sequence E: 00001111 modulation with subcarrier during second half
113// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 114// READER TO CARD - miller
72934aa3 115// Sequence X: 00001100 drop after half a period
116// Sequence Y: 00000000 no drop
117// Sequence Z: 11000000 drop at start
118#define SEC_D 0xf0
119#define SEC_E 0x0f
120#define SEC_F 0x00
121#define SEC_X 0x0c
122#define SEC_Y 0x00
123#define SEC_Z 0xc0
15c4dc5a 124
1e262141 125const uint8_t OddByteParity[256] = {
15c4dc5a 126 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
127 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
128 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
129 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
130 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
131 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
134 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
135 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
136 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
137 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
138 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
139 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
142};
143
19a700a8 144
902cb3c0 145void iso14a_set_trigger(bool enable) {
534983d7 146 trigger = enable;
147}
148
d19929cb 149
b0127e65 150void iso14a_set_timeout(uint32_t timeout) {
151 iso14a_timeout = timeout;
19a700a8 152 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
b0127e65 153}
8556b852 154
19a700a8 155
156void iso14a_set_ATS_timeout(uint8_t *ats) {
157
158 uint8_t tb1;
159 uint8_t fwi;
160 uint32_t fwt;
161
162 if (ats[0] > 1) { // there is a format byte T0
163 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
164 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
165 tb1 = ats[3];
166 } else {
167 tb1 = ats[2];
168 }
169 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
170 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
171
172 iso14a_set_timeout(fwt/(8*16));
173 }
174 }
175}
176
177
15c4dc5a 178//-----------------------------------------------------------------------------
179// Generate the parity value for a byte sequence
e30c654b 180//
15c4dc5a 181//-----------------------------------------------------------------------------
20f9a2a1
M
182byte_t oddparity (const byte_t bt)
183{
5f6d6c90 184 return OddByteParity[bt];
20f9a2a1
M
185}
186
6a1f2d82 187void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
15c4dc5a 188{
6a1f2d82 189 uint16_t paritybit_cnt = 0;
190 uint16_t paritybyte_cnt = 0;
191 uint8_t parityBits = 0;
192
193 for (uint16_t i = 0; i < iLen; i++) {
194 // Generate the parity bits
195 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
196 if (paritybit_cnt == 7) {
197 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
198 parityBits = 0; // and advance to next Parity Byte
199 paritybyte_cnt++;
200 paritybit_cnt = 0;
201 } else {
202 paritybit_cnt++;
203 }
5f6d6c90 204 }
6a1f2d82 205
206 // save remaining parity bits
207 par[paritybyte_cnt] = parityBits;
208
15c4dc5a 209}
210
534983d7 211void AppendCrc14443a(uint8_t* data, int len)
15c4dc5a 212{
5f6d6c90 213 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 214}
215
7bc95e2e 216//=============================================================================
217// ISO 14443 Type A - Miller decoder
218//=============================================================================
219// Basics:
220// This decoder is used when the PM3 acts as a tag.
221// The reader will generate "pauses" by temporarily switching of the field.
222// At the PM3 antenna we will therefore measure a modulated antenna voltage.
223// The FPGA does a comparison with a threshold and would deliver e.g.:
224// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
225// The Miller decoder needs to identify the following sequences:
226// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
227// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
228// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
229// Note 1: the bitstream may start at any time. We therefore need to sync.
230// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 231//-----------------------------------------------------------------------------
b62a5a84 232static tUart Uart;
15c4dc5a 233
d7aa3739 234// Lookup-Table to decide if 4 raw bits are a modulation.
05ddb52c 235// We accept the following:
236// 0001 - a 3 tick wide pause
237// 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
238// 0111 - a 2 tick wide pause shifted left
239// 1001 - a 2 tick wide pause shifted right
d7aa3739 240const bool Mod_Miller_LUT[] = {
05ddb52c 241// TRUE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE,
242// TRUE, TRUE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE
243 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
244 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
d7aa3739 245};
05ddb52c 246#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
247#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
d7aa3739 248
7bc95e2e 249void UartReset()
15c4dc5a 250{
7bc95e2e 251 Uart.state = STATE_UNSYNCD;
252 Uart.bitCount = 0;
253 Uart.len = 0; // number of decoded data bytes
6a1f2d82 254 Uart.parityLen = 0; // number of decoded parity bytes
7bc95e2e 255 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
6a1f2d82 256 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 257 Uart.startTime = 0;
258 Uart.endTime = 0;
259}
15c4dc5a 260
6a1f2d82 261void UartInit(uint8_t *data, uint8_t *parity)
262{
263 Uart.output = data;
264 Uart.parity = parity;
05ddb52c 265 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
6a1f2d82 266 UartReset();
267}
d714d3ef 268
7bc95e2e 269// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
270static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
271{
15c4dc5a 272
ef00343c 273 Uart.fourBits = (Uart.fourBits << 8) | bit;
7bc95e2e 274
0c8d25eb 275 if (Uart.state == STATE_UNSYNCD) { // not yet synced
3fe4ff4f 276
ef00343c 277 Uart.syncBit = 9999; // not set
05ddb52c 278 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
279 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
280 // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern
281 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
282#define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000
283#define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000
284 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
285 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
286 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
287 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
288 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
289 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
290 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
291 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
292
ef00343c 293 if (Uart.syncBit != 9999) { // found a sync bit
294 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
295 Uart.startTime -= Uart.syncBit;
296 Uart.endTime = Uart.startTime;
297 Uart.state = STATE_START_OF_COMMUNICATION;
7bc95e2e 298 }
15c4dc5a 299
7bc95e2e 300 } else {
15c4dc5a 301
ef00343c 302 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
303 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
d7aa3739 304 UartReset();
d7aa3739 305 } else { // Modulation in first half = Sequence Z = logic "0"
7bc95e2e 306 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
307 UartReset();
7bc95e2e 308 } else {
309 Uart.bitCount++;
310 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
311 Uart.state = STATE_MILLER_Z;
312 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
313 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
314 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
315 Uart.parityBits <<= 1; // make room for the parity bit
316 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
317 Uart.bitCount = 0;
318 Uart.shiftReg = 0;
6a1f2d82 319 if((Uart.len&0x0007) == 0) { // every 8 data bytes
320 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
321 Uart.parityBits = 0;
322 }
15c4dc5a 323 }
7bc95e2e 324 }
d7aa3739 325 }
326 } else {
ef00343c 327 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 328 Uart.bitCount++;
329 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
330 Uart.state = STATE_MILLER_X;
331 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
332 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
333 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
334 Uart.parityBits <<= 1; // make room for the new parity bit
335 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
336 Uart.bitCount = 0;
337 Uart.shiftReg = 0;
6a1f2d82 338 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
339 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
340 Uart.parityBits = 0;
341 }
7bc95e2e 342 }
d7aa3739 343 } else { // no modulation in both halves - Sequence Y
7bc95e2e 344 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
15c4dc5a 345 Uart.state = STATE_UNSYNCD;
6a1f2d82 346 Uart.bitCount--; // last "0" was part of EOC sequence
347 Uart.shiftReg <<= 1; // drop it
348 if(Uart.bitCount > 0) { // if we decoded some bits
349 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
350 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
351 Uart.parityBits <<= 1; // add a (void) parity bit
352 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
353 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
354 return TRUE;
355 } else if (Uart.len & 0x0007) { // there are some parity bits to store
356 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
357 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
52bfb955 358 }
359 if (Uart.len) {
6a1f2d82 360 return TRUE; // we are finished with decoding the raw data sequence
52bfb955 361 } else {
0c8d25eb 362 UartReset(); // Nothing received - start over
7bc95e2e 363 }
15c4dc5a 364 }
7bc95e2e 365 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
366 UartReset();
7bc95e2e 367 } else { // a logic "0"
368 Uart.bitCount++;
369 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
370 Uart.state = STATE_MILLER_Y;
371 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
372 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
373 Uart.parityBits <<= 1; // make room for the parity bit
374 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
375 Uart.bitCount = 0;
376 Uart.shiftReg = 0;
6a1f2d82 377 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
378 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
379 Uart.parityBits = 0;
380 }
15c4dc5a 381 }
382 }
d7aa3739 383 }
15c4dc5a 384 }
7bc95e2e 385
386 }
15c4dc5a 387
7bc95e2e 388 return FALSE; // not finished yet, need more data
15c4dc5a 389}
390
7bc95e2e 391
392
15c4dc5a 393//=============================================================================
e691fc45 394// ISO 14443 Type A - Manchester decoder
15c4dc5a 395//=============================================================================
e691fc45 396// Basics:
7bc95e2e 397// This decoder is used when the PM3 acts as a reader.
e691fc45 398// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
399// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
400// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
401// The Manchester decoder needs to identify the following sequences:
402// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
403// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
404// 8 ticks unmodulated: Sequence F = end of communication
405// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 406// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 407// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 408static tDemod Demod;
15c4dc5a 409
d7aa3739 410// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 411// We accept three or four "1" in any position
7bc95e2e 412const bool Mod_Manchester_LUT[] = {
d7aa3739 413 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
d714d3ef 414 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
7bc95e2e 415};
416
417#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
418#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 419
2f2d9fc5 420
7bc95e2e 421void DemodReset()
e691fc45 422{
7bc95e2e 423 Demod.state = DEMOD_UNSYNCD;
424 Demod.len = 0; // number of decoded data bytes
6a1f2d82 425 Demod.parityLen = 0;
7bc95e2e 426 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
427 Demod.parityBits = 0; //
428 Demod.collisionPos = 0; // Position of collision bit
429 Demod.twoBits = 0xffff; // buffer for 2 Bits
430 Demod.highCnt = 0;
431 Demod.startTime = 0;
432 Demod.endTime = 0;
e691fc45 433}
15c4dc5a 434
6a1f2d82 435void DemodInit(uint8_t *data, uint8_t *parity)
436{
437 Demod.output = data;
438 Demod.parity = parity;
439 DemodReset();
440}
441
7bc95e2e 442// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
443static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
e691fc45 444{
7bc95e2e 445
446 Demod.twoBits = (Demod.twoBits << 8) | bit;
e691fc45 447
7bc95e2e 448 if (Demod.state == DEMOD_UNSYNCD) {
449
450 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
451 if (Demod.twoBits == 0x0000) {
452 Demod.highCnt++;
453 } else {
454 Demod.highCnt = 0;
455 }
456 } else {
457 Demod.syncBit = 0xFFFF; // not set
458 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
459 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
460 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
461 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
462 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
463 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
464 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
465 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 466 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 467 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
468 Demod.startTime -= Demod.syncBit;
469 Demod.bitCount = offset; // number of decoded data bits
e691fc45 470 Demod.state = DEMOD_MANCHESTER_DATA;
2f2d9fc5 471 }
7bc95e2e 472 }
15c4dc5a 473
7bc95e2e 474 } else {
15c4dc5a 475
7bc95e2e 476 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
477 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 478 if (!Demod.collisionPos) {
479 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
480 }
481 } // modulation in first half only - Sequence D = 1
7bc95e2e 482 Demod.bitCount++;
483 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
484 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 485 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 486 Demod.parityBits <<= 1; // make room for the parity bit
e691fc45 487 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
488 Demod.bitCount = 0;
489 Demod.shiftReg = 0;
6a1f2d82 490 if((Demod.len&0x0007) == 0) { // every 8 data bytes
491 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
492 Demod.parityBits = 0;
493 }
15c4dc5a 494 }
7bc95e2e 495 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
496 } else { // no modulation in first half
497 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 498 Demod.bitCount++;
7bc95e2e 499 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
e691fc45 500 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 501 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 502 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 503 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
504 Demod.bitCount = 0;
505 Demod.shiftReg = 0;
6a1f2d82 506 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
507 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
508 Demod.parityBits = 0;
509 }
15c4dc5a 510 }
7bc95e2e 511 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
e691fc45 512 } else { // no modulation in both halves - End of communication
6a1f2d82 513 if(Demod.bitCount > 0) { // there are some remaining data bits
514 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
515 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
516 Demod.parityBits <<= 1; // add a (void) parity bit
517 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
518 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
519 return TRUE;
520 } else if (Demod.len & 0x0007) { // there are some parity bits to store
521 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
522 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
52bfb955 523 }
524 if (Demod.len) {
d7aa3739 525 return TRUE; // we are finished with decoding the raw data sequence
526 } else { // nothing received. Start over
527 DemodReset();
e691fc45 528 }
15c4dc5a 529 }
7bc95e2e 530 }
e691fc45 531
532 }
15c4dc5a 533
e691fc45 534 return FALSE; // not finished yet, need more data
15c4dc5a 535}
536
537//=============================================================================
538// Finally, a `sniffer' for ISO 14443 Type A
539// Both sides of communication!
540//=============================================================================
541
542//-----------------------------------------------------------------------------
543// Record the sequence of commands sent by the reader to the tag, with
544// triggering so that we start recording at the point that the tag is moved
545// near the reader.
546//-----------------------------------------------------------------------------
5cd9ec01
M
547void RAMFUNC SnoopIso14443a(uint8_t param) {
548 // param:
549 // bit 0 - trigger from first card answer
550 // bit 1 - trigger from first reader 7-bit request
551
552 LEDsoff();
5cd9ec01
M
553
554 // We won't start recording the frames that we acquire until we trigger;
555 // a good trigger condition to get started is probably when we see a
556 // response from the tag.
557 // triggered == FALSE -- to wait first for card
7bc95e2e 558 bool triggered = !(param & 0x03);
559
f71f4deb 560 // Allocate memory from BigBuf for some buffers
561 // free all previous allocations first
562 BigBuf_free();
563
5cd9ec01 564 // The command (reader -> tag) that we're receiving.
f71f4deb 565 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
566 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
6a1f2d82 567
5cd9ec01 568 // The response (tag -> reader) that we're receiving.
f71f4deb 569 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
570 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
5cd9ec01
M
571
572 // The DMA buffer, used to stream samples from the FPGA
f71f4deb 573 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
574
575 // init trace buffer
3000dc4e
MHS
576 clear_trace();
577 set_tracing(TRUE);
f71f4deb 578
7bc95e2e 579 uint8_t *data = dmaBuf;
580 uint8_t previous_data = 0;
5cd9ec01
M
581 int maxDataLen = 0;
582 int dataLen = 0;
7bc95e2e 583 bool TagIsActive = FALSE;
584 bool ReaderIsActive = FALSE;
585
586 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
15c4dc5a 587
5cd9ec01 588 // Set up the demodulator for tag -> reader responses.
6a1f2d82 589 DemodInit(receivedResponse, receivedResponsePar);
590
5cd9ec01 591 // Set up the demodulator for the reader -> tag commands
6a1f2d82 592 UartInit(receivedCmd, receivedCmdPar);
593
7bc95e2e 594 // Setup and start DMA.
5cd9ec01 595 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
7bc95e2e 596
5cd9ec01 597 // And now we loop, receiving samples.
7bc95e2e 598 for(uint32_t rsamples = 0; TRUE; ) {
599
5cd9ec01
M
600 if(BUTTON_PRESS()) {
601 DbpString("cancelled by button");
7bc95e2e 602 break;
5cd9ec01 603 }
15c4dc5a 604
5cd9ec01
M
605 LED_A_ON();
606 WDT_HIT();
15c4dc5a 607
5cd9ec01
M
608 int register readBufDataP = data - dmaBuf;
609 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
610 if (readBufDataP <= dmaBufDataP){
611 dataLen = dmaBufDataP - readBufDataP;
612 } else {
7bc95e2e 613 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
614 }
615 // test for length of buffer
616 if(dataLen > maxDataLen) {
617 maxDataLen = dataLen;
f71f4deb 618 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
7bc95e2e 619 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
620 break;
5cd9ec01
M
621 }
622 }
623 if(dataLen < 1) continue;
624
625 // primary buffer was stopped( <-- we lost data!
626 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
627 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
628 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 629 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
630 }
631 // secondary buffer sets as primary, secondary buffer was stopped
632 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
633 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
634 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
635 }
636
637 LED_A_OFF();
7bc95e2e 638
639 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 640
7bc95e2e 641 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
642 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
643 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
644 LED_C_ON();
5cd9ec01 645
7bc95e2e 646 // check - if there is a short 7bit request from reader
647 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
5cd9ec01 648
7bc95e2e 649 if(triggered) {
6a1f2d82 650 if (!LogTrace(receivedCmd,
651 Uart.len,
652 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
653 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
654 Uart.parity,
655 TRUE)) break;
7bc95e2e 656 }
657 /* And ready to receive another command. */
05ddb52c 658 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 659 /* And also reset the demod code, which might have been */
660 /* false-triggered by the commands from the reader. */
661 DemodReset();
662 LED_B_OFF();
663 }
664 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 665 }
3be2a5ae 666
7bc95e2e 667 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
668 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
669 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
670 LED_B_ON();
5cd9ec01 671
6a1f2d82 672 if (!LogTrace(receivedResponse,
673 Demod.len,
674 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
675 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
676 Demod.parity,
677 FALSE)) break;
5cd9ec01 678
7bc95e2e 679 if ((!triggered) && (param & 0x01)) triggered = TRUE;
5cd9ec01 680
7bc95e2e 681 // And ready to receive another response.
682 DemodReset();
683 LED_C_OFF();
684 }
685 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
686 }
5cd9ec01
M
687 }
688
7bc95e2e 689 previous_data = *data;
690 rsamples++;
5cd9ec01 691 data++;
d714d3ef 692 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
693 data = dmaBuf;
694 }
695 } // main cycle
696
697 DbpString("COMMAND FINISHED");
15c4dc5a 698
7bc95e2e 699 FpgaDisableSscDma();
700 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
3000dc4e 701 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
5cd9ec01 702 LEDsoff();
15c4dc5a 703}
704
15c4dc5a 705//-----------------------------------------------------------------------------
706// Prepare tag messages
707//-----------------------------------------------------------------------------
6a1f2d82 708static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
15c4dc5a 709{
8f51ddb0 710 ToSendReset();
15c4dc5a 711
712 // Correction bit, might be removed when not needed
713 ToSendStuffBit(0);
714 ToSendStuffBit(0);
715 ToSendStuffBit(0);
716 ToSendStuffBit(0);
717 ToSendStuffBit(1); // 1
718 ToSendStuffBit(0);
719 ToSendStuffBit(0);
720 ToSendStuffBit(0);
8f51ddb0 721
15c4dc5a 722 // Send startbit
72934aa3 723 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 724 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 725
6a1f2d82 726 for(uint16_t i = 0; i < len; i++) {
8f51ddb0 727 uint8_t b = cmd[i];
15c4dc5a 728
729 // Data bits
6a1f2d82 730 for(uint16_t j = 0; j < 8; j++) {
15c4dc5a 731 if(b & 1) {
72934aa3 732 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 733 } else {
72934aa3 734 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
735 }
736 b >>= 1;
737 }
15c4dc5a 738
0014cb46 739 // Get the parity bit
6a1f2d82 740 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 741 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 742 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 743 } else {
72934aa3 744 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 745 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 746 }
8f51ddb0 747 }
15c4dc5a 748
8f51ddb0
M
749 // Send stopbit
750 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 751
8f51ddb0
M
752 // Convert from last byte pos to length
753 ToSendMax++;
8f51ddb0
M
754}
755
6a1f2d82 756static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
757{
758 uint8_t par[MAX_PARITY_SIZE];
759
760 GetParity(cmd, len, par);
761 CodeIso14443aAsTagPar(cmd, len, par);
15c4dc5a 762}
763
15c4dc5a 764
8f51ddb0
M
765static void Code4bitAnswerAsTag(uint8_t cmd)
766{
767 int i;
768
5f6d6c90 769 ToSendReset();
8f51ddb0
M
770
771 // Correction bit, might be removed when not needed
772 ToSendStuffBit(0);
773 ToSendStuffBit(0);
774 ToSendStuffBit(0);
775 ToSendStuffBit(0);
776 ToSendStuffBit(1); // 1
777 ToSendStuffBit(0);
778 ToSendStuffBit(0);
779 ToSendStuffBit(0);
780
781 // Send startbit
782 ToSend[++ToSendMax] = SEC_D;
783
784 uint8_t b = cmd;
785 for(i = 0; i < 4; i++) {
786 if(b & 1) {
787 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 788 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
789 } else {
790 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 791 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
792 }
793 b >>= 1;
794 }
795
796 // Send stopbit
797 ToSend[++ToSendMax] = SEC_F;
798
5f6d6c90 799 // Convert from last byte pos to length
800 ToSendMax++;
15c4dc5a 801}
802
803//-----------------------------------------------------------------------------
804// Wait for commands from reader
805// Stop when button is pressed
806// Or return TRUE when command is captured
807//-----------------------------------------------------------------------------
6a1f2d82 808static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
15c4dc5a 809{
810 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
811 // only, since we are receiving, not transmitting).
812 // Signal field is off with the appropriate LED
813 LED_D_OFF();
814 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
815
816 // Now run a `software UART' on the stream of incoming samples.
6a1f2d82 817 UartInit(received, parity);
7bc95e2e 818
819 // clear RXRDY:
820 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 821
822 for(;;) {
823 WDT_HIT();
824
825 if(BUTTON_PRESS()) return FALSE;
7bc95e2e 826
15c4dc5a 827 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
7bc95e2e 828 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
829 if(MillerDecoding(b, 0)) {
830 *len = Uart.len;
15c4dc5a 831 return TRUE;
832 }
7bc95e2e 833 }
15c4dc5a 834 }
835}
28afbd2b 836
6a1f2d82 837static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
7bc95e2e 838int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
28afbd2b 839int EmSend4bit(uint8_t resp);
6a1f2d82 840int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
841int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
842int EmSendCmd(uint8_t *resp, uint16_t respLen);
843int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
844bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
845 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
15c4dc5a 846
117d9ec2 847static uint8_t* free_buffer_pointer;
ce02f6f9 848
849typedef struct {
850 uint8_t* response;
851 size_t response_n;
852 uint8_t* modulation;
853 size_t modulation_n;
7bc95e2e 854 uint32_t ProxToAirDuration;
ce02f6f9 855} tag_response_info_t;
856
ce02f6f9 857bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 858 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 859 // This will need the following byte array for a modulation sequence
860 // 144 data bits (18 * 8)
861 // 18 parity bits
862 // 2 Start and stop
863 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
864 // 1 just for the case
865 // ----------- +
866 // 166 bytes, since every bit that needs to be send costs us a byte
867 //
f71f4deb 868
869
ce02f6f9 870 // Prepare the tag modulation bits from the message
871 CodeIso14443aAsTag(response_info->response,response_info->response_n);
872
873 // Make sure we do not exceed the free buffer space
874 if (ToSendMax > max_buffer_size) {
875 Dbprintf("Out of memory, when modulating bits for tag answer:");
876 Dbhexdump(response_info->response_n,response_info->response,false);
877 return false;
878 }
879
880 // Copy the byte array, used for this modulation to the buffer position
881 memcpy(response_info->modulation,ToSend,ToSendMax);
882
7bc95e2e 883 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
ce02f6f9 884 response_info->modulation_n = ToSendMax;
7bc95e2e 885 response_info->ProxToAirDuration = LastProxToAirDuration;
ce02f6f9 886
887 return true;
888}
889
f71f4deb 890
891// "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
892// Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
893// 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
894// -> need 273 bytes buffer
895#define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
896
ce02f6f9 897bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
898 // Retrieve and store the current buffer index
899 response_info->modulation = free_buffer_pointer;
900
901 // Determine the maximum size we can use from our buffer
f71f4deb 902 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
ce02f6f9 903
904 // Forward the prepare tag modulation function to the inner function
f71f4deb 905 if (prepare_tag_modulation(response_info, max_buffer_size)) {
ce02f6f9 906 // Update the free buffer offset
907 free_buffer_pointer += ToSendMax;
908 return true;
909 } else {
910 return false;
911 }
912}
913
15c4dc5a 914//-----------------------------------------------------------------------------
915// Main loop of simulated tag: receive commands from reader, decide what
916// response to send, and send it.
917//-----------------------------------------------------------------------------
28afbd2b 918void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
15c4dc5a 919{
81cd0474 920 uint8_t sak;
921
922 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
923 uint8_t response1[2];
924
925 switch (tagType) {
926 case 1: { // MIFARE Classic
927 // Says: I am Mifare 1k - original line
928 response1[0] = 0x04;
929 response1[1] = 0x00;
930 sak = 0x08;
931 } break;
932 case 2: { // MIFARE Ultralight
933 // Says: I am a stupid memory tag, no crypto
934 response1[0] = 0x04;
935 response1[1] = 0x00;
936 sak = 0x00;
937 } break;
938 case 3: { // MIFARE DESFire
939 // Says: I am a DESFire tag, ph33r me
940 response1[0] = 0x04;
941 response1[1] = 0x03;
942 sak = 0x20;
943 } break;
944 case 4: { // ISO/IEC 14443-4
945 // Says: I am a javacard (JCOP)
946 response1[0] = 0x04;
947 response1[1] = 0x00;
948 sak = 0x28;
949 } break;
3fe4ff4f 950 case 5: { // MIFARE TNP3XXX
951 // Says: I am a toy
952 response1[0] = 0x01;
953 response1[1] = 0x0f;
954 sak = 0x01;
955 } break;
81cd0474 956 default: {
957 Dbprintf("Error: unkown tagtype (%d)",tagType);
958 return;
959 } break;
960 }
961
962 // The second response contains the (mandatory) first 24 bits of the UID
c8b6da22 963 uint8_t response2[5] = {0x00};
81cd0474 964
965 // Check if the uid uses the (optional) part
c8b6da22 966 uint8_t response2a[5] = {0x00};
967
81cd0474 968 if (uid_2nd) {
969 response2[0] = 0x88;
970 num_to_bytes(uid_1st,3,response2+1);
971 num_to_bytes(uid_2nd,4,response2a);
972 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
973
974 // Configure the ATQA and SAK accordingly
975 response1[0] |= 0x40;
976 sak |= 0x04;
977 } else {
978 num_to_bytes(uid_1st,4,response2);
979 // Configure the ATQA and SAK accordingly
980 response1[0] &= 0xBF;
981 sak &= 0xFB;
982 }
983
984 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
985 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
986
987 // Prepare the mandatory SAK (for 4 and 7 byte UID)
c8b6da22 988 uint8_t response3[3] = {0x00};
81cd0474 989 response3[0] = sak;
990 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
991
992 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
c8b6da22 993 uint8_t response3a[3] = {0x00};
81cd0474 994 response3a[0] = sak & 0xFB;
995 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
996
254b70a4 997 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
6a1f2d82 998 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
999 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1000 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1001 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1002 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 1003 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1004
7bc95e2e 1005 #define TAG_RESPONSE_COUNT 7
1006 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1007 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1008 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1009 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1010 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1011 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1012 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1013 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1014 };
1015
1016 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1017 // Such a response is less time critical, so we can prepare them on the fly
1018 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1019 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1020 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1021 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1022 tag_response_info_t dynamic_response_info = {
1023 .response = dynamic_response_buffer,
1024 .response_n = 0,
1025 .modulation = dynamic_modulation_buffer,
1026 .modulation_n = 0
1027 };
ce02f6f9 1028
f71f4deb 1029 BigBuf_free_keep_EM();
1030
1031 // allocate buffers:
1032 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1033 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1034 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1035
1036 // clear trace
3000dc4e
MHS
1037 clear_trace();
1038 set_tracing(TRUE);
f71f4deb 1039
7bc95e2e 1040 // Prepare the responses of the anticollision phase
ce02f6f9 1041 // there will be not enough time to do this at the moment the reader sends it REQA
7bc95e2e 1042 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1043 prepare_allocated_tag_modulation(&responses[i]);
1044 }
15c4dc5a 1045
7bc95e2e 1046 int len = 0;
15c4dc5a 1047
1048 // To control where we are in the protocol
1049 int order = 0;
1050 int lastorder;
1051
1052 // Just to allow some checks
1053 int happened = 0;
1054 int happened2 = 0;
81cd0474 1055 int cmdsRecvd = 0;
15c4dc5a 1056
254b70a4 1057 // We need to listen to the high-frequency, peak-detected path.
7bc95e2e 1058 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
15c4dc5a 1059
254b70a4 1060 cmdsRecvd = 0;
7bc95e2e 1061 tag_response_info_t* p_response;
15c4dc5a 1062
254b70a4 1063 LED_A_ON();
1064 for(;;) {
7bc95e2e 1065 // Clean receive command buffer
1066
6a1f2d82 1067 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
ce02f6f9 1068 DbpString("Button press");
254b70a4 1069 break;
1070 }
7bc95e2e 1071
1072 p_response = NULL;
1073
254b70a4 1074 // Okay, look at the command now.
1075 lastorder = order;
1076 if(receivedCmd[0] == 0x26) { // Received a REQUEST
ce02f6f9 1077 p_response = &responses[0]; order = 1;
254b70a4 1078 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
ce02f6f9 1079 p_response = &responses[0]; order = 6;
254b70a4 1080 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
ce02f6f9 1081 p_response = &responses[1]; order = 2;
6a1f2d82 1082 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
ce02f6f9 1083 p_response = &responses[2]; order = 20;
254b70a4 1084 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
ce02f6f9 1085 p_response = &responses[3]; order = 3;
254b70a4 1086 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
ce02f6f9 1087 p_response = &responses[4]; order = 30;
254b70a4 1088 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
6a1f2d82 1089 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
7bc95e2e 1090 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
5f6d6c90 1091 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
7bc95e2e 1092 p_response = NULL;
254b70a4 1093 } else if(receivedCmd[0] == 0x50) { // Received a HALT
3fe4ff4f 1094
7bc95e2e 1095 if (tracing) {
6a1f2d82 1096 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1097 }
1098 p_response = NULL;
254b70a4 1099 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
ce02f6f9 1100 p_response = &responses[5]; order = 7;
254b70a4 1101 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
7bc95e2e 1102 if (tagType == 1 || tagType == 2) { // RATS not supported
1103 EmSend4bit(CARD_NACK_NA);
1104 p_response = NULL;
1105 } else {
1106 p_response = &responses[6]; order = 70;
1107 }
6a1f2d82 1108 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
7bc95e2e 1109 if (tracing) {
6a1f2d82 1110 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1111 }
1112 uint32_t nr = bytes_to_num(receivedCmd,4);
1113 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1114 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1115 } else {
1116 // Check for ISO 14443A-4 compliant commands, look at left nibble
1117 switch (receivedCmd[0]) {
1118
1119 case 0x0B:
1120 case 0x0A: { // IBlock (command)
1121 dynamic_response_info.response[0] = receivedCmd[0];
1122 dynamic_response_info.response[1] = 0x00;
1123 dynamic_response_info.response[2] = 0x90;
1124 dynamic_response_info.response[3] = 0x00;
1125 dynamic_response_info.response_n = 4;
1126 } break;
1127
1128 case 0x1A:
1129 case 0x1B: { // Chaining command
1130 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1131 dynamic_response_info.response_n = 2;
1132 } break;
1133
1134 case 0xaa:
1135 case 0xbb: {
1136 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1137 dynamic_response_info.response_n = 2;
1138 } break;
1139
1140 case 0xBA: { //
1141 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1142 dynamic_response_info.response_n = 2;
1143 } break;
1144
1145 case 0xCA:
1146 case 0xC2: { // Readers sends deselect command
1147 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1148 dynamic_response_info.response_n = 2;
1149 } break;
1150
1151 default: {
1152 // Never seen this command before
1153 if (tracing) {
6a1f2d82 1154 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1155 }
1156 Dbprintf("Received unknown command (len=%d):",len);
1157 Dbhexdump(len,receivedCmd,false);
1158 // Do not respond
1159 dynamic_response_info.response_n = 0;
1160 } break;
1161 }
ce02f6f9 1162
7bc95e2e 1163 if (dynamic_response_info.response_n > 0) {
1164 // Copy the CID from the reader query
1165 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1166
7bc95e2e 1167 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1168 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1169 dynamic_response_info.response_n += 2;
ce02f6f9 1170
7bc95e2e 1171 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1172 Dbprintf("Error preparing tag response");
1173 if (tracing) {
6a1f2d82 1174 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1175 }
1176 break;
1177 }
1178 p_response = &dynamic_response_info;
1179 }
81cd0474 1180 }
15c4dc5a 1181
1182 // Count number of wakeups received after a halt
1183 if(order == 6 && lastorder == 5) { happened++; }
1184
1185 // Count number of other messages after a halt
1186 if(order != 6 && lastorder == 5) { happened2++; }
1187
15c4dc5a 1188 if(cmdsRecvd > 999) {
1189 DbpString("1000 commands later...");
254b70a4 1190 break;
15c4dc5a 1191 }
ce02f6f9 1192 cmdsRecvd++;
1193
1194 if (p_response != NULL) {
7bc95e2e 1195 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1196 // do the tracing for the previous reader request and this tag answer:
6a1f2d82 1197 uint8_t par[MAX_PARITY_SIZE];
1198 GetParity(p_response->response, p_response->response_n, par);
3fe4ff4f 1199
7bc95e2e 1200 EmLogTrace(Uart.output,
1201 Uart.len,
1202 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1203 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1204 Uart.parity,
7bc95e2e 1205 p_response->response,
1206 p_response->response_n,
1207 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1208 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1209 par);
7bc95e2e 1210 }
1211
1212 if (!tracing) {
1213 Dbprintf("Trace Full. Simulation stopped.");
1214 break;
1215 }
1216 }
15c4dc5a 1217
1218 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1219 LED_A_OFF();
f71f4deb 1220 BigBuf_free_keep_EM();
15c4dc5a 1221}
1222
9492e0b0 1223
1224// prepare a delayed transfer. This simply shifts ToSend[] by a number
1225// of bits specified in the delay parameter.
1226void PrepareDelayedTransfer(uint16_t delay)
1227{
1228 uint8_t bitmask = 0;
1229 uint8_t bits_to_shift = 0;
1230 uint8_t bits_shifted = 0;
1231
1232 delay &= 0x07;
1233 if (delay) {
1234 for (uint16_t i = 0; i < delay; i++) {
1235 bitmask |= (0x01 << i);
1236 }
7bc95e2e 1237 ToSend[ToSendMax++] = 0x00;
9492e0b0 1238 for (uint16_t i = 0; i < ToSendMax; i++) {
1239 bits_to_shift = ToSend[i] & bitmask;
1240 ToSend[i] = ToSend[i] >> delay;
1241 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1242 bits_shifted = bits_to_shift;
1243 }
1244 }
1245}
1246
7bc95e2e 1247
1248//-------------------------------------------------------------------------------------
15c4dc5a 1249// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1250// Parameter timing:
7bc95e2e 1251// if NULL: transfer at next possible time, taking into account
1252// request guard time and frame delay time
1253// if == 0: transfer immediately and return time of transfer
9492e0b0 1254// if != 0: delay transfer until time specified
7bc95e2e 1255//-------------------------------------------------------------------------------------
6a1f2d82 1256static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
15c4dc5a 1257{
7bc95e2e 1258
9492e0b0 1259 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1260
7bc95e2e 1261 uint32_t ThisTransferTime = 0;
e30c654b 1262
9492e0b0 1263 if (timing) {
1264 if(*timing == 0) { // Measure time
7bc95e2e 1265 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
9492e0b0 1266 } else {
1267 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1268 }
7bc95e2e 1269 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1270 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1271 LastTimeProxToAirStart = *timing;
1272 } else {
1273 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1274 while(GetCountSspClk() < ThisTransferTime);
1275 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1276 }
1277
7bc95e2e 1278 // clear TXRDY
1279 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1280
7bc95e2e 1281 uint16_t c = 0;
9492e0b0 1282 for(;;) {
1283 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1284 AT91C_BASE_SSC->SSC_THR = cmd[c];
1285 c++;
1286 if(c >= len) {
1287 break;
1288 }
1289 }
1290 }
7bc95e2e 1291
1292 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
15c4dc5a 1293}
1294
7bc95e2e 1295
15c4dc5a 1296//-----------------------------------------------------------------------------
195af472 1297// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1298//-----------------------------------------------------------------------------
6a1f2d82 1299void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
15c4dc5a 1300{
7bc95e2e 1301 int i, j;
1302 int last;
1303 uint8_t b;
e30c654b 1304
7bc95e2e 1305 ToSendReset();
e30c654b 1306
7bc95e2e 1307 // Start of Communication (Seq. Z)
1308 ToSend[++ToSendMax] = SEC_Z;
1309 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1310 last = 0;
1311
1312 size_t bytecount = nbytes(bits);
1313 // Generate send structure for the data bits
1314 for (i = 0; i < bytecount; i++) {
1315 // Get the current byte to send
1316 b = cmd[i];
1317 size_t bitsleft = MIN((bits-(i*8)),8);
1318
1319 for (j = 0; j < bitsleft; j++) {
1320 if (b & 1) {
1321 // Sequence X
1322 ToSend[++ToSendMax] = SEC_X;
1323 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1324 last = 1;
1325 } else {
1326 if (last == 0) {
1327 // Sequence Z
1328 ToSend[++ToSendMax] = SEC_Z;
1329 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1330 } else {
1331 // Sequence Y
1332 ToSend[++ToSendMax] = SEC_Y;
1333 last = 0;
1334 }
1335 }
1336 b >>= 1;
1337 }
1338
6a1f2d82 1339 // Only transmit parity bit if we transmitted a complete byte
7bc95e2e 1340 if (j == 8) {
1341 // Get the parity bit
6a1f2d82 1342 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1343 // Sequence X
1344 ToSend[++ToSendMax] = SEC_X;
1345 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1346 last = 1;
1347 } else {
1348 if (last == 0) {
1349 // Sequence Z
1350 ToSend[++ToSendMax] = SEC_Z;
1351 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1352 } else {
1353 // Sequence Y
1354 ToSend[++ToSendMax] = SEC_Y;
1355 last = 0;
1356 }
1357 }
1358 }
1359 }
e30c654b 1360
7bc95e2e 1361 // End of Communication: Logic 0 followed by Sequence Y
1362 if (last == 0) {
1363 // Sequence Z
1364 ToSend[++ToSendMax] = SEC_Z;
1365 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1366 } else {
1367 // Sequence Y
1368 ToSend[++ToSendMax] = SEC_Y;
1369 last = 0;
1370 }
1371 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1372
7bc95e2e 1373 // Convert to length of command:
1374 ToSendMax++;
15c4dc5a 1375}
1376
195af472 1377//-----------------------------------------------------------------------------
1378// Prepare reader command to send to FPGA
1379//-----------------------------------------------------------------------------
6a1f2d82 1380void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
195af472 1381{
6a1f2d82 1382 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
195af472 1383}
1384
0c8d25eb 1385
9ca155ba
M
1386//-----------------------------------------------------------------------------
1387// Wait for commands from reader
1388// Stop when button is pressed (return 1) or field was gone (return 2)
1389// Or return 0 when command is captured
1390//-----------------------------------------------------------------------------
6a1f2d82 1391static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
9ca155ba
M
1392{
1393 *len = 0;
1394
1395 uint32_t timer = 0, vtime = 0;
1396 int analogCnt = 0;
1397 int analogAVG = 0;
1398
1399 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1400 // only, since we are receiving, not transmitting).
1401 // Signal field is off with the appropriate LED
1402 LED_D_OFF();
1403 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1404
1405 // Set ADC to read field strength
1406 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1407 AT91C_BASE_ADC->ADC_MR =
0c8d25eb 1408 ADC_MODE_PRESCALE(63) |
1409 ADC_MODE_STARTUP_TIME(1) |
1410 ADC_MODE_SAMPLE_HOLD_TIME(15);
9ca155ba
M
1411 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1412 // start ADC
1413 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1414
1415 // Now run a 'software UART' on the stream of incoming samples.
6a1f2d82 1416 UartInit(received, parity);
7bc95e2e 1417
1418 // Clear RXRDY:
1419 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1420
9ca155ba
M
1421 for(;;) {
1422 WDT_HIT();
1423
1424 if (BUTTON_PRESS()) return 1;
1425
1426 // test if the field exists
1427 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1428 analogCnt++;
1429 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1430 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1431 if (analogCnt >= 32) {
0c8d25eb 1432 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
9ca155ba
M
1433 vtime = GetTickCount();
1434 if (!timer) timer = vtime;
1435 // 50ms no field --> card to idle state
1436 if (vtime - timer > 50) return 2;
1437 } else
1438 if (timer) timer = 0;
1439 analogCnt = 0;
1440 analogAVG = 0;
1441 }
1442 }
7bc95e2e 1443
9ca155ba 1444 // receive and test the miller decoding
7bc95e2e 1445 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1446 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1447 if(MillerDecoding(b, 0)) {
1448 *len = Uart.len;
9ca155ba
M
1449 return 0;
1450 }
7bc95e2e 1451 }
1452
9ca155ba
M
1453 }
1454}
1455
9ca155ba 1456
6a1f2d82 1457static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
7bc95e2e 1458{
1459 uint8_t b;
1460 uint16_t i = 0;
1461 uint32_t ThisTransferTime;
1462
9ca155ba
M
1463 // Modulate Manchester
1464 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1465
1466 // include correction bit if necessary
1467 if (Uart.parityBits & 0x01) {
1468 correctionNeeded = TRUE;
1469 }
1470 if(correctionNeeded) {
9ca155ba
M
1471 // 1236, so correction bit needed
1472 i = 0;
7bc95e2e 1473 } else {
1474 i = 1;
9ca155ba 1475 }
7bc95e2e 1476
d714d3ef 1477 // clear receiving shift register and holding register
7bc95e2e 1478 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1479 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1480 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1481 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
9ca155ba 1482
7bc95e2e 1483 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1484 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1485 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1486 if (AT91C_BASE_SSC->SSC_RHR) break;
1487 }
1488
1489 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1490
1491 // Clear TXRDY:
1492 AT91C_BASE_SSC->SSC_THR = SEC_F;
1493
9ca155ba 1494 // send cycle
bb42a03e 1495 for(; i < respLen; ) {
9ca155ba 1496 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1497 AT91C_BASE_SSC->SSC_THR = resp[i++];
1498 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1499 }
7bc95e2e 1500
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1501 if(BUTTON_PRESS()) {
1502 break;
1503 }
1504 }
1505
7bc95e2e 1506 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
0c8d25eb 1507 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
1508 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
7bc95e2e 1509 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1510 AT91C_BASE_SSC->SSC_THR = SEC_F;
1511 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1512 i++;
1513 }
1514 }
0c8d25eb 1515
7bc95e2e 1516 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1517
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1518 return 0;
1519}
1520
7bc95e2e 1521int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1522 Code4bitAnswerAsTag(resp);
0a39986e 1523 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1524 // do the tracing for the previous reader request and this tag answer:
6a1f2d82 1525 uint8_t par[1];
1526 GetParity(&resp, 1, par);
7bc95e2e 1527 EmLogTrace(Uart.output,
1528 Uart.len,
1529 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1530 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1531 Uart.parity,
7bc95e2e 1532 &resp,
1533 1,
1534 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1535 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1536 par);
0a39986e 1537 return res;
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M
1538}
1539
8f51ddb0 1540int EmSend4bit(uint8_t resp){
7bc95e2e 1541 return EmSend4bitEx(resp, false);
8f51ddb0
M
1542}
1543
6a1f2d82 1544int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
7bc95e2e 1545 CodeIso14443aAsTagPar(resp, respLen, par);
8f51ddb0 1546 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1547 // do the tracing for the previous reader request and this tag answer:
1548 EmLogTrace(Uart.output,
1549 Uart.len,
1550 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1551 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1552 Uart.parity,
7bc95e2e 1553 resp,
1554 respLen,
1555 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1556 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1557 par);
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1558 return res;
1559}
1560
6a1f2d82 1561int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1562 uint8_t par[MAX_PARITY_SIZE];
1563 GetParity(resp, respLen, par);
1564 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
8f51ddb0
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1565}
1566
6a1f2d82 1567int EmSendCmd(uint8_t *resp, uint16_t respLen){
1568 uint8_t par[MAX_PARITY_SIZE];
1569 GetParity(resp, respLen, par);
1570 return EmSendCmdExPar(resp, respLen, false, par);
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M
1571}
1572
6a1f2d82 1573int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1574 return EmSendCmdExPar(resp, respLen, false, par);
1575}
1576
6a1f2d82 1577bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1578 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
7bc95e2e 1579{
1580 if (tracing) {
1581 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1582 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1583 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1584 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1585 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1586 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1587 reader_EndTime = tag_StartTime - exact_fdt;
1588 reader_StartTime = reader_EndTime - reader_modlen;
6a1f2d82 1589 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
7bc95e2e 1590 return FALSE;
6a1f2d82 1591 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
7bc95e2e 1592 } else {
1593 return TRUE;
1594 }
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1595}
1596
15c4dc5a 1597//-----------------------------------------------------------------------------
1598// Wait a certain time for tag response
1599// If a response is captured return TRUE
e691fc45 1600// If it takes too long return FALSE
15c4dc5a 1601//-----------------------------------------------------------------------------
6a1f2d82 1602static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
15c4dc5a 1603{
52bfb955 1604 uint32_t c;
e691fc45 1605
15c4dc5a 1606 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1607 // only, since we are receiving, not transmitting).
1608 // Signal field is on with the appropriate LED
1609 LED_D_ON();
1610 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1c611bbd 1611
534983d7 1612 // Now get the answer from the card
6a1f2d82 1613 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 1614
7bc95e2e 1615 // clear RXRDY:
1616 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1617
15c4dc5a 1618 c = 0;
1619 for(;;) {
534983d7 1620 WDT_HIT();
15c4dc5a 1621
534983d7 1622 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1623 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1624 if(ManchesterDecoding(b, offset, 0)) {
1625 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
15c4dc5a 1626 return TRUE;
19a700a8 1627 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
7bc95e2e 1628 return FALSE;
15c4dc5a 1629 }
534983d7 1630 }
1631 }
15c4dc5a 1632}
1633
6a1f2d82 1634void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
15c4dc5a 1635{
6a1f2d82 1636 CodeIso14443aBitsAsReaderPar(frame, bits, par);
dfc3c505 1637
7bc95e2e 1638 // Send command to tag
1639 TransmitFor14443a(ToSend, ToSendMax, timing);
1640 if(trigger)
1641 LED_A_ON();
dfc3c505 1642
7bc95e2e 1643 // Log reader command in trace buffer
1644 if (tracing) {
6a1f2d82 1645 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
7bc95e2e 1646 }
15c4dc5a 1647}
1648
6a1f2d82 1649void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
dfc3c505 1650{
6a1f2d82 1651 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1652}
15c4dc5a 1653
6a1f2d82 1654void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
e691fc45 1655{
1656 // Generate parity and redirect
6a1f2d82 1657 uint8_t par[MAX_PARITY_SIZE];
1658 GetParity(frame, len/8, par);
1659 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1660}
1661
6a1f2d82 1662void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
15c4dc5a 1663{
1664 // Generate parity and redirect
6a1f2d82 1665 uint8_t par[MAX_PARITY_SIZE];
1666 GetParity(frame, len, par);
1667 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1668}
1669
6a1f2d82 1670int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
e691fc45 1671{
6a1f2d82 1672 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
7bc95e2e 1673 if (tracing) {
6a1f2d82 1674 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
7bc95e2e 1675 }
e691fc45 1676 return Demod.len;
1677}
1678
6a1f2d82 1679int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
15c4dc5a 1680{
6a1f2d82 1681 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
7bc95e2e 1682 if (tracing) {
6a1f2d82 1683 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
7bc95e2e 1684 }
e691fc45 1685 return Demod.len;
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1686}
1687
e691fc45 1688/* performs iso14443a anticollision procedure
534983d7 1689 * fills the uid pointer unless NULL
1690 * fills resp_data unless NULL */
6a1f2d82 1691int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1692 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1693 uint8_t sel_all[] = { 0x93,0x20 };
1694 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1695 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
f71f4deb 1696 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1697 uint8_t resp_par[MAX_PARITY_SIZE];
6a1f2d82 1698 byte_t uid_resp[4];
1699 size_t uid_resp_len;
1700
1701 uint8_t sak = 0x04; // cascade uid
1702 int cascade_level = 0;
1703 int len;
1704
1705 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
9492e0b0 1706 ReaderTransmitBitsPar(wupa,7,0, NULL);
7bc95e2e 1707
6a1f2d82 1708 // Receive the ATQA
1709 if(!ReaderReceive(resp, resp_par)) return 0;
6a1f2d82 1710
1711 if(p_hi14a_card) {
1712 memcpy(p_hi14a_card->atqa, resp, 2);
1713 p_hi14a_card->uidlen = 0;
1714 memset(p_hi14a_card->uid,0,10);
1715 }
5f6d6c90 1716
6a1f2d82 1717 // clear uid
1718 if (uid_ptr) {
1719 memset(uid_ptr,0,10);
1720 }
79a73ab2 1721
ee1eadee 1722 // check for proprietary anticollision:
1723 if ((resp[0] & 0x1F) == 0) {
1724 return 3;
1725 }
1726
6a1f2d82 1727 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1728 // which case we need to make a cascade 2 request and select - this is a long UID
1729 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1730 for(; sak & 0x04; cascade_level++) {
1731 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1732 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1733
1734 // SELECT_ALL
1735 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1736 if (!ReaderReceive(resp, resp_par)) return 0;
1737
1738 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1739 memset(uid_resp, 0, 4);
1740 uint16_t uid_resp_bits = 0;
1741 uint16_t collision_answer_offset = 0;
1742 // anti-collision-loop:
1743 while (Demod.collisionPos) {
1744 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1745 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1746 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
758f1fd1 1747 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
6a1f2d82 1748 }
1749 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1750 uid_resp_bits++;
1751 // construct anticollosion command:
1752 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1753 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1754 sel_uid[2+i] = uid_resp[i];
1755 }
1756 collision_answer_offset = uid_resp_bits%8;
1757 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1758 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
e691fc45 1759 }
6a1f2d82 1760 // finally, add the last bits and BCC of the UID
1761 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1762 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1763 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
e691fc45 1764 }
e691fc45 1765
6a1f2d82 1766 } else { // no collision, use the response to SELECT_ALL as current uid
1767 memcpy(uid_resp, resp, 4);
1768 }
1769 uid_resp_len = 4;
5f6d6c90 1770
6a1f2d82 1771 // calculate crypto UID. Always use last 4 Bytes.
1772 if(cuid_ptr) {
1773 *cuid_ptr = bytes_to_num(uid_resp, 4);
1774 }
e30c654b 1775
6a1f2d82 1776 // Construct SELECT UID command
1777 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1778 memcpy(sel_uid+2, uid_resp, 4); // the UID
1779 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1780 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1781 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1782
1783 // Receive the SAK
1784 if (!ReaderReceive(resp, resp_par)) return 0;
1785 sak = resp[0];
1786
52ab55ab 1787 // Test if more parts of the uid are coming
6a1f2d82 1788 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1789 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1790 // http://www.nxp.com/documents/application_note/AN10927.pdf
6a1f2d82 1791 uid_resp[0] = uid_resp[1];
1792 uid_resp[1] = uid_resp[2];
1793 uid_resp[2] = uid_resp[3];
1794
1795 uid_resp_len = 3;
1796 }
5f6d6c90 1797
6a1f2d82 1798 if(uid_ptr) {
1799 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1800 }
5f6d6c90 1801
6a1f2d82 1802 if(p_hi14a_card) {
1803 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1804 p_hi14a_card->uidlen += uid_resp_len;
1805 }
1806 }
79a73ab2 1807
6a1f2d82 1808 if(p_hi14a_card) {
1809 p_hi14a_card->sak = sak;
1810 p_hi14a_card->ats_len = 0;
1811 }
534983d7 1812
3fe4ff4f 1813 // non iso14443a compliant tag
1814 if( (sak & 0x20) == 0) return 2;
534983d7 1815
6a1f2d82 1816 // Request for answer to select
1817 AppendCrc14443a(rats, 2);
1818 ReaderTransmit(rats, sizeof(rats), NULL);
1c611bbd 1819
6a1f2d82 1820 if (!(len = ReaderReceive(resp, resp_par))) return 0;
5191b3d1 1821
3fe4ff4f 1822
6a1f2d82 1823 if(p_hi14a_card) {
1824 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1825 p_hi14a_card->ats_len = len;
1826 }
5f6d6c90 1827
6a1f2d82 1828 // reset the PCB block number
1829 iso14_pcb_blocknum = 0;
19a700a8 1830
1831 // set default timeout based on ATS
1832 iso14a_set_ATS_timeout(resp);
1833
6a1f2d82 1834 return 1;
7e758047 1835}
15c4dc5a 1836
7bc95e2e 1837void iso14443a_setup(uint8_t fpga_minor_mode) {
7cc204bf 1838 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 1839 // Set up the synchronous serial port
1840 FpgaSetupSsc();
7bc95e2e 1841 // connect Demodulated Signal to ADC:
7e758047 1842 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
e30c654b 1843
7e758047 1844 // Signal field is on with the appropriate LED
7bc95e2e 1845 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1846 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1847 LED_D_ON();
1848 } else {
1849 LED_D_OFF();
1850 }
1851 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
534983d7 1852
7bc95e2e 1853 // Start the timer
1854 StartCountSspClk();
1855
1856 DemodReset();
1857 UartReset();
1858 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1859 iso14a_set_timeout(1050); // 10ms default
7e758047 1860}
15c4dc5a 1861
6a1f2d82 1862int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1863 uint8_t parity[MAX_PARITY_SIZE];
534983d7 1864 uint8_t real_cmd[cmd_len+4];
1865 real_cmd[0] = 0x0a; //I-Block
b0127e65 1866 // put block number into the PCB
1867 real_cmd[0] |= iso14_pcb_blocknum;
534983d7 1868 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1869 memcpy(real_cmd+2, cmd, cmd_len);
1870 AppendCrc14443a(real_cmd,cmd_len+2);
1871
9492e0b0 1872 ReaderTransmit(real_cmd, cmd_len+4, NULL);
6a1f2d82 1873 size_t len = ReaderReceive(data, parity);
1874 uint8_t *data_bytes = (uint8_t *) data;
b0127e65 1875 if (!len)
1876 return 0; //DATA LINK ERROR
1877 // if we received an I- or R(ACK)-Block with a block number equal to the
1878 // current block number, toggle the current block number
1879 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1880 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1881 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1882 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1883 {
1884 iso14_pcb_blocknum ^= 1;
1885 }
1886
534983d7 1887 return len;
1888}
1889
7e758047 1890//-----------------------------------------------------------------------------
1891// Read an ISO 14443a tag. Send out commands and store answers.
1892//
1893//-----------------------------------------------------------------------------
7bc95e2e 1894void ReaderIso14443a(UsbCommand *c)
7e758047 1895{
534983d7 1896 iso14a_command_t param = c->arg[0];
7bc95e2e 1897 uint8_t *cmd = c->d.asBytes;
04bc1c66 1898 size_t len = c->arg[1] & 0xffff;
1899 size_t lenbits = c->arg[1] >> 16;
1900 uint32_t timeout = c->arg[2];
9492e0b0 1901 uint32_t arg0 = 0;
1902 byte_t buf[USB_CMD_DATA_SIZE];
6a1f2d82 1903 uint8_t par[MAX_PARITY_SIZE];
902cb3c0 1904
5f6d6c90 1905 if(param & ISO14A_CONNECT) {
3000dc4e 1906 clear_trace();
5f6d6c90 1907 }
e691fc45 1908
3000dc4e 1909 set_tracing(TRUE);
e30c654b 1910
79a73ab2 1911 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 1912 iso14a_set_trigger(TRUE);
9492e0b0 1913 }
15c4dc5a 1914
534983d7 1915 if(param & ISO14A_CONNECT) {
7bc95e2e 1916 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 1917 if(!(param & ISO14A_NO_SELECT)) {
1918 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1919 arg0 = iso14443a_select_card(NULL,card,NULL);
1920 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1921 }
534983d7 1922 }
e30c654b 1923
534983d7 1924 if(param & ISO14A_SET_TIMEOUT) {
04bc1c66 1925 iso14a_set_timeout(timeout);
534983d7 1926 }
e30c654b 1927
534983d7 1928 if(param & ISO14A_APDU) {
902cb3c0 1929 arg0 = iso14_apdu(cmd, len, buf);
79a73ab2 1930 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 1931 }
e30c654b 1932
534983d7 1933 if(param & ISO14A_RAW) {
1934 if(param & ISO14A_APPEND_CRC) {
1935 AppendCrc14443a(cmd,len);
1936 len += 2;
c7324bef 1937 if (lenbits) lenbits += 16;
15c4dc5a 1938 }
5f6d6c90 1939 if(lenbits>0) {
6a1f2d82 1940 GetParity(cmd, lenbits/8, par);
1941 ReaderTransmitBitsPar(cmd, lenbits, par, NULL);
5f6d6c90 1942 } else {
1943 ReaderTransmit(cmd,len, NULL);
1944 }
6a1f2d82 1945 arg0 = ReaderReceive(buf, par);
9492e0b0 1946 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 1947 }
15c4dc5a 1948
79a73ab2 1949 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 1950 iso14a_set_trigger(FALSE);
9492e0b0 1951 }
15c4dc5a 1952
79a73ab2 1953 if(param & ISO14A_NO_DISCONNECT) {
534983d7 1954 return;
9492e0b0 1955 }
15c4dc5a 1956
15c4dc5a 1957 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1958 LEDsoff();
15c4dc5a 1959}
b0127e65 1960
1c611bbd 1961
1c611bbd 1962// Determine the distance between two nonces.
1963// Assume that the difference is small, but we don't know which is first.
1964// Therefore try in alternating directions.
1965int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
1966
1967 uint16_t i;
1968 uint32_t nttmp1, nttmp2;
e772353f 1969
1c611bbd 1970 if (nt1 == nt2) return 0;
1971
1972 nttmp1 = nt1;
1973 nttmp2 = nt2;
1974
1975 for (i = 1; i < 32768; i++) {
1976 nttmp1 = prng_successor(nttmp1, 1);
1977 if (nttmp1 == nt2) return i;
1978 nttmp2 = prng_successor(nttmp2, 1);
1979 if (nttmp2 == nt1) return -i;
1980 }
1981
1982 return(-99999); // either nt1 or nt2 are invalid nonces
e772353f 1983}
1984
e772353f 1985
1c611bbd 1986//-----------------------------------------------------------------------------
1987// Recover several bits of the cypher stream. This implements (first stages of)
1988// the algorithm described in "The Dark Side of Security by Obscurity and
1989// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
1990// (article by Nicolas T. Courtois, 2009)
1991//-----------------------------------------------------------------------------
1992void ReaderMifare(bool first_try)
1993{
1994 // Mifare AUTH
1995 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
1996 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
1997 static uint8_t mf_nr_ar3;
e772353f 1998
f71f4deb 1999 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
2000 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
7bc95e2e 2001
f71f4deb 2002 // free eventually allocated BigBuf memory. We want all for tracing.
2003 BigBuf_free();
2004
3000dc4e
MHS
2005 clear_trace();
2006 set_tracing(TRUE);
e772353f 2007
1c611bbd 2008 byte_t nt_diff = 0;
6a1f2d82 2009 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
1c611bbd 2010 static byte_t par_low = 0;
2011 bool led_on = TRUE;
ca4714cd 2012 uint8_t uid[10] ={0};
1c611bbd 2013 uint32_t cuid;
e772353f 2014
6a1f2d82 2015 uint32_t nt = 0;
2ed270a8 2016 uint32_t previous_nt = 0;
1c611bbd 2017 static uint32_t nt_attacked = 0;
3fe4ff4f 2018 byte_t par_list[8] = {0x00};
2019 byte_t ks_list[8] = {0x00};
e772353f 2020
1c611bbd 2021 static uint32_t sync_time;
2022 static uint32_t sync_cycles;
2023 int catch_up_cycles = 0;
2024 int last_catch_up = 0;
2025 uint16_t consecutive_resyncs = 0;
2026 int isOK = 0;
e772353f 2027
1c611bbd 2028 if (first_try) {
1c611bbd 2029 mf_nr_ar3 = 0;
7bc95e2e 2030 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2031 sync_time = GetCountSspClk() & 0xfffffff8;
1c611bbd 2032 sync_cycles = 65536; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
2033 nt_attacked = 0;
2034 nt = 0;
6a1f2d82 2035 par[0] = 0;
1c611bbd 2036 }
2037 else {
2038 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
1c611bbd 2039 mf_nr_ar3++;
2040 mf_nr_ar[3] = mf_nr_ar3;
6a1f2d82 2041 par[0] = par_low;
1c611bbd 2042 }
e30c654b 2043
15c4dc5a 2044 LED_A_ON();
2045 LED_B_OFF();
2046 LED_C_OFF();
1c611bbd 2047
7bc95e2e 2048
1c611bbd 2049 for(uint16_t i = 0; TRUE; i++) {
2050
2051 WDT_HIT();
e30c654b 2052
1c611bbd 2053 // Test if the action was cancelled
2054 if(BUTTON_PRESS()) {
2055 break;
2056 }
2057
2058 LED_C_ON();
e30c654b 2059
1c611bbd 2060 if(!iso14443a_select_card(uid, NULL, &cuid)) {
9492e0b0 2061 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
1c611bbd 2062 continue;
2063 }
2064
9492e0b0 2065 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
1c611bbd 2066 catch_up_cycles = 0;
2067
2068 // if we missed the sync time already, advance to the next nonce repeat
7bc95e2e 2069 while(GetCountSspClk() > sync_time) {
9492e0b0 2070 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
1c611bbd 2071 }
e30c654b 2072
9492e0b0 2073 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2074 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
f89c7050 2075
1c611bbd 2076 // Receive the (4 Byte) "random" nonce
6a1f2d82 2077 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2078 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
1c611bbd 2079 continue;
2080 }
2081
1c611bbd 2082 previous_nt = nt;
2083 nt = bytes_to_num(receivedAnswer, 4);
2084
2085 // Transmit reader nonce with fake par
9492e0b0 2086 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
1c611bbd 2087
2088 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2089 int nt_distance = dist_nt(previous_nt, nt);
2090 if (nt_distance == 0) {
2091 nt_attacked = nt;
2092 }
2093 else {
2094 if (nt_distance == -99999) { // invalid nonce received, try again
2095 continue;
2096 }
2097 sync_cycles = (sync_cycles - nt_distance);
9492e0b0 2098 if (MF_DBGLEVEL >= 3) Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles);
1c611bbd 2099 continue;
2100 }
2101 }
2102
2103 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2104 catch_up_cycles = -dist_nt(nt_attacked, nt);
2105 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2106 catch_up_cycles = 0;
2107 continue;
2108 }
2109 if (catch_up_cycles == last_catch_up) {
2110 consecutive_resyncs++;
2111 }
2112 else {
2113 last_catch_up = catch_up_cycles;
2114 consecutive_resyncs = 0;
2115 }
2116 if (consecutive_resyncs < 3) {
9492e0b0 2117 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
1c611bbd 2118 }
2119 else {
2120 sync_cycles = sync_cycles + catch_up_cycles;
9492e0b0 2121 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
1c611bbd 2122 }
2123 continue;
2124 }
2125
2126 consecutive_resyncs = 0;
2127
2128 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
6a1f2d82 2129 if (ReaderReceive(receivedAnswer, receivedAnswerPar))
1c611bbd 2130 {
9492e0b0 2131 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
1c611bbd 2132
2133 if (nt_diff == 0)
2134 {
6a1f2d82 2135 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2136 }
2137
2138 led_on = !led_on;
2139 if(led_on) LED_B_ON(); else LED_B_OFF();
2140
6a1f2d82 2141 par_list[nt_diff] = SwapBits(par[0], 8);
1c611bbd 2142 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2143
2144 // Test if the information is complete
2145 if (nt_diff == 0x07) {
2146 isOK = 1;
2147 break;
2148 }
2149
2150 nt_diff = (nt_diff + 1) & 0x07;
2151 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
6a1f2d82 2152 par[0] = par_low;
1c611bbd 2153 } else {
2154 if (nt_diff == 0 && first_try)
2155 {
6a1f2d82 2156 par[0]++;
1c611bbd 2157 } else {
6a1f2d82 2158 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2159 }
2160 }
2161 }
2162
1c611bbd 2163
2164 mf_nr_ar[3] &= 0x1F;
2165
2166 byte_t buf[28];
2167 memcpy(buf + 0, uid, 4);
2168 num_to_bytes(nt, 4, buf + 4);
2169 memcpy(buf + 8, par_list, 8);
2170 memcpy(buf + 16, ks_list, 8);
2171 memcpy(buf + 24, mf_nr_ar, 4);
2172
2173 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2174
2175 // Thats it...
2176 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2177 LEDsoff();
7bc95e2e 2178
3000dc4e 2179 set_tracing(FALSE);
20f9a2a1 2180}
1c611bbd 2181
d2f487af 2182/**
2183 *MIFARE 1K simulate.
2184 *
2185 *@param flags :
2186 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2187 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2188 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2189 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2190 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2191 */
2192void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
20f9a2a1 2193{
50193c1e 2194 int cardSTATE = MFEMUL_NOFIELD;
8556b852 2195 int _7BUID = 0;
9ca155ba 2196 int vHf = 0; // in mV
8f51ddb0 2197 int res;
0a39986e
M
2198 uint32_t selTimer = 0;
2199 uint32_t authTimer = 0;
6a1f2d82 2200 uint16_t len = 0;
8f51ddb0 2201 uint8_t cardWRBL = 0;
9ca155ba
M
2202 uint8_t cardAUTHSC = 0;
2203 uint8_t cardAUTHKEY = 0xff; // no authentication
51969283 2204 uint32_t cardRr = 0;
9ca155ba 2205 uint32_t cuid = 0;
d2f487af 2206 //uint32_t rn_enc = 0;
51969283 2207 uint32_t ans = 0;
0014cb46
M
2208 uint32_t cardINTREG = 0;
2209 uint8_t cardINTBLOCK = 0;
9ca155ba
M
2210 struct Crypto1State mpcs = {0, 0};
2211 struct Crypto1State *pcs;
2212 pcs = &mpcs;
d2f487af 2213 uint32_t numReads = 0;//Counts numer of times reader read a block
f71f4deb 2214 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2215 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE];
2216 uint8_t response[MAX_MIFARE_FRAME_SIZE];
2217 uint8_t response_par[MAX_MIFARE_PARITY_SIZE];
9ca155ba 2218
d2f487af 2219 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2220 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2221 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2222 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2223 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
9ca155ba 2224
d2f487af 2225 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2226 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
7bc95e2e 2227
d2f487af 2228 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2229 // This can be used in a reader-only attack.
2230 // (it can also be retrieved via 'hf 14a list', but hey...
2231 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0};
2232 uint8_t ar_nr_collected = 0;
0014cb46 2233
f71f4deb 2234 // free eventually allocated BigBuf memory but keep Emulator Memory
2235 BigBuf_free_keep_EM();
0c8d25eb 2236
0a39986e 2237 // clear trace
3000dc4e
MHS
2238 clear_trace();
2239 set_tracing(TRUE);
51969283 2240
7bc95e2e 2241 // Authenticate response - nonce
51969283 2242 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
7bc95e2e 2243
d2f487af 2244 //-- Determine the UID
2245 // Can be set from emulator memory, incoming data
2246 // and can be 7 or 4 bytes long
7bc95e2e 2247 if (flags & FLAG_4B_UID_IN_DATA)
d2f487af 2248 {
2249 // 4B uid comes from data-portion of packet
2250 memcpy(rUIDBCC1,datain,4);
8556b852 2251 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
8556b852 2252
7bc95e2e 2253 } else if (flags & FLAG_7B_UID_IN_DATA) {
d2f487af 2254 // 7B uid comes from data-portion of packet
2255 memcpy(&rUIDBCC1[1],datain,3);
2256 memcpy(rUIDBCC2, datain+3, 4);
2257 _7BUID = true;
7bc95e2e 2258 } else {
d2f487af 2259 // get UID from emul memory
2260 emlGetMemBt(receivedCmd, 7, 1);
2261 _7BUID = !(receivedCmd[0] == 0x00);
2262 if (!_7BUID) { // ---------- 4BUID
2263 emlGetMemBt(rUIDBCC1, 0, 4);
2264 } else { // ---------- 7BUID
2265 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2266 emlGetMemBt(rUIDBCC2, 3, 4);
2267 }
2268 }
7bc95e2e 2269
d2f487af 2270 /*
2271 * Regardless of what method was used to set the UID, set fifth byte and modify
2272 * the ATQA for 4 or 7-byte UID
2273 */
d2f487af 2274 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
7bc95e2e 2275 if (_7BUID) {
d2f487af 2276 rATQA[0] = 0x44;
8556b852 2277 rUIDBCC1[0] = 0x88;
8556b852
M
2278 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2279 }
2280
9ca155ba 2281 // We need to listen to the high-frequency, peak-detected path.
7bc95e2e 2282 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
9ca155ba 2283
9ca155ba 2284
d2f487af 2285 if (MF_DBGLEVEL >= 1) {
2286 if (!_7BUID) {
b03c0f2d 2287 Dbprintf("4B UID: %02x%02x%02x%02x",
2288 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
7bc95e2e 2289 } else {
b03c0f2d 2290 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2291 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2292 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
d2f487af 2293 }
2294 }
7bc95e2e 2295
2296 bool finished = FALSE;
d2f487af 2297 while (!BUTTON_PRESS() && !finished) {
9ca155ba 2298 WDT_HIT();
9ca155ba
M
2299
2300 // find reader field
9ca155ba 2301 if (cardSTATE == MFEMUL_NOFIELD) {
0c8d25eb 2302 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
9ca155ba 2303 if (vHf > MF_MINFIELDV) {
0014cb46 2304 cardSTATE_TO_IDLE();
9ca155ba
M
2305 LED_A_ON();
2306 }
2307 }
d2f487af 2308 if(cardSTATE == MFEMUL_NOFIELD) continue;
9ca155ba 2309
d2f487af 2310 //Now, get data
2311
6a1f2d82 2312 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
d2f487af 2313 if (res == 2) { //Field is off!
2314 cardSTATE = MFEMUL_NOFIELD;
2315 LEDsoff();
2316 continue;
7bc95e2e 2317 } else if (res == 1) {
2318 break; //return value 1 means button press
2319 }
2320
d2f487af 2321 // REQ or WUP request in ANY state and WUP in HALTED state
2322 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2323 selTimer = GetTickCount();
2324 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2325 cardSTATE = MFEMUL_SELECT1;
2326
2327 // init crypto block
2328 LED_B_OFF();
2329 LED_C_OFF();
2330 crypto1_destroy(pcs);
2331 cardAUTHKEY = 0xff;
2332 continue;
0a39986e 2333 }
7bc95e2e 2334
50193c1e 2335 switch (cardSTATE) {
d2f487af 2336 case MFEMUL_NOFIELD:
2337 case MFEMUL_HALTED:
50193c1e 2338 case MFEMUL_IDLE:{
6a1f2d82 2339 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
50193c1e
M
2340 break;
2341 }
2342 case MFEMUL_SELECT1:{
9ca155ba
M
2343 // select all
2344 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
d2f487af 2345 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
9ca155ba 2346 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
0014cb46 2347 break;
9ca155ba
M
2348 }
2349
d2f487af 2350 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2351 {
2352 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2353 }
9ca155ba 2354 // select card
0a39986e
M
2355 if (len == 9 &&
2356 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
bfb6a143 2357 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
9ca155ba 2358 cuid = bytes_to_num(rUIDBCC1, 4);
8556b852
M
2359 if (!_7BUID) {
2360 cardSTATE = MFEMUL_WORK;
0014cb46
M
2361 LED_B_ON();
2362 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2363 break;
8556b852
M
2364 } else {
2365 cardSTATE = MFEMUL_SELECT2;
8556b852 2366 }
9ca155ba 2367 }
50193c1e
M
2368 break;
2369 }
d2f487af 2370 case MFEMUL_AUTH1:{
2371 if( len != 8)
2372 {
2373 cardSTATE_TO_IDLE();
6a1f2d82 2374 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2375 break;
2376 }
0c8d25eb 2377
d2f487af 2378 uint32_t ar = bytes_to_num(receivedCmd, 4);
6a1f2d82 2379 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
d2f487af 2380
2381 //Collect AR/NR
2382 if(ar_nr_collected < 2){
273b57a7 2383 if(ar_nr_responses[2] != ar)
2384 {// Avoid duplicates... probably not necessary, ar should vary.
d2f487af 2385 ar_nr_responses[ar_nr_collected*4] = cuid;
2386 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2387 ar_nr_responses[ar_nr_collected*4+2] = ar;
2388 ar_nr_responses[ar_nr_collected*4+3] = nr;
273b57a7 2389 ar_nr_collected++;
d2f487af 2390 }
2391 }
2392
2393 // --- crypto
2394 crypto1_word(pcs, ar , 1);
2395 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2396
2397 // test if auth OK
2398 if (cardRr != prng_successor(nonce, 64)){
b03c0f2d 2399 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2400 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2401 cardRr, prng_successor(nonce, 64));
7bc95e2e 2402 // Shouldn't we respond anything here?
d2f487af 2403 // Right now, we don't nack or anything, which causes the
2404 // reader to do a WUPA after a while. /Martin
b03c0f2d 2405 // -- which is the correct response. /piwi
d2f487af 2406 cardSTATE_TO_IDLE();
6a1f2d82 2407 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2408 break;
2409 }
2410
2411 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2412
2413 num_to_bytes(ans, 4, rAUTH_AT);
2414 // --- crypto
2415 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2416 LED_C_ON();
2417 cardSTATE = MFEMUL_WORK;
b03c0f2d 2418 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2419 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2420 GetTickCount() - authTimer);
d2f487af 2421 break;
2422 }
50193c1e 2423 case MFEMUL_SELECT2:{
7bc95e2e 2424 if (!len) {
6a1f2d82 2425 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2426 break;
2427 }
8556b852 2428 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
9ca155ba 2429 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
8556b852
M
2430 break;
2431 }
9ca155ba 2432
8556b852
M
2433 // select 2 card
2434 if (len == 9 &&
2435 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2436 EmSendCmd(rSAK, sizeof(rSAK));
8556b852
M
2437 cuid = bytes_to_num(rUIDBCC2, 4);
2438 cardSTATE = MFEMUL_WORK;
2439 LED_B_ON();
0014cb46 2440 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
8556b852
M
2441 break;
2442 }
0014cb46
M
2443
2444 // i guess there is a command). go into the work state.
7bc95e2e 2445 if (len != 4) {
6a1f2d82 2446 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2447 break;
2448 }
0014cb46 2449 cardSTATE = MFEMUL_WORK;
d2f487af 2450 //goto lbWORK;
2451 //intentional fall-through to the next case-stmt
50193c1e 2452 }
51969283 2453
7bc95e2e 2454 case MFEMUL_WORK:{
2455 if (len == 0) {
6a1f2d82 2456 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2457 break;
2458 }
2459
d2f487af 2460 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2461
7bc95e2e 2462 if(encrypted_data) {
51969283
M
2463 // decrypt seqence
2464 mf_crypto1_decrypt(pcs, receivedCmd, len);
d2f487af 2465 }
7bc95e2e 2466
d2f487af 2467 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2468 authTimer = GetTickCount();
2469 cardAUTHSC = receivedCmd[1] / 4; // received block num
2470 cardAUTHKEY = receivedCmd[0] - 0x60;
2471 crypto1_destroy(pcs);//Added by martin
2472 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
51969283 2473
d2f487af 2474 if (!encrypted_data) { // first authentication
b03c0f2d 2475 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
51969283 2476
d2f487af 2477 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2478 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
7bc95e2e 2479 } else { // nested authentication
b03c0f2d 2480 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
7bc95e2e 2481 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
d2f487af 2482 num_to_bytes(ans, 4, rAUTH_AT);
2483 }
0c8d25eb 2484
d2f487af 2485 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2486 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2487 cardSTATE = MFEMUL_AUTH1;
2488 break;
51969283 2489 }
7bc95e2e 2490
8f51ddb0
M
2491 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2492 // BUT... ACK --> NACK
2493 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2494 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2495 break;
2496 }
2497
2498 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2499 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2500 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2501 break;
0a39986e
M
2502 }
2503
7bc95e2e 2504 if(len != 4) {
6a1f2d82 2505 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2506 break;
2507 }
d2f487af 2508
2509 if(receivedCmd[0] == 0x30 // read block
2510 || receivedCmd[0] == 0xA0 // write block
b03c0f2d 2511 || receivedCmd[0] == 0xC0 // inc
2512 || receivedCmd[0] == 0xC1 // dec
2513 || receivedCmd[0] == 0xC2 // restore
7bc95e2e 2514 || receivedCmd[0] == 0xB0) { // transfer
2515 if (receivedCmd[1] >= 16 * 4) {
d2f487af 2516 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2517 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2518 break;
2519 }
2520
7bc95e2e 2521 if (receivedCmd[1] / 4 != cardAUTHSC) {
8f51ddb0 2522 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
d2f487af 2523 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
8f51ddb0
M
2524 break;
2525 }
d2f487af 2526 }
2527 // read block
2528 if (receivedCmd[0] == 0x30) {
b03c0f2d 2529 if (MF_DBGLEVEL >= 4) {
d2f487af 2530 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2531 }
8f51ddb0
M
2532 emlGetMem(response, receivedCmd[1], 1);
2533 AppendCrc14443a(response, 16);
6a1f2d82 2534 mf_crypto1_encrypt(pcs, response, 18, response_par);
2535 EmSendCmdPar(response, 18, response_par);
d2f487af 2536 numReads++;
7bc95e2e 2537 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
d2f487af 2538 Dbprintf("%d reads done, exiting", numReads);
2539 finished = true;
2540 }
0a39986e
M
2541 break;
2542 }
0a39986e 2543 // write block
d2f487af 2544 if (receivedCmd[0] == 0xA0) {
b03c0f2d 2545 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
8f51ddb0 2546 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
8f51ddb0
M
2547 cardSTATE = MFEMUL_WRITEBL2;
2548 cardWRBL = receivedCmd[1];
0a39986e 2549 break;
7bc95e2e 2550 }
0014cb46 2551 // increment, decrement, restore
d2f487af 2552 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
b03c0f2d 2553 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2554 if (emlCheckValBl(receivedCmd[1])) {
2555 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
0014cb46
M
2556 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2557 break;
2558 }
2559 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2560 if (receivedCmd[0] == 0xC1)
2561 cardSTATE = MFEMUL_INTREG_INC;
2562 if (receivedCmd[0] == 0xC0)
2563 cardSTATE = MFEMUL_INTREG_DEC;
2564 if (receivedCmd[0] == 0xC2)
2565 cardSTATE = MFEMUL_INTREG_REST;
2566 cardWRBL = receivedCmd[1];
0014cb46
M
2567 break;
2568 }
0014cb46 2569 // transfer
d2f487af 2570 if (receivedCmd[0] == 0xB0) {
b03c0f2d 2571 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
0014cb46
M
2572 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2573 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2574 else
2575 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0014cb46
M
2576 break;
2577 }
9ca155ba 2578 // halt
d2f487af 2579 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
9ca155ba 2580 LED_B_OFF();
0a39986e 2581 LED_C_OFF();
0014cb46
M
2582 cardSTATE = MFEMUL_HALTED;
2583 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
6a1f2d82 2584 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0a39986e 2585 break;
9ca155ba 2586 }
d2f487af 2587 // RATS
2588 if (receivedCmd[0] == 0xe0) {//RATS
8f51ddb0
M
2589 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2590 break;
2591 }
d2f487af 2592 // command not allowed
2593 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2594 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
51969283 2595 break;
8f51ddb0
M
2596 }
2597 case MFEMUL_WRITEBL2:{
2598 if (len == 18){
2599 mf_crypto1_decrypt(pcs, receivedCmd, len);
2600 emlSetMem(receivedCmd, cardWRBL, 1);
2601 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2602 cardSTATE = MFEMUL_WORK;
51969283 2603 } else {
0014cb46 2604 cardSTATE_TO_IDLE();
6a1f2d82 2605 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
8f51ddb0 2606 }
8f51ddb0 2607 break;
50193c1e 2608 }
0014cb46
M
2609
2610 case MFEMUL_INTREG_INC:{
2611 mf_crypto1_decrypt(pcs, receivedCmd, len);
2612 memcpy(&ans, receivedCmd, 4);
2613 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2614 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2615 cardSTATE_TO_IDLE();
2616 break;
7bc95e2e 2617 }
6a1f2d82 2618 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2619 cardINTREG = cardINTREG + ans;
2620 cardSTATE = MFEMUL_WORK;
2621 break;
2622 }
2623 case MFEMUL_INTREG_DEC:{
2624 mf_crypto1_decrypt(pcs, receivedCmd, len);
2625 memcpy(&ans, receivedCmd, 4);
2626 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2627 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2628 cardSTATE_TO_IDLE();
2629 break;
2630 }
6a1f2d82 2631 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2632 cardINTREG = cardINTREG - ans;
2633 cardSTATE = MFEMUL_WORK;
2634 break;
2635 }
2636 case MFEMUL_INTREG_REST:{
2637 mf_crypto1_decrypt(pcs, receivedCmd, len);
2638 memcpy(&ans, receivedCmd, 4);
2639 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2640 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2641 cardSTATE_TO_IDLE();
2642 break;
2643 }
6a1f2d82 2644 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2645 cardSTATE = MFEMUL_WORK;
2646 break;
2647 }
50193c1e 2648 }
50193c1e
M
2649 }
2650
9ca155ba
M
2651 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2652 LEDsoff();
2653
d2f487af 2654 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2655 {
2656 //May just aswell send the collected ar_nr in the response aswell
2657 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
2658 }
d714d3ef 2659
d2f487af 2660 if(flags & FLAG_NR_AR_ATTACK)
2661 {
7bc95e2e 2662 if(ar_nr_collected > 1) {
d2f487af 2663 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
d714d3ef 2664 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
0c8d25eb 2665 ar_nr_responses[0], // UID
d2f487af 2666 ar_nr_responses[1], //NT
2667 ar_nr_responses[2], //AR1
2668 ar_nr_responses[3], //NR1
2669 ar_nr_responses[6], //AR2
2670 ar_nr_responses[7] //NR2
2671 );
7bc95e2e 2672 } else {
d2f487af 2673 Dbprintf("Failed to obtain two AR/NR pairs!");
7bc95e2e 2674 if(ar_nr_collected >0) {
d714d3ef 2675 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
d2f487af 2676 ar_nr_responses[0], // UID
2677 ar_nr_responses[1], //NT
2678 ar_nr_responses[2], //AR1
2679 ar_nr_responses[3] //NR1
2680 );
2681 }
2682 }
2683 }
3000dc4e 2684 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
0c8d25eb 2685
15c4dc5a 2686}
b62a5a84 2687
d2f487af 2688
2689
b62a5a84
M
2690//-----------------------------------------------------------------------------
2691// MIFARE sniffer.
2692//
2693//-----------------------------------------------------------------------------
5cd9ec01
M
2694void RAMFUNC SniffMifare(uint8_t param) {
2695 // param:
2696 // bit 0 - trigger from first card answer
2697 // bit 1 - trigger from first reader 7-bit request
39864b0b
M
2698
2699 // C(red) A(yellow) B(green)
b62a5a84
M
2700 LEDsoff();
2701 // init trace buffer
3000dc4e
MHS
2702 clear_trace();
2703 set_tracing(TRUE);
b62a5a84 2704
b62a5a84
M
2705 // The command (reader -> tag) that we're receiving.
2706 // The length of a received command will in most cases be no more than 18 bytes.
2707 // So 32 should be enough!
f71f4deb 2708 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2709 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
b62a5a84 2710 // The response (tag -> reader) that we're receiving.
f71f4deb 2711 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
2712 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
b62a5a84
M
2713
2714 // As we receive stuff, we copy it from receivedCmd or receivedResponse
2715 // into trace, along with its length and other annotations.
2716 //uint8_t *trace = (uint8_t *)BigBuf;
2717
f71f4deb 2718 // free eventually allocated BigBuf memory
2719 BigBuf_free();
2720 // allocate the DMA buffer, used to stream samples from the FPGA
2721 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
7bc95e2e 2722 uint8_t *data = dmaBuf;
2723 uint8_t previous_data = 0;
5cd9ec01
M
2724 int maxDataLen = 0;
2725 int dataLen = 0;
7bc95e2e 2726 bool ReaderIsActive = FALSE;
2727 bool TagIsActive = FALSE;
2728
2729 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
b62a5a84
M
2730
2731 // Set up the demodulator for tag -> reader responses.
6a1f2d82 2732 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
2733
2734 // Set up the demodulator for the reader -> tag commands
6a1f2d82 2735 UartInit(receivedCmd, receivedCmdPar);
b62a5a84
M
2736
2737 // Setup for the DMA.
7bc95e2e 2738 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
b62a5a84 2739
b62a5a84 2740 LED_D_OFF();
39864b0b
M
2741
2742 // init sniffer
2743 MfSniffInit();
b62a5a84 2744
b62a5a84 2745 // And now we loop, receiving samples.
7bc95e2e 2746 for(uint32_t sniffCounter = 0; TRUE; ) {
2747
5cd9ec01
M
2748 if(BUTTON_PRESS()) {
2749 DbpString("cancelled by button");
7bc95e2e 2750 break;
5cd9ec01
M
2751 }
2752
b62a5a84
M
2753 LED_A_ON();
2754 WDT_HIT();
39864b0b 2755
7bc95e2e 2756 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2757 // check if a transaction is completed (timeout after 2000ms).
2758 // if yes, stop the DMA transfer and send what we have so far to the client
2759 if (MfSniffSend(2000)) {
2760 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2761 sniffCounter = 0;
2762 data = dmaBuf;
2763 maxDataLen = 0;
2764 ReaderIsActive = FALSE;
2765 TagIsActive = FALSE;
2766 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
39864b0b 2767 }
39864b0b 2768 }
7bc95e2e 2769
2770 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2771 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2772 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2773 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2774 } else {
2775 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
5cd9ec01
M
2776 }
2777 // test for length of buffer
7bc95e2e 2778 if(dataLen > maxDataLen) { // we are more behind than ever...
2779 maxDataLen = dataLen;
f71f4deb 2780 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
5cd9ec01 2781 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 2782 break;
b62a5a84
M
2783 }
2784 }
5cd9ec01 2785 if(dataLen < 1) continue;
b62a5a84 2786
7bc95e2e 2787 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
2788 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2789 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2790 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
55acbb2a 2791 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
2792 }
2793 // secondary buffer sets as primary, secondary buffer was stopped
2794 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2795 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
2796 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2797 }
5cd9ec01
M
2798
2799 LED_A_OFF();
b62a5a84 2800
7bc95e2e 2801 if (sniffCounter & 0x01) {
b62a5a84 2802
7bc95e2e 2803 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2804 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2805 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2806 LED_C_INV();
6a1f2d82 2807 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
b62a5a84 2808
7bc95e2e 2809 /* And ready to receive another command. */
05ddb52c 2810 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 2811
2812 /* And also reset the demod code */
2813 DemodReset();
2814 }
2815 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2816 }
2817
2818 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2819 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2820 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2821 LED_C_INV();
b62a5a84 2822
6a1f2d82 2823 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
39864b0b 2824
7bc95e2e 2825 // And ready to receive another response.
2826 DemodReset();
2827 }
2828 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2829 }
b62a5a84
M
2830 }
2831
7bc95e2e 2832 previous_data = *data;
2833 sniffCounter++;
5cd9ec01 2834 data++;
d714d3ef 2835 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01 2836 data = dmaBuf;
b62a5a84 2837 }
7bc95e2e 2838
b62a5a84
M
2839 } // main cycle
2840
2841 DbpString("COMMAND FINISHED");
2842
55acbb2a 2843 FpgaDisableSscDma();
39864b0b
M
2844 MfSniffEnd();
2845
7bc95e2e 2846 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
b62a5a84 2847 LEDsoff();
3803d529 2848}
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