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lf t5 read plus lf demod adjustments
[proxmark3-svn] / armsrc / lfops.c
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e09f21fa 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
9//-----------------------------------------------------------------------------
10
11#include "proxmark3.h"
12#include "apps.h"
13#include "util.h"
14#include "hitag2.h"
15#include "crc16.h"
16#include "string.h"
17#include "lfdemod.h"
18#include "lfsampling.h"
f7048dc8 19#include "usb_cdc.h"
e09f21fa 20
21
22/**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
30{
31
32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
34
35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
71
72 // now do the read
73 DoAcquisition_config(false);
74}
75
76
77
78/* blank r/w tag data stream
79...0000000000000000 01111111
801010101010101010101010101010101010101010101010101010101010101010
810011010010100001
8201111111
83101010101010101[0]000...
84
85[5555fe852c5555555555555555fe0000]
86*/
87void ReadTItag(void)
88{
89 // some hardcoded initial params
90 // when we read a TI tag we sample the zerocross line at 2Mhz
91 // TI tags modulate a 1 as 16 cycles of 123.2Khz
92 // TI tags modulate a 0 as 16 cycles of 134.2Khz
93 #define FSAMPLE 2000000
94 #define FREQLO 123200
95 #define FREQHI 134200
96
97 signed char *dest = (signed char *)BigBuf_get_addr();
98 uint16_t n = BigBuf_max_traceLen();
99 // 128 bit shift register [shift3:shift2:shift1:shift0]
100 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
101
102 int i, cycles=0, samples=0;
103 // how many sample points fit in 16 cycles of each frequency
104 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
105 // when to tell if we're close enough to one freq or another
106 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
107
108 // TI tags charge at 134.2Khz
109 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
111
112 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
113 // connects to SSP_DIN and the SSP_DOUT logic level controls
114 // whether we're modulating the antenna (high)
115 // or listening to the antenna (low)
116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
117
118 // get TI tag data into the buffer
119 AcquireTiType();
120
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
122
123 for (i=0; i<n-1; i++) {
124 // count cycles by looking for lo to hi zero crossings
125 if ( (dest[i]<0) && (dest[i+1]>0) ) {
126 cycles++;
127 // after 16 cycles, measure the frequency
128 if (cycles>15) {
129 cycles=0;
130 samples=i-samples; // number of samples in these 16 cycles
131
132 // TI bits are coming to us lsb first so shift them
133 // right through our 128 bit right shift register
134 shift0 = (shift0>>1) | (shift1 << 31);
135 shift1 = (shift1>>1) | (shift2 << 31);
136 shift2 = (shift2>>1) | (shift3 << 31);
137 shift3 >>= 1;
138
139 // check if the cycles fall close to the number
140 // expected for either the low or high frequency
141 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
142 // low frequency represents a 1
143 shift3 |= (1<<31);
144 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
145 // high frequency represents a 0
146 } else {
147 // probably detected a gay waveform or noise
148 // use this as gaydar or discard shift register and start again
149 shift3 = shift2 = shift1 = shift0 = 0;
150 }
151 samples = i;
152
153 // for each bit we receive, test if we've detected a valid tag
154
155 // if we see 17 zeroes followed by 6 ones, we might have a tag
156 // remember the bits are backwards
157 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
158 // if start and end bytes match, we have a tag so break out of the loop
159 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
160 cycles = 0xF0B; //use this as a flag (ugly but whatever)
161 break;
162 }
163 }
164 }
165 }
166 }
167
168 // if flag is set we have a tag
169 if (cycles!=0xF0B) {
170 DbpString("Info: No valid tag detected.");
171 } else {
172 // put 64 bit data into shift1 and shift0
173 shift0 = (shift0>>24) | (shift1 << 8);
174 shift1 = (shift1>>24) | (shift2 << 8);
175
176 // align 16 bit crc into lower half of shift2
177 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
178
179 // if r/w tag, check ident match
180 if (shift3 & (1<<15) ) {
181 DbpString("Info: TI tag is rewriteable");
182 // only 15 bits compare, last bit of ident is not valid
183 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
184 DbpString("Error: Ident mismatch!");
185 } else {
186 DbpString("Info: TI tag ident is valid");
187 }
188 } else {
189 DbpString("Info: TI tag is readonly");
190 }
191
192 // WARNING the order of the bytes in which we calc crc below needs checking
193 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
194 // bytes in reverse or something
195 // calculate CRC
196 uint32_t crc=0;
197
198 crc = update_crc16(crc, (shift0)&0xff);
199 crc = update_crc16(crc, (shift0>>8)&0xff);
200 crc = update_crc16(crc, (shift0>>16)&0xff);
201 crc = update_crc16(crc, (shift0>>24)&0xff);
202 crc = update_crc16(crc, (shift1)&0xff);
203 crc = update_crc16(crc, (shift1>>8)&0xff);
204 crc = update_crc16(crc, (shift1>>16)&0xff);
205 crc = update_crc16(crc, (shift1>>24)&0xff);
206
207 Dbprintf("Info: Tag data: %x%08x, crc=%x",
208 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
209 if (crc != (shift2&0xffff)) {
210 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
211 } else {
212 DbpString("Info: CRC is good");
213 }
214 }
215}
216
217void WriteTIbyte(uint8_t b)
218{
219 int i = 0;
220
221 // modulate 8 bits out to the antenna
222 for (i=0; i<8; i++)
223 {
224 if (b&(1<<i)) {
225 // stop modulating antenna
226 LOW(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 // modulate antenna
229 HIGH(GPIO_SSC_DOUT);
230 SpinDelayUs(1000);
231 } else {
232 // stop modulating antenna
233 LOW(GPIO_SSC_DOUT);
234 SpinDelayUs(300);
235 // modulate antenna
236 HIGH(GPIO_SSC_DOUT);
237 SpinDelayUs(1700);
238 }
239 }
240}
241
242void AcquireTiType(void)
243{
244 int i, j, n;
245 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
246 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
247 #define TIBUFLEN 1250
248
249 // clear buffer
250 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
251 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
252
253 // Set up the synchronous serial port
254 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
255 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
256
257 // steal this pin from the SSP and use it to control the modulation
258 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
259 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
260
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
262 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
263
264 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
265 // 48/2 = 24 MHz clock must be divided by 12
266 AT91C_BASE_SSC->SSC_CMR = 12;
267
268 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
269 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
270 AT91C_BASE_SSC->SSC_TCMR = 0;
271 AT91C_BASE_SSC->SSC_TFMR = 0;
272
273 LED_D_ON();
274
275 // modulate antenna
276 HIGH(GPIO_SSC_DOUT);
277
278 // Charge TI tag for 50ms.
279 SpinDelay(50);
280
281 // stop modulating antenna and listen
282 LOW(GPIO_SSC_DOUT);
283
284 LED_D_OFF();
285
286 i = 0;
287 for(;;) {
288 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
289 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
290 i++; if(i >= TIBUFLEN) break;
291 }
292 WDT_HIT();
293 }
294
295 // return stolen pin to SSP
296 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
297 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
298
299 char *dest = (char *)BigBuf_get_addr();
300 n = TIBUFLEN*32;
301 // unpack buffer
302 for (i=TIBUFLEN-1; i>=0; i--) {
303 for (j=0; j<32; j++) {
304 if(BigBuf[i] & (1 << j)) {
305 dest[--n] = 1;
306 } else {
307 dest[--n] = -1;
308 }
309 }
310 }
311}
312
313// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
314// if crc provided, it will be written with the data verbatim (even if bogus)
315// if not provided a valid crc will be computed from the data and written.
316void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
317{
318 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
319 if(crc == 0) {
320 crc = update_crc16(crc, (idlo)&0xff);
321 crc = update_crc16(crc, (idlo>>8)&0xff);
322 crc = update_crc16(crc, (idlo>>16)&0xff);
323 crc = update_crc16(crc, (idlo>>24)&0xff);
324 crc = update_crc16(crc, (idhi)&0xff);
325 crc = update_crc16(crc, (idhi>>8)&0xff);
326 crc = update_crc16(crc, (idhi>>16)&0xff);
327 crc = update_crc16(crc, (idhi>>24)&0xff);
328 }
329 Dbprintf("Writing to tag: %x%08x, crc=%x",
330 (unsigned int) idhi, (unsigned int) idlo, crc);
331
332 // TI tags charge at 134.2Khz
333 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
334 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
335 // connects to SSP_DIN and the SSP_DOUT logic level controls
336 // whether we're modulating the antenna (high)
337 // or listening to the antenna (low)
338 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
339 LED_A_ON();
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 // writing algorithm:
346 // a high bit consists of a field off for 1ms and field on for 1ms
347 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
348 // initiate a charge time of 50ms (field on) then immediately start writing bits
349 // start by writing 0xBB (keyword) and 0xEB (password)
350 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
351 // finally end with 0x0300 (write frame)
352 // all data is sent lsb firts
353 // finish with 15ms programming time
354
355 // modulate antenna
356 HIGH(GPIO_SSC_DOUT);
357 SpinDelay(50); // charge time
358
359 WriteTIbyte(0xbb); // keyword
360 WriteTIbyte(0xeb); // password
361 WriteTIbyte( (idlo )&0xff );
362 WriteTIbyte( (idlo>>8 )&0xff );
363 WriteTIbyte( (idlo>>16)&0xff );
364 WriteTIbyte( (idlo>>24)&0xff );
365 WriteTIbyte( (idhi )&0xff );
366 WriteTIbyte( (idhi>>8 )&0xff );
367 WriteTIbyte( (idhi>>16)&0xff );
368 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
369 WriteTIbyte( (crc )&0xff ); // crc lo
370 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
371 WriteTIbyte(0x00); // write frame lo
372 WriteTIbyte(0x03); // write frame hi
373 HIGH(GPIO_SSC_DOUT);
374 SpinDelay(50); // programming time
375
376 LED_A_OFF();
377
378 // get TI tag data into the buffer
379 AcquireTiType();
380
381 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
382 DbpString("Now use tiread to check");
383}
384
385void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
386{
387 int i;
388 uint8_t *tab = BigBuf_get_addr();
389
390 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
391 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
392
393 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
394
395 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
396 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
397
398 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
399 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
400
401 i = 0;
402 for(;;) {
403 //wait until SSC_CLK goes HIGH
404 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
f7048dc8 405 if(BUTTON_PRESS() || usb_poll()) {
e09f21fa 406 DbpString("Stopped");
407 return;
408 }
409 WDT_HIT();
410 }
411 if (ledcontrol)
412 LED_D_ON();
413
414 if(tab[i])
415 OPEN_COIL();
416 else
417 SHORT_COIL();
418
419 if (ledcontrol)
420 LED_D_OFF();
421 //wait until SSC_CLK goes LOW
422 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
423 if(BUTTON_PRESS()) {
424 DbpString("Stopped");
425 return;
426 }
427 WDT_HIT();
428 }
429
430 i++;
431 if(i == period) {
432
433 i = 0;
434 if (gap) {
435 SHORT_COIL();
436 SpinDelayUs(gap);
437 }
438 }
439 }
440}
441
e09f21fa 442#define DEBUG_FRAME_CONTENTS 1
443void SimulateTagLowFrequencyBidir(int divisor, int t0)
444{
445}
446
447// compose fc/8 fc/10 waveform (FSK2)
448static void fc(int c, int *n)
449{
450 uint8_t *dest = BigBuf_get_addr();
451 int idx;
452
453 // for when we want an fc8 pattern every 4 logical bits
454 if(c==0) {
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=1;
458 dest[((*n)++)]=1;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 dest[((*n)++)]=0;
462 dest[((*n)++)]=0;
463 }
464
712ebfa6 465 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
e09f21fa 466 if(c==8) {
467 for (idx=0; idx<6; idx++) {
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=1;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 dest[((*n)++)]=0;
476 }
477 }
478
712ebfa6 479 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
e09f21fa 480 if(c==10) {
481 for (idx=0; idx<5; idx++) {
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=1;
486 dest[((*n)++)]=1;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 dest[((*n)++)]=0;
491 dest[((*n)++)]=0;
492 }
493 }
494}
495// compose fc/X fc/Y waveform (FSKx)
712ebfa6 496static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 497{
498 uint8_t *dest = BigBuf_get_addr();
712ebfa6 499 uint8_t halfFC = fc/2;
500 uint8_t wavesPerClock = clock/fc;
501 uint8_t mod = clock % fc; //modifier
502 uint8_t modAdj = fc/mod; //how often to apply modifier
503 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
e09f21fa 504 // loop through clock - step field clock
712ebfa6 505 for (uint8_t idx=0; idx < wavesPerClock; idx++){
506 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
507 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
508 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
509 *n += fc;
e09f21fa 510 }
511 if (mod>0) (*modCnt)++;
512 if ((mod>0) && modAdjOk){ //fsk2
513 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
712ebfa6 514 memset(dest+(*n), 0, fc-halfFC);
515 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
516 *n += fc;
e09f21fa 517 }
518 }
e09f21fa 519 if (mod>0 && !modAdjOk){ //fsk1
712ebfa6 520 memset(dest+(*n), 0, mod-(mod/2));
521 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
522 *n += mod;
e09f21fa 523 }
524}
525
526// prepare a waveform pattern in the buffer based on the ID given then
527// simulate a HID tag until the button is pressed
528void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
529{
530 int n=0, i=0;
531 /*
532 HID tag bitstream format
533 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
534 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
535 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
536 A fc8 is inserted before every 4 bits
537 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
538 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
539 */
540
541 if (hi>0xFFF) {
78f5b1a7 542 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
e09f21fa 543 return;
544 }
545 fc(0,&n);
546 // special start of frame marker containing invalid bit sequences
547 fc(8, &n); fc(8, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549 fc(10, &n); fc(10, &n); // invalid
550 fc(8, &n); fc(10, &n); // logical 0
551
552 WDT_HIT();
553 // manchester encode bits 43 to 32
554 for (i=11; i>=0; i--) {
555 if ((i%4)==3) fc(0,&n);
556 if ((hi>>i)&1) {
557 fc(10, &n); fc(8, &n); // low-high transition
558 } else {
559 fc(8, &n); fc(10, &n); // high-low transition
560 }
561 }
562
563 WDT_HIT();
564 // manchester encode bits 31 to 0
565 for (i=31; i>=0; i--) {
566 if ((i%4)==3) fc(0,&n);
567 if ((lo>>i)&1) {
568 fc(10, &n); fc(8, &n); // low-high transition
569 } else {
570 fc(8, &n); fc(10, &n); // high-low transition
571 }
572 }
573
574 if (ledcontrol)
575 LED_A_ON();
576 SimulateTagLowFrequency(n, 0, ledcontrol);
577
578 if (ledcontrol)
579 LED_A_OFF();
580}
581
582// prepare a waveform pattern in the buffer based on the ID given then
583// simulate a FSK tag until the button is pressed
584// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
585void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
586{
587 int ledcontrol=1;
588 int n=0, i=0;
589 uint8_t fcHigh = arg1 >> 8;
590 uint8_t fcLow = arg1 & 0xFF;
591 uint16_t modCnt = 0;
e09f21fa 592 uint8_t clk = arg2 & 0xFF;
593 uint8_t invert = (arg2 >> 8) & 1;
712ebfa6 594
e09f21fa 595 for (i=0; i<size; i++){
596 if (BitStream[i] == invert){
597 fcAll(fcLow, &n, clk, &modCnt);
598 } else {
599 fcAll(fcHigh, &n, clk, &modCnt);
600 }
601 }
602 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
712ebfa6 603 /*Dbprintf("DEBUG: First 32:");
e09f21fa 604 uint8_t *dest = BigBuf_get_addr();
605 i=0;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
607 i+=16;
608 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
78f5b1a7 609 */
e09f21fa 610 if (ledcontrol)
611 LED_A_ON();
712ebfa6 612
78f5b1a7 613 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 614
615 if (ledcontrol)
616 LED_A_OFF();
617}
618
619// compose ask waveform for one bit(ASK)
620static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
621{
622 uint8_t *dest = BigBuf_get_addr();
712ebfa6 623 uint8_t halfClk = clock/2;
e09f21fa 624 // c = current bit 1 or 0
b41534d1 625 if (manchester==1){
712ebfa6 626 memset(dest+(*n), c, halfClk);
627 memset(dest+(*n) + halfClk, c^1, halfClk);
e09f21fa 628 } else {
712ebfa6 629 memset(dest+(*n), c, clock);
e09f21fa 630 }
712ebfa6 631 *n += clock;
e09f21fa 632}
633
b41534d1 634static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
635{
636 uint8_t *dest = BigBuf_get_addr();
637 uint8_t halfClk = clock/2;
638 if (c){
639 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
640 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
641 } else {
642 memset(dest+(*n), c ^ *phase, clock);
643 *phase ^= 1;
644 }
645
646}
647
e09f21fa 648// args clock, ask/man or askraw, invert, transmission separator
649void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
650{
651 int ledcontrol = 1;
652 int n=0, i=0;
653 uint8_t clk = (arg1 >> 8) & 0xFF;
b41534d1 654 uint8_t encoding = arg1 & 1;
e09f21fa 655 uint8_t separator = arg2 & 1;
656 uint8_t invert = (arg2 >> 8) & 1;
b41534d1 657
658 if (encoding==2){ //biphase
659 uint8_t phase=0;
660 for (i=0; i<size; i++){
661 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
662 }
663 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
664 for (i=0; i<size; i++){
665 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
666 }
667 }
668 } else { // ask/manchester || ask/raw
ada339a1 669 for (i=0; i<size; i++){
b41534d1 670 askSimBit(BitStream[i]^invert, &n, clk, encoding);
671 }
672 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
673 for (i=0; i<size; i++){
674 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
675 }
ada339a1 676 }
677 }
b41534d1 678
712ebfa6 679 if (separator==1) Dbprintf("sorry but separator option not yet available");
e09f21fa 680
b41534d1 681 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
e09f21fa 682 //DEBUG
712ebfa6 683 //Dbprintf("First 32:");
e09f21fa 684 //uint8_t *dest = BigBuf_get_addr();
685 //i=0;
686 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
687 //i+=16;
688 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 689
690 if (ledcontrol)
691 LED_A_ON();
712ebfa6 692
78f5b1a7 693 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 694
695 if (ledcontrol)
696 LED_A_OFF();
697}
698
699//carrier can be 2,4 or 8
700static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
701{
702 uint8_t *dest = BigBuf_get_addr();
712ebfa6 703 uint8_t halfWave = waveLen/2;
704 //uint8_t idx;
e09f21fa 705 int i = 0;
706 if (phaseChg){
707 // write phase change
712ebfa6 708 memset(dest+(*n), *curPhase^1, halfWave);
709 memset(dest+(*n) + halfWave, *curPhase, halfWave);
710 *n += waveLen;
e09f21fa 711 *curPhase ^= 1;
712ebfa6 712 i += waveLen;
e09f21fa 713 }
714 //write each normal clock wave for the clock duration
715 for (; i < clk; i+=waveLen){
712ebfa6 716 memset(dest+(*n), *curPhase, halfWave);
717 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
718 *n += waveLen;
e09f21fa 719 }
720}
721
722// args clock, carrier, invert,
723void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
724{
725 int ledcontrol=1;
726 int n=0, i=0;
727 uint8_t clk = arg1 >> 8;
728 uint8_t carrier = arg1 & 0xFF;
729 uint8_t invert = arg2 & 0xFF;
78f5b1a7 730 uint8_t curPhase = 0;
e09f21fa 731 for (i=0; i<size; i++){
732 if (BitStream[i] == curPhase){
733 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
734 } else {
735 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
736 }
737 }
738 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
712ebfa6 739 //Dbprintf("DEBUG: First 32:");
740 //uint8_t *dest = BigBuf_get_addr();
741 //i=0;
742 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
743 //i+=16;
744 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 745
746 if (ledcontrol)
747 LED_A_ON();
78f5b1a7 748 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 749
750 if (ledcontrol)
751 LED_A_OFF();
752}
753
754// loop to get raw HID waveform then FSK demodulate the TAG ID from it
755void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
756{
757 uint8_t *dest = BigBuf_get_addr();
758 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
759 size_t size = 0;
760 uint32_t hi2=0, hi=0, lo=0;
761 int idx=0;
762 // Configure to go in 125Khz listen mode
763 LFSetupFPGAForADC(95, true);
764
765 while(!BUTTON_PRESS()) {
766
767 WDT_HIT();
768 if (ledcontrol) LED_A_ON();
769
770 DoAcquisition_default(-1,true);
771 // FSK demodulator
772 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
773 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
774
775 if (idx>0 && lo>0){
776 // final loop, go over previously decoded manchester data and decode into usable tag ID
777 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
778 if (hi2 != 0){ //extra large HID tags
779 Dbprintf("TAG ID: %x%08x%08x (%d)",
780 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
781 }else { //standard HID tags <38 bits
782 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
783 uint8_t bitlen = 0;
784 uint32_t fc = 0;
785 uint32_t cardnum = 0;
786 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
787 uint32_t lo2=0;
788 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
789 uint8_t idx3 = 1;
790 while(lo2 > 1){ //find last bit set to 1 (format len bit)
791 lo2=lo2 >> 1;
792 idx3++;
793 }
794 bitlen = idx3+19;
795 fc =0;
796 cardnum=0;
797 if(bitlen == 26){
798 cardnum = (lo>>1)&0xFFFF;
799 fc = (lo>>17)&0xFF;
800 }
801 if(bitlen == 37){
802 cardnum = (lo>>1)&0x7FFFF;
803 fc = ((hi&0xF)<<12)|(lo>>20);
804 }
805 if(bitlen == 34){
806 cardnum = (lo>>1)&0xFFFF;
807 fc= ((hi&1)<<15)|(lo>>17);
808 }
809 if(bitlen == 35){
810 cardnum = (lo>>1)&0xFFFFF;
811 fc = ((hi&1)<<11)|(lo>>21);
812 }
813 }
814 else { //if bit 38 is not set then 37 bit format is used
815 bitlen= 37;
816 fc =0;
817 cardnum=0;
818 if(bitlen==37){
819 cardnum = (lo>>1)&0x7FFFF;
820 fc = ((hi&0xF)<<12)|(lo>>20);
821 }
822 }
823 //Dbprintf("TAG ID: %x%08x (%d)",
824 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
825 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
826 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
827 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
828 }
829 if (findone){
830 if (ledcontrol) LED_A_OFF();
831 *high = hi;
832 *low = lo;
833 return;
834 }
835 // reset
836 hi2 = hi = lo = 0;
837 }
838 WDT_HIT();
839 }
840 DbpString("Stopped");
841 if (ledcontrol) LED_A_OFF();
842}
843
844void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
845{
846 uint8_t *dest = BigBuf_get_addr();
847
b41534d1 848 size_t size=0, idx=0;
e09f21fa 849 int clk=0, invert=0, errCnt=0, maxErr=20;
b41534d1 850 uint32_t hi=0;
e09f21fa 851 uint64_t lo=0;
852 // Configure to go in 125Khz listen mode
853 LFSetupFPGAForADC(95, true);
854
855 while(!BUTTON_PRESS()) {
856
857 WDT_HIT();
858 if (ledcontrol) LED_A_ON();
859
b41534d1 860 DoAcquisition_default(-1,true);
861 size = BigBuf_max_traceLen();
e09f21fa 862 //Dbprintf("DEBUG: Buffer got");
b41534d1 863 //askdemod and manchester decode
864 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
e09f21fa 865 //Dbprintf("DEBUG: ASK Got");
866 WDT_HIT();
867
868 if (errCnt>=0){
b41534d1 869 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
e09f21fa 870 //Dbprintf("DEBUG: EM GOT");
b41534d1 871 if (errCnt){
872 if (size>64){
873 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
874 hi,
875 (uint32_t)(lo>>32),
876 (uint32_t)lo,
877 (uint32_t)(lo&0xFFFF),
878 (uint32_t)((lo>>16LL) & 0xFF),
879 (uint32_t)(lo & 0xFFFFFF));
880 } else {
881 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
882 (uint32_t)(lo>>32),
883 (uint32_t)lo,
884 (uint32_t)(lo&0xFFFF),
885 (uint32_t)((lo>>16LL) & 0xFF),
886 (uint32_t)(lo & 0xFFFFFF));
887 }
e09f21fa 888 }
889 if (findone){
890 if (ledcontrol) LED_A_OFF();
891 *high=lo>>32;
892 *low=lo & 0xFFFFFFFF;
893 return;
894 }
895 } else{
896 //Dbprintf("DEBUG: No Tag");
897 }
898 WDT_HIT();
899 lo = 0;
900 clk=0;
901 invert=0;
902 errCnt=0;
903 size=0;
904 }
905 DbpString("Stopped");
906 if (ledcontrol) LED_A_OFF();
907}
908
909void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
910{
911 uint8_t *dest = BigBuf_get_addr();
912 int idx=0;
913 uint32_t code=0, code2=0;
914 uint8_t version=0;
915 uint8_t facilitycode=0;
916 uint16_t number=0;
917 // Configure to go in 125Khz listen mode
918 LFSetupFPGAForADC(95, true);
919
920 while(!BUTTON_PRESS()) {
921 WDT_HIT();
922 if (ledcontrol) LED_A_ON();
923 DoAcquisition_default(-1,true);
924 //fskdemod and get start index
925 WDT_HIT();
926 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
927 if (idx>0){
928 //valid tag found
929
930 //Index map
931 //0 10 20 30 40 50 60
932 //| | | | | | |
933 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
934 //-----------------------------------------------------------------------------
935 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
936 //
937 //XSF(version)facility:codeone+codetwo
938 //Handle the data
939 if(findone){ //only print binary if we are doing one
940 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
941 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
942 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
943 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
944 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
945 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
946 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
947 }
948 code = bytebits_to_byte(dest+idx,32);
949 code2 = bytebits_to_byte(dest+idx+32,32);
950 version = bytebits_to_byte(dest+idx+27,8); //14,4
951 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
952 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
953
954 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
955 // if we're only looking for one tag
956 if (findone){
957 if (ledcontrol) LED_A_OFF();
958 //LED_A_OFF();
959 *high=code;
960 *low=code2;
961 return;
962 }
963 code=code2=0;
964 version=facilitycode=0;
965 number=0;
966 idx=0;
967 }
968 WDT_HIT();
969 }
970 DbpString("Stopped");
971 if (ledcontrol) LED_A_OFF();
972}
973
974/*------------------------------
975 * T5555/T5557/T5567 routines
976 *------------------------------
977 */
978
979/* T55x7 configuration register definitions */
980#define T55x7_POR_DELAY 0x00000001
981#define T55x7_ST_TERMINATOR 0x00000008
982#define T55x7_PWD 0x00000010
983#define T55x7_MAXBLOCK_SHIFT 5
984#define T55x7_AOR 0x00000200
985#define T55x7_PSKCF_RF_2 0
986#define T55x7_PSKCF_RF_4 0x00000400
987#define T55x7_PSKCF_RF_8 0x00000800
988#define T55x7_MODULATION_DIRECT 0
989#define T55x7_MODULATION_PSK1 0x00001000
990#define T55x7_MODULATION_PSK2 0x00002000
991#define T55x7_MODULATION_PSK3 0x00003000
992#define T55x7_MODULATION_FSK1 0x00004000
993#define T55x7_MODULATION_FSK2 0x00005000
994#define T55x7_MODULATION_FSK1a 0x00006000
995#define T55x7_MODULATION_FSK2a 0x00007000
996#define T55x7_MODULATION_MANCHESTER 0x00008000
997#define T55x7_MODULATION_BIPHASE 0x00010000
998#define T55x7_BITRATE_RF_8 0
999#define T55x7_BITRATE_RF_16 0x00040000
1000#define T55x7_BITRATE_RF_32 0x00080000
1001#define T55x7_BITRATE_RF_40 0x000C0000
1002#define T55x7_BITRATE_RF_50 0x00100000
1003#define T55x7_BITRATE_RF_64 0x00140000
1004#define T55x7_BITRATE_RF_100 0x00180000
1005#define T55x7_BITRATE_RF_128 0x001C0000
1006
1007/* T5555 (Q5) configuration register definitions */
1008#define T5555_ST_TERMINATOR 0x00000001
1009#define T5555_MAXBLOCK_SHIFT 0x00000001
1010#define T5555_MODULATION_MANCHESTER 0
1011#define T5555_MODULATION_PSK1 0x00000010
1012#define T5555_MODULATION_PSK2 0x00000020
1013#define T5555_MODULATION_PSK3 0x00000030
1014#define T5555_MODULATION_FSK1 0x00000040
1015#define T5555_MODULATION_FSK2 0x00000050
1016#define T5555_MODULATION_BIPHASE 0x00000060
1017#define T5555_MODULATION_DIRECT 0x00000070
1018#define T5555_INVERT_OUTPUT 0x00000080
1019#define T5555_PSK_RF_2 0
1020#define T5555_PSK_RF_4 0x00000100
1021#define T5555_PSK_RF_8 0x00000200
1022#define T5555_USE_PWD 0x00000400
1023#define T5555_USE_AOR 0x00000800
1024#define T5555_BITRATE_SHIFT 12
1025#define T5555_FAST_WRITE 0x00004000
1026#define T5555_PAGE_SELECT 0x00008000
1027
1028/*
1029 * Relevant times in microsecond
1030 * To compensate antenna falling times shorten the write times
1031 * and enlarge the gap ones.
1032 */
13d77ef9 1033#define START_GAP 50*8 // 10 - 50fc 250
1034#define WRITE_GAP 20*8 // - 30fc 160
1035#define WRITE_0 24*8 // 16 - 63fc 54fc 144
1036#define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550 //400
1037
1038#define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
e09f21fa 1039
1040// Write one bit to card
1041void T55xxWriteBit(int bit)
1042{
1043 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1044 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1045 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1046 if (bit == 0)
1047 SpinDelayUs(WRITE_0);
1048 else
1049 SpinDelayUs(WRITE_1);
1050 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1051 SpinDelayUs(WRITE_GAP);
1052}
1053
1054// Write one card block in page 0, no lock
1055void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1056{
e09f21fa 1057 uint32_t i;
1058
1059 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1060 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1061 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1062
1063 // Give it a bit of time for the resonant antenna to settle.
1064 // And for the tag to fully power up
13d77ef9 1065 //SpinDelay(150);
e09f21fa 1066
1067 // Now start writting
1068 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1069 SpinDelayUs(START_GAP);
1070
1071 // Opcode
1072 T55xxWriteBit(1);
1073 T55xxWriteBit(0); //Page 0
1074 if (PwdMode == 1){
1075 // Pwd
1076 for (i = 0x80000000; i != 0; i >>= 1)
1077 T55xxWriteBit(Pwd & i);
1078 }
1079 // Lock bit
1080 T55xxWriteBit(0);
1081
1082 // Data
1083 for (i = 0x80000000; i != 0; i >>= 1)
1084 T55xxWriteBit(Data & i);
1085
1086 // Block
1087 for (i = 0x04; i != 0; i >>= 1)
1088 T55xxWriteBit(Block & i);
1089
1090 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1091 // so wait a little more)
1092 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1093 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1094 SpinDelay(20);
1095 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1096}
1097
13d77ef9 1098void TurnReadLFOn(){
1099 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1100 // Give it a bit of time for the resonant antenna to settle.
1101 SpinDelayUs(8*150);
1102}
1103
1104
e09f21fa 1105// Read one card block in page 0
1106void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1107{
13d77ef9 1108 uint32_t i = 0;
e09f21fa 1109 uint8_t *dest = BigBuf_get_addr();
13d77ef9 1110 uint16_t bufferlength = BigBuf_max_traceLen();
1111 if ( bufferlength > T55xx_SAMPLES_SIZE )
1112 bufferlength = T55xx_SAMPLES_SIZE;
e09f21fa 1113
13d77ef9 1114 // Clear destination buffer before sending the command
1115 memset(dest, 0x80, bufferlength);
e09f21fa 1116
13d77ef9 1117 // Set up FPGA, 125kHz
1118 // Wait for config.. (192+8190xPOW)x8 == 67ms
1119 LFSetupFPGAForADC(0, true);
e09f21fa 1120 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1121 SpinDelayUs(START_GAP);
1122
1123 // Opcode
1124 T55xxWriteBit(1);
1125 T55xxWriteBit(0); //Page 0
1126 if (PwdMode == 1){
1127 // Pwd
1128 for (i = 0x80000000; i != 0; i >>= 1)
1129 T55xxWriteBit(Pwd & i);
1130 }
1131 // Lock bit
1132 T55xxWriteBit(0);
1133 // Block
1134 for (i = 0x04; i != 0; i >>= 1)
1135 T55xxWriteBit(Block & i);
1136
1137 // Turn field on to read the response
13d77ef9 1138 TurnReadLFOn();
e09f21fa 1139 // Now do the acquisition
1140 i = 0;
1141 for(;;) {
1142 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1143 AT91C_BASE_SSC->SSC_THR = 0x43;
13d77ef9 1144 LED_D_ON();
e09f21fa 1145 }
1146 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1147 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
e09f21fa 1148 i++;
13d77ef9 1149 LED_D_OFF();
1150 if (i >= bufferlength) break;
e09f21fa 1151 }
1152 }
1153
13d77ef9 1154 cmd_send(CMD_ACK,0,0,0,0,0);
e09f21fa 1155 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1156 LED_D_OFF();
e09f21fa 1157}
1158
1159// Read card traceability data (page 1)
1160void T55xxReadTrace(void){
13d77ef9 1161
1162 uint32_t i = 0;
e09f21fa 1163 uint8_t *dest = BigBuf_get_addr();
13d77ef9 1164 uint16_t bufferlength = BigBuf_max_traceLen();
1165 if ( bufferlength > T55xx_SAMPLES_SIZE )
1166 bufferlength= T55xx_SAMPLES_SIZE;
e09f21fa 1167
e09f21fa 1168 // Clear destination buffer before sending the command
13d77ef9 1169 memset(dest, 0x80, bufferlength);
e09f21fa 1170
13d77ef9 1171 LFSetupFPGAForADC(0, true);
e09f21fa 1172 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1173 SpinDelayUs(START_GAP);
1174
1175 // Opcode
1176 T55xxWriteBit(1);
1177 T55xxWriteBit(1); //Page 1
1178
1179 // Turn field on to read the response
13d77ef9 1180 TurnReadLFOn();
e09f21fa 1181
1182 // Now do the acquisition
e09f21fa 1183 for(;;) {
1184 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1185 AT91C_BASE_SSC->SSC_THR = 0x43;
13d77ef9 1186 LED_D_ON();
e09f21fa 1187 }
1188 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1189 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1190 i++;
13d77ef9 1191 LED_D_OFF();
1192
1193 if (i >= bufferlength) break;
e09f21fa 1194 }
1195 }
1196
13d77ef9 1197 cmd_send(CMD_ACK,0,0,0,0,0);
e09f21fa 1198 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1199 LED_D_OFF();
e09f21fa 1200}
1201
1202/*-------------- Cloning routines -----------*/
1203// Copy HID id to card and setup block 0 config
1204void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1205{
1206 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1207 int last_block = 0;
1208
1209 if (longFMT){
1210 // Ensure no more than 84 bits supplied
1211 if (hi2>0xFFFFF) {
1212 DbpString("Tags can only have 84 bits.");
1213 return;
1214 }
1215 // Build the 6 data blocks for supplied 84bit ID
1216 last_block = 6;
1217 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1218 for (int i=0;i<4;i++) {
1219 if (hi2 & (1<<(19-i)))
1220 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1221 else
1222 data1 |= (1<<((3-i)*2)); // 0 -> 01
1223 }
1224
1225 data2 = 0;
1226 for (int i=0;i<16;i++) {
1227 if (hi2 & (1<<(15-i)))
1228 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1229 else
1230 data2 |= (1<<((15-i)*2)); // 0 -> 01
1231 }
1232
1233 data3 = 0;
1234 for (int i=0;i<16;i++) {
1235 if (hi & (1<<(31-i)))
1236 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1237 else
1238 data3 |= (1<<((15-i)*2)); // 0 -> 01
1239 }
1240
1241 data4 = 0;
1242 for (int i=0;i<16;i++) {
1243 if (hi & (1<<(15-i)))
1244 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1245 else
1246 data4 |= (1<<((15-i)*2)); // 0 -> 01
1247 }
1248
1249 data5 = 0;
1250 for (int i=0;i<16;i++) {
1251 if (lo & (1<<(31-i)))
1252 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1253 else
1254 data5 |= (1<<((15-i)*2)); // 0 -> 01
1255 }
1256
1257 data6 = 0;
1258 for (int i=0;i<16;i++) {
1259 if (lo & (1<<(15-i)))
1260 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1261 else
1262 data6 |= (1<<((15-i)*2)); // 0 -> 01
1263 }
1264 }
1265 else {
1266 // Ensure no more than 44 bits supplied
1267 if (hi>0xFFF) {
1268 DbpString("Tags can only have 44 bits.");
1269 return;
1270 }
1271
1272 // Build the 3 data blocks for supplied 44bit ID
1273 last_block = 3;
1274
1275 data1 = 0x1D000000; // load preamble
1276
1277 for (int i=0;i<12;i++) {
1278 if (hi & (1<<(11-i)))
1279 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1280 else
1281 data1 |= (1<<((11-i)*2)); // 0 -> 01
1282 }
1283
1284 data2 = 0;
1285 for (int i=0;i<16;i++) {
1286 if (lo & (1<<(31-i)))
1287 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1288 else
1289 data2 |= (1<<((15-i)*2)); // 0 -> 01
1290 }
1291
1292 data3 = 0;
1293 for (int i=0;i<16;i++) {
1294 if (lo & (1<<(15-i)))
1295 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1296 else
1297 data3 |= (1<<((15-i)*2)); // 0 -> 01
1298 }
1299 }
1300
1301 LED_D_ON();
1302 // Program the data blocks for supplied ID
1303 // and the block 0 for HID format
1304 T55xxWriteBlock(data1,1,0,0);
1305 T55xxWriteBlock(data2,2,0,0);
1306 T55xxWriteBlock(data3,3,0,0);
1307
1308 if (longFMT) { // if long format there are 6 blocks
1309 T55xxWriteBlock(data4,4,0,0);
1310 T55xxWriteBlock(data5,5,0,0);
1311 T55xxWriteBlock(data6,6,0,0);
1312 }
1313
1314 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1315 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1316 T55x7_MODULATION_FSK2a |
1317 last_block << T55x7_MAXBLOCK_SHIFT,
1318 0,0,0);
1319
1320 LED_D_OFF();
1321
1322 DbpString("DONE!");
1323}
1324
1325void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1326{
1327 int data1=0, data2=0; //up to six blocks for long format
1328
1329 data1 = hi; // load preamble
1330 data2 = lo;
1331
1332 LED_D_ON();
1333 // Program the data blocks for supplied ID
1334 // and the block 0 for HID format
1335 T55xxWriteBlock(data1,1,0,0);
1336 T55xxWriteBlock(data2,2,0,0);
1337
1338 //Config Block
1339 T55xxWriteBlock(0x00147040,0,0,0);
1340 LED_D_OFF();
1341
1342 DbpString("DONE!");
1343}
1344
1345// Define 9bit header for EM410x tags
1346#define EM410X_HEADER 0x1FF
1347#define EM410X_ID_LENGTH 40
1348
1349void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1350{
1351 int i, id_bit;
1352 uint64_t id = EM410X_HEADER;
1353 uint64_t rev_id = 0; // reversed ID
1354 int c_parity[4]; // column parity
1355 int r_parity = 0; // row parity
1356 uint32_t clock = 0;
1357
1358 // Reverse ID bits given as parameter (for simpler operations)
1359 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1360 if (i < 32) {
1361 rev_id = (rev_id << 1) | (id_lo & 1);
1362 id_lo >>= 1;
1363 } else {
1364 rev_id = (rev_id << 1) | (id_hi & 1);
1365 id_hi >>= 1;
1366 }
1367 }
1368
1369 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1370 id_bit = rev_id & 1;
1371
1372 if (i % 4 == 0) {
1373 // Don't write row parity bit at start of parsing
1374 if (i)
1375 id = (id << 1) | r_parity;
1376 // Start counting parity for new row
1377 r_parity = id_bit;
1378 } else {
1379 // Count row parity
1380 r_parity ^= id_bit;
1381 }
1382
1383 // First elements in column?
1384 if (i < 4)
1385 // Fill out first elements
1386 c_parity[i] = id_bit;
1387 else
1388 // Count column parity
1389 c_parity[i % 4] ^= id_bit;
1390
1391 // Insert ID bit
1392 id = (id << 1) | id_bit;
1393 rev_id >>= 1;
1394 }
1395
1396 // Insert parity bit of last row
1397 id = (id << 1) | r_parity;
1398
1399 // Fill out column parity at the end of tag
1400 for (i = 0; i < 4; ++i)
1401 id = (id << 1) | c_parity[i];
1402
1403 // Add stop bit
1404 id <<= 1;
1405
1406 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1407 LED_D_ON();
1408
1409 // Write EM410x ID
1410 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1411 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1412
1413 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1414 if (card) {
1415 // Clock rate is stored in bits 8-15 of the card value
1416 clock = (card & 0xFF00) >> 8;
1417 Dbprintf("Clock rate: %d", clock);
1418 switch (clock)
1419 {
1420 case 32:
1421 clock = T55x7_BITRATE_RF_32;
1422 break;
1423 case 16:
1424 clock = T55x7_BITRATE_RF_16;
1425 break;
1426 case 0:
1427 // A value of 0 is assumed to be 64 for backwards-compatibility
1428 // Fall through...
1429 case 64:
1430 clock = T55x7_BITRATE_RF_64;
1431 break;
1432 default:
1433 Dbprintf("Invalid clock rate: %d", clock);
1434 return;
1435 }
1436
1437 // Writing configuration for T55x7 tag
1438 T55xxWriteBlock(clock |
1439 T55x7_MODULATION_MANCHESTER |
1440 2 << T55x7_MAXBLOCK_SHIFT,
1441 0, 0, 0);
1442 }
1443 else
1444 // Writing configuration for T5555(Q5) tag
1445 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1446 T5555_MODULATION_MANCHESTER |
1447 2 << T5555_MAXBLOCK_SHIFT,
1448 0, 0, 0);
1449
1450 LED_D_OFF();
1451 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1452 (uint32_t)(id >> 32), (uint32_t)id);
1453}
1454
1455// Clone Indala 64-bit tag by UID to T55x7
1456void CopyIndala64toT55x7(int hi, int lo)
1457{
1458
1459 //Program the 2 data blocks for supplied 64bit UID
1460 // and the block 0 for Indala64 format
1461 T55xxWriteBlock(hi,1,0,0);
1462 T55xxWriteBlock(lo,2,0,0);
1463 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1464 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1465 T55x7_MODULATION_PSK1 |
1466 2 << T55x7_MAXBLOCK_SHIFT,
1467 0, 0, 0);
1468 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1469 // T5567WriteBlock(0x603E1042,0);
1470
1471 DbpString("DONE!");
1472
1473}
1474
1475void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1476{
1477
1478 //Program the 7 data blocks for supplied 224bit UID
1479 // and the block 0 for Indala224 format
1480 T55xxWriteBlock(uid1,1,0,0);
1481 T55xxWriteBlock(uid2,2,0,0);
1482 T55xxWriteBlock(uid3,3,0,0);
1483 T55xxWriteBlock(uid4,4,0,0);
1484 T55xxWriteBlock(uid5,5,0,0);
1485 T55xxWriteBlock(uid6,6,0,0);
1486 T55xxWriteBlock(uid7,7,0,0);
1487 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1488 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1489 T55x7_MODULATION_PSK1 |
1490 7 << T55x7_MAXBLOCK_SHIFT,
1491 0,0,0);
1492 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1493 // T5567WriteBlock(0x603E10E2,0);
1494
1495 DbpString("DONE!");
1496
1497}
1498
1499
1500#define abs(x) ( ((x)<0) ? -(x) : (x) )
1501#define max(x,y) ( x<y ? y:x)
1502
1503int DemodPCF7931(uint8_t **outBlocks) {
1504 uint8_t BitStream[256];
1505 uint8_t Blocks[8][16];
1506 uint8_t *GraphBuffer = BigBuf_get_addr();
1507 int GraphTraceLen = BigBuf_max_traceLen();
1508 int i, j, lastval, bitidx, half_switch;
1509 int clock = 64;
1510 int tolerance = clock / 8;
1511 int pmc, block_done;
1512 int lc, warnings = 0;
1513 int num_blocks = 0;
1514 int lmin=128, lmax=128;
1515 uint8_t dir;
1516
1517 LFSetupFPGAForADC(95, true);
1518 DoAcquisition_default(0, 0);
1519
1520
1521 lmin = 64;
1522 lmax = 192;
1523
1524 i = 2;
1525
1526 /* Find first local max/min */
1527 if(GraphBuffer[1] > GraphBuffer[0]) {
1528 while(i < GraphTraceLen) {
1529 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1530 break;
1531 i++;
1532 }
1533 dir = 0;
1534 }
1535 else {
1536 while(i < GraphTraceLen) {
1537 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1538 break;
1539 i++;
1540 }
1541 dir = 1;
1542 }
1543
1544 lastval = i++;
1545 half_switch = 0;
1546 pmc = 0;
1547 block_done = 0;
1548
1549 for (bitidx = 0; i < GraphTraceLen; i++)
1550 {
1551 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1552 {
1553 lc = i - lastval;
1554 lastval = i;
1555
1556 // Switch depending on lc length:
1557 // Tolerance is 1/8 of clock rate (arbitrary)
1558 if (abs(lc-clock/4) < tolerance) {
1559 // 16T0
1560 if((i - pmc) == lc) { /* 16T0 was previous one */
1561 /* It's a PMC ! */
1562 i += (128+127+16+32+33+16)-1;
1563 lastval = i;
1564 pmc = 0;
1565 block_done = 1;
1566 }
1567 else {
1568 pmc = i;
1569 }
1570 } else if (abs(lc-clock/2) < tolerance) {
1571 // 32TO
1572 if((i - pmc) == lc) { /* 16T0 was previous one */
1573 /* It's a PMC ! */
1574 i += (128+127+16+32+33)-1;
1575 lastval = i;
1576 pmc = 0;
1577 block_done = 1;
1578 }
1579 else if(half_switch == 1) {
1580 BitStream[bitidx++] = 0;
1581 half_switch = 0;
1582 }
1583 else
1584 half_switch++;
1585 } else if (abs(lc-clock) < tolerance) {
1586 // 64TO
1587 BitStream[bitidx++] = 1;
1588 } else {
1589 // Error
1590 warnings++;
1591 if (warnings > 10)
1592 {
1593 Dbprintf("Error: too many detection errors, aborting.");
1594 return 0;
1595 }
1596 }
1597
1598 if(block_done == 1) {
1599 if(bitidx == 128) {
1600 for(j=0; j<16; j++) {
1601 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1602 64*BitStream[j*8+6]+
1603 32*BitStream[j*8+5]+
1604 16*BitStream[j*8+4]+
1605 8*BitStream[j*8+3]+
1606 4*BitStream[j*8+2]+
1607 2*BitStream[j*8+1]+
1608 BitStream[j*8];
1609 }
1610 num_blocks++;
1611 }
1612 bitidx = 0;
1613 block_done = 0;
1614 half_switch = 0;
1615 }
1616 if(i < GraphTraceLen)
1617 {
1618 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1619 else dir = 1;
1620 }
1621 }
1622 if(bitidx==255)
1623 bitidx=0;
1624 warnings = 0;
1625 if(num_blocks == 4) break;
1626 }
1627 memcpy(outBlocks, Blocks, 16*num_blocks);
1628 return num_blocks;
1629}
1630
1631int IsBlock0PCF7931(uint8_t *Block) {
1632 // Assume RFU means 0 :)
1633 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1634 return 1;
1635 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1636 return 1;
1637 return 0;
1638}
1639
1640int IsBlock1PCF7931(uint8_t *Block) {
1641 // Assume RFU means 0 :)
1642 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1643 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1644 return 1;
1645
1646 return 0;
1647}
1648
1649#define ALLOC 16
1650
1651void ReadPCF7931() {
1652 uint8_t Blocks[8][17];
1653 uint8_t tmpBlocks[4][16];
1654 int i, j, ind, ind2, n;
1655 int num_blocks = 0;
1656 int max_blocks = 8;
1657 int ident = 0;
1658 int error = 0;
1659 int tries = 0;
1660
1661 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1662
1663 do {
1664 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1665 n = DemodPCF7931((uint8_t**)tmpBlocks);
1666 if(!n)
1667 error++;
1668 if(error==10 && num_blocks == 0) {
1669 Dbprintf("Error, no tag or bad tag");
1670 return;
1671 }
1672 else if (tries==20 || error==10) {
1673 Dbprintf("Error reading the tag");
1674 Dbprintf("Here is the partial content");
1675 goto end;
1676 }
1677
1678 for(i=0; i<n; i++)
1679 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1680 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1681 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1682 if(!ident) {
1683 for(i=0; i<n; i++) {
1684 if(IsBlock0PCF7931(tmpBlocks[i])) {
1685 // Found block 0 ?
1686 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1687 // Found block 1!
1688 // \o/
1689 ident = 1;
1690 memcpy(Blocks[0], tmpBlocks[i], 16);
1691 Blocks[0][ALLOC] = 1;
1692 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1693 Blocks[1][ALLOC] = 1;
1694 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1695 // Debug print
1696 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1697 num_blocks = 2;
1698 // Handle following blocks
1699 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1700 if(j==n) j=0;
1701 if(j==i) break;
1702 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1703 Blocks[ind2][ALLOC] = 1;
1704 }
1705 break;
1706 }
1707 }
1708 }
1709 }
1710 else {
1711 for(i=0; i<n; i++) { // Look for identical block in known blocks
1712 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1713 for(j=0; j<max_blocks; j++) {
1714 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1715 // Found an identical block
1716 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1717 if(ind2 < 0)
1718 ind2 = max_blocks;
1719 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1720 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1721 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1722 Blocks[ind2][ALLOC] = 1;
1723 num_blocks++;
1724 if(num_blocks == max_blocks) goto end;
1725 }
1726 }
1727 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1728 if(ind2 > max_blocks)
1729 ind2 = 0;
1730 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1731 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1732 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1733 Blocks[ind2][ALLOC] = 1;
1734 num_blocks++;
1735 if(num_blocks == max_blocks) goto end;
1736 }
1737 }
1738 }
1739 }
1740 }
1741 }
1742 }
1743 tries++;
1744 if (BUTTON_PRESS()) return;
1745 } while (num_blocks != max_blocks);
1746 end:
1747 Dbprintf("-----------------------------------------");
1748 Dbprintf("Memory content:");
1749 Dbprintf("-----------------------------------------");
1750 for(i=0; i<max_blocks; i++) {
1751 if(Blocks[i][ALLOC]==1)
1752 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1753 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1754 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1755 else
1756 Dbprintf("<missing block %d>", i);
1757 }
1758 Dbprintf("-----------------------------------------");
1759
1760 return ;
1761}
1762
1763
1764//-----------------------------------
1765// EM4469 / EM4305 routines
1766//-----------------------------------
1767#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1768#define FWD_CMD_WRITE 0xA
1769#define FWD_CMD_READ 0x9
1770#define FWD_CMD_DISABLE 0x5
1771
1772
1773uint8_t forwardLink_data[64]; //array of forwarded bits
1774uint8_t * forward_ptr; //ptr for forward message preparation
1775uint8_t fwd_bit_sz; //forwardlink bit counter
1776uint8_t * fwd_write_ptr; //forwardlink bit pointer
1777
1778//====================================================================
1779// prepares command bits
1780// see EM4469 spec
1781//====================================================================
1782//--------------------------------------------------------------------
1783uint8_t Prepare_Cmd( uint8_t cmd ) {
1784 //--------------------------------------------------------------------
1785
1786 *forward_ptr++ = 0; //start bit
1787 *forward_ptr++ = 0; //second pause for 4050 code
1788
1789 *forward_ptr++ = cmd;
1790 cmd >>= 1;
1791 *forward_ptr++ = cmd;
1792 cmd >>= 1;
1793 *forward_ptr++ = cmd;
1794 cmd >>= 1;
1795 *forward_ptr++ = cmd;
1796
1797 return 6; //return number of emited bits
1798}
1799
1800//====================================================================
1801// prepares address bits
1802// see EM4469 spec
1803//====================================================================
1804
1805//--------------------------------------------------------------------
1806uint8_t Prepare_Addr( uint8_t addr ) {
1807 //--------------------------------------------------------------------
1808
1809 register uint8_t line_parity;
1810
1811 uint8_t i;
1812 line_parity = 0;
1813 for(i=0;i<6;i++) {
1814 *forward_ptr++ = addr;
1815 line_parity ^= addr;
1816 addr >>= 1;
1817 }
1818
1819 *forward_ptr++ = (line_parity & 1);
1820
1821 return 7; //return number of emited bits
1822}
1823
1824//====================================================================
1825// prepares data bits intreleaved with parity bits
1826// see EM4469 spec
1827//====================================================================
1828
1829//--------------------------------------------------------------------
1830uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1831 //--------------------------------------------------------------------
1832
1833 register uint8_t line_parity;
1834 register uint8_t column_parity;
1835 register uint8_t i, j;
1836 register uint16_t data;
1837
1838 data = data_low;
1839 column_parity = 0;
1840
1841 for(i=0; i<4; i++) {
1842 line_parity = 0;
1843 for(j=0; j<8; j++) {
1844 line_parity ^= data;
1845 column_parity ^= (data & 1) << j;
1846 *forward_ptr++ = data;
1847 data >>= 1;
1848 }
1849 *forward_ptr++ = line_parity;
1850 if(i == 1)
1851 data = data_hi;
1852 }
1853
1854 for(j=0; j<8; j++) {
1855 *forward_ptr++ = column_parity;
1856 column_parity >>= 1;
1857 }
1858 *forward_ptr = 0;
1859
1860 return 45; //return number of emited bits
1861}
1862
1863//====================================================================
1864// Forward Link send function
1865// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1866// fwd_bit_count set with number of bits to be sent
1867//====================================================================
1868void SendForward(uint8_t fwd_bit_count) {
1869
1870 fwd_write_ptr = forwardLink_data;
1871 fwd_bit_sz = fwd_bit_count;
1872
1873 LED_D_ON();
1874
1875 //Field on
1876 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1877 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1878 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1879
1880 // Give it a bit of time for the resonant antenna to settle.
1881 // And for the tag to fully power up
1882 SpinDelay(150);
1883
1884 // force 1st mod pulse (start gap must be longer for 4305)
1885 fwd_bit_sz--; //prepare next bit modulation
1886 fwd_write_ptr++;
1887 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1888 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1889 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1890 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1891 SpinDelayUs(16*8); //16 cycles on (8us each)
1892
1893 // now start writting
1894 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1895 if(((*fwd_write_ptr++) & 1) == 1)
1896 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1897 else {
1898 //These timings work for 4469/4269/4305 (with the 55*8 above)
1899 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1900 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1901 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1902 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1903 SpinDelayUs(9*8); //16 cycles on (8us each)
1904 }
1905 }
1906}
1907
1908void EM4xLogin(uint32_t Password) {
1909
1910 uint8_t fwd_bit_count;
1911
1912 forward_ptr = forwardLink_data;
1913 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1914 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1915
1916 SendForward(fwd_bit_count);
1917
1918 //Wait for command to complete
1919 SpinDelay(20);
1920
1921}
1922
1923void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1924
1925 uint8_t fwd_bit_count;
1926 uint8_t *dest = BigBuf_get_addr();
1927 int m=0, i=0;
1928
1929 //If password mode do login
1930 if (PwdMode == 1) EM4xLogin(Pwd);
1931
1932 forward_ptr = forwardLink_data;
1933 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1934 fwd_bit_count += Prepare_Addr( Address );
1935
1936 m = BigBuf_max_traceLen();
1937 // Clear destination buffer before sending the command
1938 memset(dest, 128, m);
1939 // Connect the A/D to the peak-detected low-frequency path.
1940 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1941 // Now set up the SSC to get the ADC samples that are now streaming at us.
1942 FpgaSetupSsc();
1943
1944 SendForward(fwd_bit_count);
1945
1946 // Now do the acquisition
1947 i = 0;
1948 for(;;) {
1949 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1950 AT91C_BASE_SSC->SSC_THR = 0x43;
1951 }
1952 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1953 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1954 i++;
1955 if (i >= m) break;
1956 }
1957 }
1958 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1959 LED_D_OFF();
1960}
1961
1962void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1963
1964 uint8_t fwd_bit_count;
1965
1966 //If password mode do login
1967 if (PwdMode == 1) EM4xLogin(Pwd);
1968
1969 forward_ptr = forwardLink_data;
1970 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1971 fwd_bit_count += Prepare_Addr( Address );
1972 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1973
1974 SendForward(fwd_bit_count);
1975
1976 //Wait for write to complete
1977 SpinDelay(20);
1978 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1979 LED_D_OFF();
1980}
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