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fix my understanding of REQB vs WUPB
[proxmark3-svn] / fpga / tests / tb_lf_edge_detect.v
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3b2fee43 1//-----------------------------------------------------------------------------
2// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
3//
4// This code is licensed to you under the terms of the GNU GPL, version 2 or,
5// at your option, any later version. See the LICENSE.txt file for the text of
6// the license.
7//-----------------------------------------------------------------------------
8// testbench for lf_edge_detect
9`include "lf_edge_detect.v"
10
11`define FIN "tb_tmp/data.filtered.gold"
12`define FOUT_MIN "tb_tmp/data.min"
13`define FOUT_MAX "tb_tmp/data.max"
14`define FOUT_STATE "tb_tmp/data.state"
15`define FOUT_TOGGLE "tb_tmp/data.toggle"
16`define FOUT_HIGH "tb_tmp/data.high"
17`define FOUT_HIGHZ "tb_tmp/data.highz"
18`define FOUT_LOWZ "tb_tmp/data.lowz"
19`define FOUT_LOW "tb_tmp/data.low"
20
21module lf_edge_detect_tb;
22
23 integer fin, fout_state, fout_toggle;
24 integer fout_high, fout_highz, fout_lowz, fout_low, fout_min, fout_max;
25 integer r;
26
27 reg clk = 0;
28 reg [7:0] adc_d;
29 wire adc_clk;
30 wire data_rdy;
31 wire edge_state;
32 wire edge_toggle;
33
34 wire [7:0] high_threshold;
35 wire [7:0] highz_threshold;
36 wire [7:0] lowz_threshold;
37 wire [7:0] low_threshold;
38 wire [7:0] max;
39 wire [7:0] min;
40
41 initial
42 begin
43 clk = 0;
44 fin = $fopen(`FIN, "r");
45 if (!fin) begin
46 $display("ERROR: can't open the data file");
47 $finish;
48 end
49 fout_min = $fopen(`FOUT_MIN, "w+");
50 fout_max = $fopen(`FOUT_MAX, "w+");
51 fout_state = $fopen(`FOUT_STATE, "w+");
52 fout_toggle = $fopen(`FOUT_TOGGLE, "w+");
53 fout_high = $fopen(`FOUT_HIGH, "w+");
54 fout_highz = $fopen(`FOUT_HIGHZ, "w+");
55 fout_lowz = $fopen(`FOUT_LOWZ, "w+");
56 fout_low = $fopen(`FOUT_LOW, "w+");
57 if (!$feof(fin))
58 adc_d = $fgetc(fin); // read the first value
59 end
60
61 always
62 # 1 clk = !clk;
63
64 // input
65 initial
66 begin
67 while (!$feof(fin)) begin
68 @(negedge clk) adc_d <= $fgetc(fin);
69 end
70
71 if ($feof(fin))
72 begin
73 # 3 $fclose(fin);
74 $fclose(fout_state);
75 $fclose(fout_toggle);
76 $fclose(fout_high);
77 $fclose(fout_highz);
78 $fclose(fout_lowz);
79 $fclose(fout_low);
80 $fclose(fout_min);
81 $fclose(fout_max);
82 $finish;
83 end
84 end
85
86 initial
87 begin
88 // $monitor("%d\t S: %b, E: %b", $time, edge_state, edge_toggle);
89 end
90
91 // output
92 always @(negedge clk)
93 if ($time > 2) begin
94 r = $fputc(min, fout_min);
95 r = $fputc(max, fout_max);
96 r = $fputc(edge_state, fout_state);
97 r = $fputc(edge_toggle, fout_toggle);
98 r = $fputc(high_threshold, fout_high);
99 r = $fputc(highz_threshold, fout_highz);
100 r = $fputc(lowz_threshold, fout_lowz);
101 r = $fputc(low_threshold, fout_low);
102 end
103
104 // module to test
105 lf_edge_detect detect(clk, adc_d, 8'd127,
106 max, min,
107 high_threshold, highz_threshold,
108 lowz_threshold, low_threshold,
109 edge_state, edge_toggle);
110
111endmodule
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