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Add mifare crypto trace decryption utility
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7cc204bf 1//-----------------------------------------------------------------------------
2// The FPGA is responsible for interfacing between the A/D, the coil drivers,
3// and the ARM. In the low-frequency modes it passes the data straight
4// through, so that the ARM gets raw A/D samples over the SSP. In the high-
5// frequency modes, the FPGA might perform some demodulation first, to
6// reduce the amount of data that we must send to the ARM.
7//
8// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
9// could be improved.
10//
11// Jonathan Westhues, March 2006
12// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
fa57f6e1 13// iZsh <izsh at fail0verflow.com>, June 2014
7cc204bf 14//-----------------------------------------------------------------------------
15
16`include "hi_read_tx.v"
17`include "hi_read_rx_xcorr.v"
18`include "hi_simulate.v"
19`include "hi_iso14443a.v"
20`include "util.v"
21
22module fpga_hf(
23 input spck, output miso, input mosi, input ncs,
24 input pck0, input ck_1356meg, input ck_1356megb,
25 output pwr_lo, output pwr_hi,
26 output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
27 input [7:0] adc_d, output adc_clk, output adc_noe,
28 output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
29 input cross_hi, input cross_lo,
30 output dbg
31);
32
33//-----------------------------------------------------------------------------
34// The SPI receiver. This sets up the configuration word, which the rest of
35// the logic looks at to determine how to connect the A/D and the coil
36// drivers (i.e., which section gets it). Also assign some symbolic names
37// to the configuration bits, for use below.
38//-----------------------------------------------------------------------------
39
40reg [15:0] shift_reg;
41reg [7:0] conf_word;
42
43// We switch modes between transmitting to the 13.56 MHz tag and receiving
44// from it, which means that we must make sure that we can do so without
45// glitching, or else we will glitch the transmitted carrier.
46always @(posedge ncs)
47begin
48 case(shift_reg[15:12])
49 4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
50 endcase
51end
52
53always @(posedge spck)
54begin
55 if(~ncs)
56 begin
57 shift_reg[15:1] <= shift_reg[14:0];
58 shift_reg[0] <= mosi;
59 end
60end
61
62wire [2:0] major_mode;
63assign major_mode = conf_word[7:5];
64
65// For the high-frequency transmit configuration: modulation depth, either
66// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
67// some fraction of the buffers)
68wire hi_read_tx_shallow_modulation = conf_word[0];
69
da586b17 70// For the high-frequency receive correlator: frequency against which to
71// correlate.
72wire hi_read_rx_xcorr_848 = conf_word[0];
73// and whether to drive the coil (reader) or just short it (snooper)
7cc204bf 74wire hi_read_rx_xcorr_snoop = conf_word[1];
75
7cc204bf 76// For the high-frequency simulated tag: what kind of modulation to use.
77wire [2:0] hi_simulate_mod_type = conf_word[2:0];
78
79//-----------------------------------------------------------------------------
80// And then we instantiate the modules corresponding to each of the FPGA's
81// major modes, and use muxes to connect the outputs of the active mode to
82// the output pins.
83//-----------------------------------------------------------------------------
84
85hi_read_tx ht(
86 pck0, ck_1356meg, ck_1356megb,
87 ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
88 adc_d, ht_adc_clk,
89 ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
90 cross_hi, cross_lo,
91 ht_dbg,
92 hi_read_tx_shallow_modulation
93);
94
95hi_read_rx_xcorr hrxc(
96 pck0, ck_1356meg, ck_1356megb,
97 hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
98 adc_d, hrxc_adc_clk,
99 hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
100 cross_hi, cross_lo,
101 hrxc_dbg,
da586b17 102 hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop
7cc204bf 103);
104
105hi_simulate hs(
106 pck0, ck_1356meg, ck_1356megb,
107 hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
108 adc_d, hs_adc_clk,
109 hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
110 cross_hi, cross_lo,
111 hs_dbg,
112 hi_simulate_mod_type
113);
114
115hi_iso14443a hisn(
116 pck0, ck_1356meg, ck_1356megb,
117 hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
118 adc_d, hisn_adc_clk,
119 hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
120 cross_hi, cross_lo,
121 hisn_dbg,
122 hi_simulate_mod_type
123);
124
125// Major modes:
126
127// 000 -- HF reader, transmitting to tag; modulation depth selectable
128// 001 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
129// 010 -- HF simulated tag
130// 011 -- HF ISO14443-A
131// 111 -- everything off
132
133mux8 mux_ssp_clk (major_mode, ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0);
134mux8 mux_ssp_din (major_mode, ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0);
135mux8 mux_ssp_frame (major_mode, ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0);
136mux8 mux_pwr_oe1 (major_mode, pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0);
137mux8 mux_pwr_oe2 (major_mode, pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0);
138mux8 mux_pwr_oe3 (major_mode, pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0);
139mux8 mux_pwr_oe4 (major_mode, pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0);
140mux8 mux_pwr_lo (major_mode, pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0);
141mux8 mux_pwr_hi (major_mode, pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0);
142mux8 mux_adc_clk (major_mode, adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0);
143mux8 mux_dbg (major_mode, dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, 1'b0, 1'b0, 1'b0, 1'b0);
144
145// In all modes, let the ADC's outputs be enabled.
146assign adc_noe = 1'b0;
147
148endmodule
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