Legic Tag Simulator (#666)
[proxmark3-svn] / fpga / hi_simulate.v
CommitLineData
ba06a4b6 1//-----------------------------------------------------------------------------
2// Pretend to be an ISO 14443 tag. We will do this by alternately short-
3// circuiting and open-circuiting the antenna coil, with the tri-state
4// pins.
5//
6// We communicate over the SSP, as a bitstream (i.e., might as well be
7// unframed, though we still generate the word sync signal). The output
8// (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
9// -> ARM) is us using the A/D as a fancy comparator; this is with
10// (software-added) hysteresis, to undo the high-pass filter.
11//
12// At this point only Type A is implemented. This means that we are using a
13// bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
14// things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
15//
16// Jonathan Westhues, October 2006
17//-----------------------------------------------------------------------------
18
19module hi_simulate(
20 pck0, ck_1356meg, ck_1356megb,
21 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
22 adc_d, adc_clk,
23 ssp_frame, ssp_din, ssp_dout, ssp_clk,
24 cross_hi, cross_lo,
25 dbg,
26 mod_type
27);
28 input pck0, ck_1356meg, ck_1356megb;
29 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
30 input [7:0] adc_d;
31 output adc_clk;
32 input ssp_dout;
33 output ssp_frame, ssp_din, ssp_clk;
34 input cross_hi, cross_lo;
35 output dbg;
36 input [2:0] mod_type;
37
38// Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can
39// always be low.
40assign pwr_hi = 1'b0;
41assign pwr_lo = 1'b0;
42
43// The comparator with hysteresis on the output from the peak detector.
44reg after_hysteresis;
45assign adc_clk = ck_1356meg;
46
47always @(negedge adc_clk)
48begin
49 if(& adc_d[7:5]) after_hysteresis = 1'b1;
50 else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;
51end
52
645c960f 53
1b902aa0
A
54// Divide 13.56 MHz to produce various frequencies for SSP_CLK
55// and modulation. 11 bits allow for factors of up to /128.
645c960f
MHS
56reg [10:0] ssp_clk_divider;
57
ba06a4b6 58always @(posedge adc_clk)
59 ssp_clk_divider <= (ssp_clk_divider + 1);
645c960f
MHS
60
61reg ssp_clk;
1b902aa0 62
645c960f
MHS
63always @(negedge adc_clk)
64begin
645c960f 65 if(mod_type == 3'b101)
1b902aa0
A
66 // Get bit every at 53KHz (every 8th carrier bit of 424kHz)
67 ssp_clk <= ssp_clk_divider[7];
68 else if(mod_type == 3'b010)
69 // Get next bit at 212kHz
70 ssp_clk <= ssp_clk_divider[5];
645c960f 71 else
1b902aa0
A
72 // Get next bit at 424Khz
73 ssp_clk <= ssp_clk_divider[4];
645c960f
MHS
74end
75
76
ba06a4b6 77// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
78// this is arbitrary, because it's just a bitstream.
79// One nasty issue, though: I can't make it work with both rx and tx at
80// once. The phase wrt ssp_clk must be changed. TODO to find out why
81// that is and make a better fix.
82reg [2:0] ssp_frame_divider_to_arm;
83always @(posedge ssp_clk)
84 ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
85reg [2:0] ssp_frame_divider_from_arm;
86always @(negedge ssp_clk)
87 ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
88
645c960f 89
1b902aa0 90reg ssp_frame;
ba06a4b6 91always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
92 if(mod_type == 3'b000) // not modulating, so listening, to ARM
93 ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
94 else
1b902aa0 95 ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
ba06a4b6 96
97// Synchronize up the after-hysteresis signal, to produce DIN.
98reg ssp_din;
99always @(posedge ssp_clk)
100 ssp_din = after_hysteresis;
101
1b902aa0 102// Modulating carrier frequency is fc/64 (212kHz) to fc/16 (848kHz). Reuse ssp_clk divider for that.
ba06a4b6 103reg modulating_carrier;
104always @(mod_type or ssp_clk or ssp_dout)
105 if(mod_type == 3'b000)
106 modulating_carrier <= 1'b0; // no modulation
107 else if(mod_type == 3'b001)
108 modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
109 else if(mod_type == 3'b010)
1b902aa0 110 modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
645c960f 111 else if(mod_type == 3'b100 || mod_type == 3'b101)
1b902aa0 112 modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
ba06a4b6 113 else
114 modulating_carrier <= 1'b0; // yet unused
115
116// This one is all LF, so doesn't matter
117assign pwr_oe2 = modulating_carrier;
118
119// Toggle only one of these, since we are already producing much deeper
120// modulation than a real tag would.
121assign pwr_oe1 = modulating_carrier;
122assign pwr_oe4 = modulating_carrier;
123
124// This one is always on, so that we can watch the carrier.
125assign pwr_oe3 = 1'b0;
126
1b902aa0 127assign dbg = ssp_din;
ba06a4b6 128
129endmodule
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