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[proxmark3-svn] / armsrc / lfops.c
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e09f21fa 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
9//-----------------------------------------------------------------------------
10
11#include "proxmark3.h"
12#include "apps.h"
13#include "util.h"
14#include "hitag2.h"
15#include "crc16.h"
16#include "string.h"
17#include "lfdemod.h"
18#include "lfsampling.h"
f7048dc8 19#include "usb_cdc.h"
e09f21fa 20
21
22/**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
30{
31
32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
34
35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
71
72 // now do the read
73 DoAcquisition_config(false);
74}
75
76
77
78/* blank r/w tag data stream
79...0000000000000000 01111111
801010101010101010101010101010101010101010101010101010101010101010
810011010010100001
8201111111
83101010101010101[0]000...
84
85[5555fe852c5555555555555555fe0000]
86*/
87void ReadTItag(void)
88{
89 // some hardcoded initial params
90 // when we read a TI tag we sample the zerocross line at 2Mhz
91 // TI tags modulate a 1 as 16 cycles of 123.2Khz
92 // TI tags modulate a 0 as 16 cycles of 134.2Khz
93 #define FSAMPLE 2000000
94 #define FREQLO 123200
95 #define FREQHI 134200
96
97 signed char *dest = (signed char *)BigBuf_get_addr();
98 uint16_t n = BigBuf_max_traceLen();
99 // 128 bit shift register [shift3:shift2:shift1:shift0]
100 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
101
102 int i, cycles=0, samples=0;
103 // how many sample points fit in 16 cycles of each frequency
104 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
105 // when to tell if we're close enough to one freq or another
106 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
107
108 // TI tags charge at 134.2Khz
109 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
111
112 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
113 // connects to SSP_DIN and the SSP_DOUT logic level controls
114 // whether we're modulating the antenna (high)
115 // or listening to the antenna (low)
116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
117
118 // get TI tag data into the buffer
119 AcquireTiType();
120
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
122
123 for (i=0; i<n-1; i++) {
124 // count cycles by looking for lo to hi zero crossings
125 if ( (dest[i]<0) && (dest[i+1]>0) ) {
126 cycles++;
127 // after 16 cycles, measure the frequency
128 if (cycles>15) {
129 cycles=0;
130 samples=i-samples; // number of samples in these 16 cycles
131
132 // TI bits are coming to us lsb first so shift them
133 // right through our 128 bit right shift register
134 shift0 = (shift0>>1) | (shift1 << 31);
135 shift1 = (shift1>>1) | (shift2 << 31);
136 shift2 = (shift2>>1) | (shift3 << 31);
137 shift3 >>= 1;
138
139 // check if the cycles fall close to the number
140 // expected for either the low or high frequency
141 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
142 // low frequency represents a 1
143 shift3 |= (1<<31);
144 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
145 // high frequency represents a 0
146 } else {
147 // probably detected a gay waveform or noise
148 // use this as gaydar or discard shift register and start again
149 shift3 = shift2 = shift1 = shift0 = 0;
150 }
151 samples = i;
152
153 // for each bit we receive, test if we've detected a valid tag
154
155 // if we see 17 zeroes followed by 6 ones, we might have a tag
156 // remember the bits are backwards
157 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
158 // if start and end bytes match, we have a tag so break out of the loop
159 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
160 cycles = 0xF0B; //use this as a flag (ugly but whatever)
161 break;
162 }
163 }
164 }
165 }
166 }
167
168 // if flag is set we have a tag
169 if (cycles!=0xF0B) {
170 DbpString("Info: No valid tag detected.");
171 } else {
172 // put 64 bit data into shift1 and shift0
173 shift0 = (shift0>>24) | (shift1 << 8);
174 shift1 = (shift1>>24) | (shift2 << 8);
175
176 // align 16 bit crc into lower half of shift2
177 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
178
179 // if r/w tag, check ident match
180 if (shift3 & (1<<15) ) {
181 DbpString("Info: TI tag is rewriteable");
182 // only 15 bits compare, last bit of ident is not valid
183 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
184 DbpString("Error: Ident mismatch!");
185 } else {
186 DbpString("Info: TI tag ident is valid");
187 }
188 } else {
189 DbpString("Info: TI tag is readonly");
190 }
191
192 // WARNING the order of the bytes in which we calc crc below needs checking
193 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
194 // bytes in reverse or something
195 // calculate CRC
196 uint32_t crc=0;
197
198 crc = update_crc16(crc, (shift0)&0xff);
199 crc = update_crc16(crc, (shift0>>8)&0xff);
200 crc = update_crc16(crc, (shift0>>16)&0xff);
201 crc = update_crc16(crc, (shift0>>24)&0xff);
202 crc = update_crc16(crc, (shift1)&0xff);
203 crc = update_crc16(crc, (shift1>>8)&0xff);
204 crc = update_crc16(crc, (shift1>>16)&0xff);
205 crc = update_crc16(crc, (shift1>>24)&0xff);
206
207 Dbprintf("Info: Tag data: %x%08x, crc=%x",
208 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
209 if (crc != (shift2&0xffff)) {
210 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
211 } else {
212 DbpString("Info: CRC is good");
213 }
214 }
215}
216
217void WriteTIbyte(uint8_t b)
218{
219 int i = 0;
220
221 // modulate 8 bits out to the antenna
222 for (i=0; i<8; i++)
223 {
224 if (b&(1<<i)) {
225 // stop modulating antenna
226 LOW(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 // modulate antenna
229 HIGH(GPIO_SSC_DOUT);
230 SpinDelayUs(1000);
231 } else {
232 // stop modulating antenna
233 LOW(GPIO_SSC_DOUT);
234 SpinDelayUs(300);
235 // modulate antenna
236 HIGH(GPIO_SSC_DOUT);
237 SpinDelayUs(1700);
238 }
239 }
240}
241
242void AcquireTiType(void)
243{
244 int i, j, n;
245 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
246 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
247 #define TIBUFLEN 1250
248
249 // clear buffer
250 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
251 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
252
253 // Set up the synchronous serial port
254 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
255 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
256
257 // steal this pin from the SSP and use it to control the modulation
258 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
259 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
260
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
262 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
263
264 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
265 // 48/2 = 24 MHz clock must be divided by 12
266 AT91C_BASE_SSC->SSC_CMR = 12;
267
268 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
269 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
270 AT91C_BASE_SSC->SSC_TCMR = 0;
271 AT91C_BASE_SSC->SSC_TFMR = 0;
272
273 LED_D_ON();
274
275 // modulate antenna
276 HIGH(GPIO_SSC_DOUT);
277
278 // Charge TI tag for 50ms.
279 SpinDelay(50);
280
281 // stop modulating antenna and listen
282 LOW(GPIO_SSC_DOUT);
283
284 LED_D_OFF();
285
286 i = 0;
287 for(;;) {
288 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
289 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
290 i++; if(i >= TIBUFLEN) break;
291 }
292 WDT_HIT();
293 }
294
295 // return stolen pin to SSP
296 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
297 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
298
299 char *dest = (char *)BigBuf_get_addr();
300 n = TIBUFLEN*32;
301 // unpack buffer
302 for (i=TIBUFLEN-1; i>=0; i--) {
303 for (j=0; j<32; j++) {
304 if(BigBuf[i] & (1 << j)) {
305 dest[--n] = 1;
306 } else {
307 dest[--n] = -1;
308 }
309 }
310 }
311}
312
313// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
314// if crc provided, it will be written with the data verbatim (even if bogus)
315// if not provided a valid crc will be computed from the data and written.
316void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
317{
318 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
319 if(crc == 0) {
320 crc = update_crc16(crc, (idlo)&0xff);
321 crc = update_crc16(crc, (idlo>>8)&0xff);
322 crc = update_crc16(crc, (idlo>>16)&0xff);
323 crc = update_crc16(crc, (idlo>>24)&0xff);
324 crc = update_crc16(crc, (idhi)&0xff);
325 crc = update_crc16(crc, (idhi>>8)&0xff);
326 crc = update_crc16(crc, (idhi>>16)&0xff);
327 crc = update_crc16(crc, (idhi>>24)&0xff);
328 }
329 Dbprintf("Writing to tag: %x%08x, crc=%x",
330 (unsigned int) idhi, (unsigned int) idlo, crc);
331
332 // TI tags charge at 134.2Khz
333 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
334 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
335 // connects to SSP_DIN and the SSP_DOUT logic level controls
336 // whether we're modulating the antenna (high)
337 // or listening to the antenna (low)
338 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
339 LED_A_ON();
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 // writing algorithm:
346 // a high bit consists of a field off for 1ms and field on for 1ms
347 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
348 // initiate a charge time of 50ms (field on) then immediately start writing bits
349 // start by writing 0xBB (keyword) and 0xEB (password)
350 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
351 // finally end with 0x0300 (write frame)
352 // all data is sent lsb firts
353 // finish with 15ms programming time
354
355 // modulate antenna
356 HIGH(GPIO_SSC_DOUT);
357 SpinDelay(50); // charge time
358
359 WriteTIbyte(0xbb); // keyword
360 WriteTIbyte(0xeb); // password
361 WriteTIbyte( (idlo )&0xff );
362 WriteTIbyte( (idlo>>8 )&0xff );
363 WriteTIbyte( (idlo>>16)&0xff );
364 WriteTIbyte( (idlo>>24)&0xff );
365 WriteTIbyte( (idhi )&0xff );
366 WriteTIbyte( (idhi>>8 )&0xff );
367 WriteTIbyte( (idhi>>16)&0xff );
368 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
369 WriteTIbyte( (crc )&0xff ); // crc lo
370 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
371 WriteTIbyte(0x00); // write frame lo
372 WriteTIbyte(0x03); // write frame hi
373 HIGH(GPIO_SSC_DOUT);
374 SpinDelay(50); // programming time
375
376 LED_A_OFF();
377
378 // get TI tag data into the buffer
379 AcquireTiType();
380
381 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
382 DbpString("Now use tiread to check");
383}
384
385void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
386{
387 int i;
388 uint8_t *tab = BigBuf_get_addr();
389
390 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
391 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
392
393 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
394
395 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
396 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
397
398 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
399 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
400
401 i = 0;
402 for(;;) {
403 //wait until SSC_CLK goes HIGH
404 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
f7048dc8 405 if(BUTTON_PRESS() || usb_poll()) {
e09f21fa 406 DbpString("Stopped");
407 return;
408 }
409 WDT_HIT();
410 }
411 if (ledcontrol)
412 LED_D_ON();
413
414 if(tab[i])
415 OPEN_COIL();
416 else
417 SHORT_COIL();
418
419 if (ledcontrol)
420 LED_D_OFF();
421 //wait until SSC_CLK goes LOW
422 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
423 if(BUTTON_PRESS()) {
424 DbpString("Stopped");
425 return;
426 }
427 WDT_HIT();
428 }
429
430 i++;
431 if(i == period) {
432
433 i = 0;
434 if (gap) {
435 SHORT_COIL();
436 SpinDelayUs(gap);
437 }
438 }
439 }
440}
441
e09f21fa 442#define DEBUG_FRAME_CONTENTS 1
443void SimulateTagLowFrequencyBidir(int divisor, int t0)
444{
445}
446
447// compose fc/8 fc/10 waveform (FSK2)
448static void fc(int c, int *n)
449{
450 uint8_t *dest = BigBuf_get_addr();
451 int idx;
452
453 // for when we want an fc8 pattern every 4 logical bits
454 if(c==0) {
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=1;
458 dest[((*n)++)]=1;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 dest[((*n)++)]=0;
462 dest[((*n)++)]=0;
463 }
464
712ebfa6 465 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
e09f21fa 466 if(c==8) {
467 for (idx=0; idx<6; idx++) {
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=1;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 dest[((*n)++)]=0;
476 }
477 }
478
712ebfa6 479 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
e09f21fa 480 if(c==10) {
481 for (idx=0; idx<5; idx++) {
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=1;
486 dest[((*n)++)]=1;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 dest[((*n)++)]=0;
491 dest[((*n)++)]=0;
492 }
493 }
494}
495// compose fc/X fc/Y waveform (FSKx)
712ebfa6 496static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 497{
498 uint8_t *dest = BigBuf_get_addr();
712ebfa6 499 uint8_t halfFC = fc/2;
500 uint8_t wavesPerClock = clock/fc;
501 uint8_t mod = clock % fc; //modifier
502 uint8_t modAdj = fc/mod; //how often to apply modifier
503 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
e09f21fa 504 // loop through clock - step field clock
712ebfa6 505 for (uint8_t idx=0; idx < wavesPerClock; idx++){
506 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
507 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
508 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
509 *n += fc;
e09f21fa 510 }
511 if (mod>0) (*modCnt)++;
512 if ((mod>0) && modAdjOk){ //fsk2
513 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
712ebfa6 514 memset(dest+(*n), 0, fc-halfFC);
515 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
516 *n += fc;
e09f21fa 517 }
518 }
e09f21fa 519 if (mod>0 && !modAdjOk){ //fsk1
712ebfa6 520 memset(dest+(*n), 0, mod-(mod/2));
521 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
522 *n += mod;
e09f21fa 523 }
524}
525
526// prepare a waveform pattern in the buffer based on the ID given then
527// simulate a HID tag until the button is pressed
528void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
529{
530 int n=0, i=0;
531 /*
532 HID tag bitstream format
533 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
534 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
535 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
536 A fc8 is inserted before every 4 bits
537 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
538 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
539 */
540
541 if (hi>0xFFF) {
78f5b1a7 542 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
e09f21fa 543 return;
544 }
545 fc(0,&n);
546 // special start of frame marker containing invalid bit sequences
547 fc(8, &n); fc(8, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549 fc(10, &n); fc(10, &n); // invalid
550 fc(8, &n); fc(10, &n); // logical 0
551
552 WDT_HIT();
553 // manchester encode bits 43 to 32
554 for (i=11; i>=0; i--) {
555 if ((i%4)==3) fc(0,&n);
556 if ((hi>>i)&1) {
557 fc(10, &n); fc(8, &n); // low-high transition
558 } else {
559 fc(8, &n); fc(10, &n); // high-low transition
560 }
561 }
562
563 WDT_HIT();
564 // manchester encode bits 31 to 0
565 for (i=31; i>=0; i--) {
566 if ((i%4)==3) fc(0,&n);
567 if ((lo>>i)&1) {
568 fc(10, &n); fc(8, &n); // low-high transition
569 } else {
570 fc(8, &n); fc(10, &n); // high-low transition
571 }
572 }
573
574 if (ledcontrol)
575 LED_A_ON();
576 SimulateTagLowFrequency(n, 0, ledcontrol);
577
578 if (ledcontrol)
579 LED_A_OFF();
580}
581
582// prepare a waveform pattern in the buffer based on the ID given then
583// simulate a FSK tag until the button is pressed
584// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
585void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
586{
587 int ledcontrol=1;
588 int n=0, i=0;
589 uint8_t fcHigh = arg1 >> 8;
590 uint8_t fcLow = arg1 & 0xFF;
591 uint16_t modCnt = 0;
e09f21fa 592 uint8_t clk = arg2 & 0xFF;
593 uint8_t invert = (arg2 >> 8) & 1;
712ebfa6 594
e09f21fa 595 for (i=0; i<size; i++){
596 if (BitStream[i] == invert){
597 fcAll(fcLow, &n, clk, &modCnt);
598 } else {
599 fcAll(fcHigh, &n, clk, &modCnt);
600 }
601 }
602 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
712ebfa6 603 /*Dbprintf("DEBUG: First 32:");
e09f21fa 604 uint8_t *dest = BigBuf_get_addr();
605 i=0;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
607 i+=16;
608 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
78f5b1a7 609 */
e09f21fa 610 if (ledcontrol)
611 LED_A_ON();
712ebfa6 612
78f5b1a7 613 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 614
615 if (ledcontrol)
616 LED_A_OFF();
617}
618
619// compose ask waveform for one bit(ASK)
620static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
621{
622 uint8_t *dest = BigBuf_get_addr();
712ebfa6 623 uint8_t halfClk = clock/2;
e09f21fa 624 // c = current bit 1 or 0
b41534d1 625 if (manchester==1){
712ebfa6 626 memset(dest+(*n), c, halfClk);
627 memset(dest+(*n) + halfClk, c^1, halfClk);
e09f21fa 628 } else {
712ebfa6 629 memset(dest+(*n), c, clock);
e09f21fa 630 }
712ebfa6 631 *n += clock;
e09f21fa 632}
633
b41534d1 634static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
635{
636 uint8_t *dest = BigBuf_get_addr();
637 uint8_t halfClk = clock/2;
638 if (c){
639 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
640 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
641 } else {
642 memset(dest+(*n), c ^ *phase, clock);
643 *phase ^= 1;
644 }
645
646}
647
e09f21fa 648// args clock, ask/man or askraw, invert, transmission separator
649void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
650{
651 int ledcontrol = 1;
652 int n=0, i=0;
653 uint8_t clk = (arg1 >> 8) & 0xFF;
b41534d1 654 uint8_t encoding = arg1 & 1;
e09f21fa 655 uint8_t separator = arg2 & 1;
656 uint8_t invert = (arg2 >> 8) & 1;
b41534d1 657
658 if (encoding==2){ //biphase
659 uint8_t phase=0;
660 for (i=0; i<size; i++){
661 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
662 }
663 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
664 for (i=0; i<size; i++){
665 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
666 }
667 }
668 } else { // ask/manchester || ask/raw
ada339a1 669 for (i=0; i<size; i++){
b41534d1 670 askSimBit(BitStream[i]^invert, &n, clk, encoding);
671 }
672 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
673 for (i=0; i<size; i++){
674 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
675 }
ada339a1 676 }
677 }
b41534d1 678
712ebfa6 679 if (separator==1) Dbprintf("sorry but separator option not yet available");
e09f21fa 680
b41534d1 681 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
e09f21fa 682 //DEBUG
712ebfa6 683 //Dbprintf("First 32:");
e09f21fa 684 //uint8_t *dest = BigBuf_get_addr();
685 //i=0;
686 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
687 //i+=16;
688 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 689
690 if (ledcontrol)
691 LED_A_ON();
712ebfa6 692
78f5b1a7 693 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 694
695 if (ledcontrol)
696 LED_A_OFF();
697}
698
699//carrier can be 2,4 or 8
700static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
701{
702 uint8_t *dest = BigBuf_get_addr();
712ebfa6 703 uint8_t halfWave = waveLen/2;
704 //uint8_t idx;
e09f21fa 705 int i = 0;
706 if (phaseChg){
707 // write phase change
712ebfa6 708 memset(dest+(*n), *curPhase^1, halfWave);
709 memset(dest+(*n) + halfWave, *curPhase, halfWave);
710 *n += waveLen;
e09f21fa 711 *curPhase ^= 1;
712ebfa6 712 i += waveLen;
e09f21fa 713 }
714 //write each normal clock wave for the clock duration
715 for (; i < clk; i+=waveLen){
712ebfa6 716 memset(dest+(*n), *curPhase, halfWave);
717 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
718 *n += waveLen;
e09f21fa 719 }
720}
721
722// args clock, carrier, invert,
723void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
724{
725 int ledcontrol=1;
726 int n=0, i=0;
727 uint8_t clk = arg1 >> 8;
728 uint8_t carrier = arg1 & 0xFF;
729 uint8_t invert = arg2 & 0xFF;
78f5b1a7 730 uint8_t curPhase = 0;
e09f21fa 731 for (i=0; i<size; i++){
732 if (BitStream[i] == curPhase){
733 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
734 } else {
735 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
736 }
737 }
738 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
712ebfa6 739 //Dbprintf("DEBUG: First 32:");
740 //uint8_t *dest = BigBuf_get_addr();
741 //i=0;
742 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
743 //i+=16;
744 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 745
746 if (ledcontrol)
747 LED_A_ON();
78f5b1a7 748 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 749
750 if (ledcontrol)
751 LED_A_OFF();
752}
753
754// loop to get raw HID waveform then FSK demodulate the TAG ID from it
755void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
756{
757 uint8_t *dest = BigBuf_get_addr();
758 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
759 size_t size = 0;
760 uint32_t hi2=0, hi=0, lo=0;
761 int idx=0;
762 // Configure to go in 125Khz listen mode
763 LFSetupFPGAForADC(95, true);
764
765 while(!BUTTON_PRESS()) {
766
767 WDT_HIT();
768 if (ledcontrol) LED_A_ON();
769
770 DoAcquisition_default(-1,true);
771 // FSK demodulator
772 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
773 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
774
775 if (idx>0 && lo>0){
776 // final loop, go over previously decoded manchester data and decode into usable tag ID
777 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
778 if (hi2 != 0){ //extra large HID tags
779 Dbprintf("TAG ID: %x%08x%08x (%d)",
780 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
781 }else { //standard HID tags <38 bits
782 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
783 uint8_t bitlen = 0;
784 uint32_t fc = 0;
785 uint32_t cardnum = 0;
786 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
787 uint32_t lo2=0;
788 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
789 uint8_t idx3 = 1;
790 while(lo2 > 1){ //find last bit set to 1 (format len bit)
791 lo2=lo2 >> 1;
792 idx3++;
793 }
794 bitlen = idx3+19;
795 fc =0;
796 cardnum=0;
797 if(bitlen == 26){
798 cardnum = (lo>>1)&0xFFFF;
799 fc = (lo>>17)&0xFF;
800 }
801 if(bitlen == 37){
802 cardnum = (lo>>1)&0x7FFFF;
803 fc = ((hi&0xF)<<12)|(lo>>20);
804 }
805 if(bitlen == 34){
806 cardnum = (lo>>1)&0xFFFF;
807 fc= ((hi&1)<<15)|(lo>>17);
808 }
809 if(bitlen == 35){
810 cardnum = (lo>>1)&0xFFFFF;
811 fc = ((hi&1)<<11)|(lo>>21);
812 }
813 }
814 else { //if bit 38 is not set then 37 bit format is used
815 bitlen= 37;
816 fc =0;
817 cardnum=0;
818 if(bitlen==37){
819 cardnum = (lo>>1)&0x7FFFF;
820 fc = ((hi&0xF)<<12)|(lo>>20);
821 }
822 }
823 //Dbprintf("TAG ID: %x%08x (%d)",
824 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
825 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
826 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
827 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
828 }
829 if (findone){
830 if (ledcontrol) LED_A_OFF();
831 *high = hi;
832 *low = lo;
833 return;
834 }
835 // reset
836 hi2 = hi = lo = 0;
837 }
838 WDT_HIT();
839 }
840 DbpString("Stopped");
841 if (ledcontrol) LED_A_OFF();
842}
843
844void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
845{
846 uint8_t *dest = BigBuf_get_addr();
847
b41534d1 848 size_t size=0, idx=0;
e09f21fa 849 int clk=0, invert=0, errCnt=0, maxErr=20;
b41534d1 850 uint32_t hi=0;
e09f21fa 851 uint64_t lo=0;
852 // Configure to go in 125Khz listen mode
853 LFSetupFPGAForADC(95, true);
854
855 while(!BUTTON_PRESS()) {
856
857 WDT_HIT();
858 if (ledcontrol) LED_A_ON();
859
b41534d1 860 DoAcquisition_default(-1,true);
861 size = BigBuf_max_traceLen();
e09f21fa 862 //Dbprintf("DEBUG: Buffer got");
b41534d1 863 //askdemod and manchester decode
864 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
e09f21fa 865 //Dbprintf("DEBUG: ASK Got");
866 WDT_HIT();
867
868 if (errCnt>=0){
b41534d1 869 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
e09f21fa 870 //Dbprintf("DEBUG: EM GOT");
b41534d1 871 if (errCnt){
872 if (size>64){
873 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
874 hi,
875 (uint32_t)(lo>>32),
876 (uint32_t)lo,
877 (uint32_t)(lo&0xFFFF),
878 (uint32_t)((lo>>16LL) & 0xFF),
879 (uint32_t)(lo & 0xFFFFFF));
880 } else {
881 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
882 (uint32_t)(lo>>32),
883 (uint32_t)lo,
884 (uint32_t)(lo&0xFFFF),
885 (uint32_t)((lo>>16LL) & 0xFF),
886 (uint32_t)(lo & 0xFFFFFF));
887 }
e09f21fa 888 }
889 if (findone){
890 if (ledcontrol) LED_A_OFF();
891 *high=lo>>32;
892 *low=lo & 0xFFFFFFFF;
893 return;
894 }
895 } else{
896 //Dbprintf("DEBUG: No Tag");
897 }
898 WDT_HIT();
899 lo = 0;
900 clk=0;
901 invert=0;
902 errCnt=0;
903 size=0;
904 }
905 DbpString("Stopped");
906 if (ledcontrol) LED_A_OFF();
907}
908
909void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
910{
911 uint8_t *dest = BigBuf_get_addr();
912 int idx=0;
913 uint32_t code=0, code2=0;
914 uint8_t version=0;
915 uint8_t facilitycode=0;
916 uint16_t number=0;
917 // Configure to go in 125Khz listen mode
918 LFSetupFPGAForADC(95, true);
919
920 while(!BUTTON_PRESS()) {
921 WDT_HIT();
922 if (ledcontrol) LED_A_ON();
923 DoAcquisition_default(-1,true);
924 //fskdemod and get start index
925 WDT_HIT();
926 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
927 if (idx>0){
928 //valid tag found
929
930 //Index map
931 //0 10 20 30 40 50 60
932 //| | | | | | |
933 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
934 //-----------------------------------------------------------------------------
935 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
936 //
937 //XSF(version)facility:codeone+codetwo
938 //Handle the data
939 if(findone){ //only print binary if we are doing one
940 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
941 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
942 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
943 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
944 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
945 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
946 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
947 }
948 code = bytebits_to_byte(dest+idx,32);
949 code2 = bytebits_to_byte(dest+idx+32,32);
950 version = bytebits_to_byte(dest+idx+27,8); //14,4
951 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
952 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
953
954 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
955 // if we're only looking for one tag
956 if (findone){
957 if (ledcontrol) LED_A_OFF();
958 //LED_A_OFF();
959 *high=code;
960 *low=code2;
961 return;
962 }
963 code=code2=0;
964 version=facilitycode=0;
965 number=0;
966 idx=0;
967 }
968 WDT_HIT();
969 }
970 DbpString("Stopped");
971 if (ledcontrol) LED_A_OFF();
972}
973
974/*------------------------------
975 * T5555/T5557/T5567 routines
976 *------------------------------
977 */
978
979/* T55x7 configuration register definitions */
980#define T55x7_POR_DELAY 0x00000001
981#define T55x7_ST_TERMINATOR 0x00000008
982#define T55x7_PWD 0x00000010
983#define T55x7_MAXBLOCK_SHIFT 5
984#define T55x7_AOR 0x00000200
985#define T55x7_PSKCF_RF_2 0
986#define T55x7_PSKCF_RF_4 0x00000400
987#define T55x7_PSKCF_RF_8 0x00000800
988#define T55x7_MODULATION_DIRECT 0
989#define T55x7_MODULATION_PSK1 0x00001000
990#define T55x7_MODULATION_PSK2 0x00002000
991#define T55x7_MODULATION_PSK3 0x00003000
992#define T55x7_MODULATION_FSK1 0x00004000
993#define T55x7_MODULATION_FSK2 0x00005000
994#define T55x7_MODULATION_FSK1a 0x00006000
995#define T55x7_MODULATION_FSK2a 0x00007000
996#define T55x7_MODULATION_MANCHESTER 0x00008000
997#define T55x7_MODULATION_BIPHASE 0x00010000
998#define T55x7_BITRATE_RF_8 0
999#define T55x7_BITRATE_RF_16 0x00040000
1000#define T55x7_BITRATE_RF_32 0x00080000
1001#define T55x7_BITRATE_RF_40 0x000C0000
1002#define T55x7_BITRATE_RF_50 0x00100000
1003#define T55x7_BITRATE_RF_64 0x00140000
1004#define T55x7_BITRATE_RF_100 0x00180000
1005#define T55x7_BITRATE_RF_128 0x001C0000
1006
1007/* T5555 (Q5) configuration register definitions */
1008#define T5555_ST_TERMINATOR 0x00000001
1009#define T5555_MAXBLOCK_SHIFT 0x00000001
1010#define T5555_MODULATION_MANCHESTER 0
1011#define T5555_MODULATION_PSK1 0x00000010
1012#define T5555_MODULATION_PSK2 0x00000020
1013#define T5555_MODULATION_PSK3 0x00000030
1014#define T5555_MODULATION_FSK1 0x00000040
1015#define T5555_MODULATION_FSK2 0x00000050
1016#define T5555_MODULATION_BIPHASE 0x00000060
1017#define T5555_MODULATION_DIRECT 0x00000070
1018#define T5555_INVERT_OUTPUT 0x00000080
1019#define T5555_PSK_RF_2 0
1020#define T5555_PSK_RF_4 0x00000100
1021#define T5555_PSK_RF_8 0x00000200
1022#define T5555_USE_PWD 0x00000400
1023#define T5555_USE_AOR 0x00000800
1024#define T5555_BITRATE_SHIFT 12
1025#define T5555_FAST_WRITE 0x00004000
1026#define T5555_PAGE_SELECT 0x00008000
1027
1028/*
1029 * Relevant times in microsecond
1030 * To compensate antenna falling times shorten the write times
1031 * and enlarge the gap ones.
1032 */
1033#define START_GAP 250
1034#define WRITE_GAP 160
1035#define WRITE_0 144 // 192
1036#define WRITE_1 400 // 432 for T55x7; 448 for E5550
1037
1038// Write one bit to card
1039void T55xxWriteBit(int bit)
1040{
1041 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1042 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1043 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1044 if (bit == 0)
1045 SpinDelayUs(WRITE_0);
1046 else
1047 SpinDelayUs(WRITE_1);
1048 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1049 SpinDelayUs(WRITE_GAP);
1050}
1051
1052// Write one card block in page 0, no lock
1053void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1054{
1055 //unsigned int i; //enio adjustment 12/10/14
1056 uint32_t i;
1057
1058 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1059 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1060 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1061
1062 // Give it a bit of time for the resonant antenna to settle.
1063 // And for the tag to fully power up
1064 SpinDelay(150);
1065
1066 // Now start writting
1067 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1068 SpinDelayUs(START_GAP);
1069
1070 // Opcode
1071 T55xxWriteBit(1);
1072 T55xxWriteBit(0); //Page 0
1073 if (PwdMode == 1){
1074 // Pwd
1075 for (i = 0x80000000; i != 0; i >>= 1)
1076 T55xxWriteBit(Pwd & i);
1077 }
1078 // Lock bit
1079 T55xxWriteBit(0);
1080
1081 // Data
1082 for (i = 0x80000000; i != 0; i >>= 1)
1083 T55xxWriteBit(Data & i);
1084
1085 // Block
1086 for (i = 0x04; i != 0; i >>= 1)
1087 T55xxWriteBit(Block & i);
1088
1089 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1090 // so wait a little more)
1091 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1092 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1093 SpinDelay(20);
1094 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1095}
1096
1097// Read one card block in page 0
1098void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1099{
1100 uint8_t *dest = BigBuf_get_addr();
1101 //int m=0, i=0; //enio adjustment 12/10/14
1102 uint32_t m=0, i=0;
1103 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1104 m = BigBuf_max_traceLen();
1105 // Clear destination buffer before sending the command
1106 memset(dest, 128, m);
1107 // Connect the A/D to the peak-detected low-frequency path.
1108 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1109 // Now set up the SSC to get the ADC samples that are now streaming at us.
1110 FpgaSetupSsc();
1111
1112 LED_D_ON();
1113 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1114 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1115
1116 // Give it a bit of time for the resonant antenna to settle.
1117 // And for the tag to fully power up
1118 SpinDelay(150);
1119
1120 // Now start writting
1121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1122 SpinDelayUs(START_GAP);
1123
1124 // Opcode
1125 T55xxWriteBit(1);
1126 T55xxWriteBit(0); //Page 0
1127 if (PwdMode == 1){
1128 // Pwd
1129 for (i = 0x80000000; i != 0; i >>= 1)
1130 T55xxWriteBit(Pwd & i);
1131 }
1132 // Lock bit
1133 T55xxWriteBit(0);
1134 // Block
1135 for (i = 0x04; i != 0; i >>= 1)
1136 T55xxWriteBit(Block & i);
1137
1138 // Turn field on to read the response
1139 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1140 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1141
1142 // Now do the acquisition
1143 i = 0;
1144 for(;;) {
1145 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1146 AT91C_BASE_SSC->SSC_THR = 0x43;
1147 }
1148 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1149 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1150 // we don't care about actual value, only if it's more or less than a
1151 // threshold essentially we capture zero crossings for later analysis
1152 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1153 i++;
1154 if (i >= m) break;
1155 }
1156 }
1157
1158 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1159 LED_D_OFF();
1160 DbpString("DONE!");
1161}
1162
1163// Read card traceability data (page 1)
1164void T55xxReadTrace(void){
1165 uint8_t *dest = BigBuf_get_addr();
1166 int m=0, i=0;
1167
1168 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1169 m = BigBuf_max_traceLen();
1170 // Clear destination buffer before sending the command
1171 memset(dest, 128, m);
1172 // Connect the A/D to the peak-detected low-frequency path.
1173 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1174 // Now set up the SSC to get the ADC samples that are now streaming at us.
1175 FpgaSetupSsc();
1176
1177 LED_D_ON();
1178 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1179 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1180
1181 // Give it a bit of time for the resonant antenna to settle.
1182 // And for the tag to fully power up
1183 SpinDelay(150);
1184
1185 // Now start writting
1186 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1187 SpinDelayUs(START_GAP);
1188
1189 // Opcode
1190 T55xxWriteBit(1);
1191 T55xxWriteBit(1); //Page 1
1192
1193 // Turn field on to read the response
1194 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1195 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1196
1197 // Now do the acquisition
1198 i = 0;
1199 for(;;) {
1200 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1201 AT91C_BASE_SSC->SSC_THR = 0x43;
1202 }
1203 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1204 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1205 i++;
1206 if (i >= m) break;
1207 }
1208 }
1209
1210 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1211 LED_D_OFF();
1212 DbpString("DONE!");
1213}
1214
1215/*-------------- Cloning routines -----------*/
1216// Copy HID id to card and setup block 0 config
1217void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1218{
1219 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1220 int last_block = 0;
1221
1222 if (longFMT){
1223 // Ensure no more than 84 bits supplied
1224 if (hi2>0xFFFFF) {
1225 DbpString("Tags can only have 84 bits.");
1226 return;
1227 }
1228 // Build the 6 data blocks for supplied 84bit ID
1229 last_block = 6;
1230 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1231 for (int i=0;i<4;i++) {
1232 if (hi2 & (1<<(19-i)))
1233 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1234 else
1235 data1 |= (1<<((3-i)*2)); // 0 -> 01
1236 }
1237
1238 data2 = 0;
1239 for (int i=0;i<16;i++) {
1240 if (hi2 & (1<<(15-i)))
1241 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1242 else
1243 data2 |= (1<<((15-i)*2)); // 0 -> 01
1244 }
1245
1246 data3 = 0;
1247 for (int i=0;i<16;i++) {
1248 if (hi & (1<<(31-i)))
1249 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1250 else
1251 data3 |= (1<<((15-i)*2)); // 0 -> 01
1252 }
1253
1254 data4 = 0;
1255 for (int i=0;i<16;i++) {
1256 if (hi & (1<<(15-i)))
1257 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1258 else
1259 data4 |= (1<<((15-i)*2)); // 0 -> 01
1260 }
1261
1262 data5 = 0;
1263 for (int i=0;i<16;i++) {
1264 if (lo & (1<<(31-i)))
1265 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1266 else
1267 data5 |= (1<<((15-i)*2)); // 0 -> 01
1268 }
1269
1270 data6 = 0;
1271 for (int i=0;i<16;i++) {
1272 if (lo & (1<<(15-i)))
1273 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1274 else
1275 data6 |= (1<<((15-i)*2)); // 0 -> 01
1276 }
1277 }
1278 else {
1279 // Ensure no more than 44 bits supplied
1280 if (hi>0xFFF) {
1281 DbpString("Tags can only have 44 bits.");
1282 return;
1283 }
1284
1285 // Build the 3 data blocks for supplied 44bit ID
1286 last_block = 3;
1287
1288 data1 = 0x1D000000; // load preamble
1289
1290 for (int i=0;i<12;i++) {
1291 if (hi & (1<<(11-i)))
1292 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1293 else
1294 data1 |= (1<<((11-i)*2)); // 0 -> 01
1295 }
1296
1297 data2 = 0;
1298 for (int i=0;i<16;i++) {
1299 if (lo & (1<<(31-i)))
1300 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1301 else
1302 data2 |= (1<<((15-i)*2)); // 0 -> 01
1303 }
1304
1305 data3 = 0;
1306 for (int i=0;i<16;i++) {
1307 if (lo & (1<<(15-i)))
1308 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1309 else
1310 data3 |= (1<<((15-i)*2)); // 0 -> 01
1311 }
1312 }
1313
1314 LED_D_ON();
1315 // Program the data blocks for supplied ID
1316 // and the block 0 for HID format
1317 T55xxWriteBlock(data1,1,0,0);
1318 T55xxWriteBlock(data2,2,0,0);
1319 T55xxWriteBlock(data3,3,0,0);
1320
1321 if (longFMT) { // if long format there are 6 blocks
1322 T55xxWriteBlock(data4,4,0,0);
1323 T55xxWriteBlock(data5,5,0,0);
1324 T55xxWriteBlock(data6,6,0,0);
1325 }
1326
1327 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1328 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1329 T55x7_MODULATION_FSK2a |
1330 last_block << T55x7_MAXBLOCK_SHIFT,
1331 0,0,0);
1332
1333 LED_D_OFF();
1334
1335 DbpString("DONE!");
1336}
1337
1338void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1339{
1340 int data1=0, data2=0; //up to six blocks for long format
1341
1342 data1 = hi; // load preamble
1343 data2 = lo;
1344
1345 LED_D_ON();
1346 // Program the data blocks for supplied ID
1347 // and the block 0 for HID format
1348 T55xxWriteBlock(data1,1,0,0);
1349 T55xxWriteBlock(data2,2,0,0);
1350
1351 //Config Block
1352 T55xxWriteBlock(0x00147040,0,0,0);
1353 LED_D_OFF();
1354
1355 DbpString("DONE!");
1356}
1357
1358// Define 9bit header for EM410x tags
1359#define EM410X_HEADER 0x1FF
1360#define EM410X_ID_LENGTH 40
1361
1362void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1363{
1364 int i, id_bit;
1365 uint64_t id = EM410X_HEADER;
1366 uint64_t rev_id = 0; // reversed ID
1367 int c_parity[4]; // column parity
1368 int r_parity = 0; // row parity
1369 uint32_t clock = 0;
1370
1371 // Reverse ID bits given as parameter (for simpler operations)
1372 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1373 if (i < 32) {
1374 rev_id = (rev_id << 1) | (id_lo & 1);
1375 id_lo >>= 1;
1376 } else {
1377 rev_id = (rev_id << 1) | (id_hi & 1);
1378 id_hi >>= 1;
1379 }
1380 }
1381
1382 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1383 id_bit = rev_id & 1;
1384
1385 if (i % 4 == 0) {
1386 // Don't write row parity bit at start of parsing
1387 if (i)
1388 id = (id << 1) | r_parity;
1389 // Start counting parity for new row
1390 r_parity = id_bit;
1391 } else {
1392 // Count row parity
1393 r_parity ^= id_bit;
1394 }
1395
1396 // First elements in column?
1397 if (i < 4)
1398 // Fill out first elements
1399 c_parity[i] = id_bit;
1400 else
1401 // Count column parity
1402 c_parity[i % 4] ^= id_bit;
1403
1404 // Insert ID bit
1405 id = (id << 1) | id_bit;
1406 rev_id >>= 1;
1407 }
1408
1409 // Insert parity bit of last row
1410 id = (id << 1) | r_parity;
1411
1412 // Fill out column parity at the end of tag
1413 for (i = 0; i < 4; ++i)
1414 id = (id << 1) | c_parity[i];
1415
1416 // Add stop bit
1417 id <<= 1;
1418
1419 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1420 LED_D_ON();
1421
1422 // Write EM410x ID
1423 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1424 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1425
1426 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1427 if (card) {
1428 // Clock rate is stored in bits 8-15 of the card value
1429 clock = (card & 0xFF00) >> 8;
1430 Dbprintf("Clock rate: %d", clock);
1431 switch (clock)
1432 {
1433 case 32:
1434 clock = T55x7_BITRATE_RF_32;
1435 break;
1436 case 16:
1437 clock = T55x7_BITRATE_RF_16;
1438 break;
1439 case 0:
1440 // A value of 0 is assumed to be 64 for backwards-compatibility
1441 // Fall through...
1442 case 64:
1443 clock = T55x7_BITRATE_RF_64;
1444 break;
1445 default:
1446 Dbprintf("Invalid clock rate: %d", clock);
1447 return;
1448 }
1449
1450 // Writing configuration for T55x7 tag
1451 T55xxWriteBlock(clock |
1452 T55x7_MODULATION_MANCHESTER |
1453 2 << T55x7_MAXBLOCK_SHIFT,
1454 0, 0, 0);
1455 }
1456 else
1457 // Writing configuration for T5555(Q5) tag
1458 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1459 T5555_MODULATION_MANCHESTER |
1460 2 << T5555_MAXBLOCK_SHIFT,
1461 0, 0, 0);
1462
1463 LED_D_OFF();
1464 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1465 (uint32_t)(id >> 32), (uint32_t)id);
1466}
1467
1468// Clone Indala 64-bit tag by UID to T55x7
1469void CopyIndala64toT55x7(int hi, int lo)
1470{
1471
1472 //Program the 2 data blocks for supplied 64bit UID
1473 // and the block 0 for Indala64 format
1474 T55xxWriteBlock(hi,1,0,0);
1475 T55xxWriteBlock(lo,2,0,0);
1476 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1477 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1478 T55x7_MODULATION_PSK1 |
1479 2 << T55x7_MAXBLOCK_SHIFT,
1480 0, 0, 0);
1481 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1482 // T5567WriteBlock(0x603E1042,0);
1483
1484 DbpString("DONE!");
1485
1486}
1487
1488void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1489{
1490
1491 //Program the 7 data blocks for supplied 224bit UID
1492 // and the block 0 for Indala224 format
1493 T55xxWriteBlock(uid1,1,0,0);
1494 T55xxWriteBlock(uid2,2,0,0);
1495 T55xxWriteBlock(uid3,3,0,0);
1496 T55xxWriteBlock(uid4,4,0,0);
1497 T55xxWriteBlock(uid5,5,0,0);
1498 T55xxWriteBlock(uid6,6,0,0);
1499 T55xxWriteBlock(uid7,7,0,0);
1500 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1501 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1502 T55x7_MODULATION_PSK1 |
1503 7 << T55x7_MAXBLOCK_SHIFT,
1504 0,0,0);
1505 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1506 // T5567WriteBlock(0x603E10E2,0);
1507
1508 DbpString("DONE!");
1509
1510}
1511
1512
1513#define abs(x) ( ((x)<0) ? -(x) : (x) )
1514#define max(x,y) ( x<y ? y:x)
1515
1516int DemodPCF7931(uint8_t **outBlocks) {
1517 uint8_t BitStream[256];
1518 uint8_t Blocks[8][16];
1519 uint8_t *GraphBuffer = BigBuf_get_addr();
1520 int GraphTraceLen = BigBuf_max_traceLen();
1521 int i, j, lastval, bitidx, half_switch;
1522 int clock = 64;
1523 int tolerance = clock / 8;
1524 int pmc, block_done;
1525 int lc, warnings = 0;
1526 int num_blocks = 0;
1527 int lmin=128, lmax=128;
1528 uint8_t dir;
1529
1530 LFSetupFPGAForADC(95, true);
1531 DoAcquisition_default(0, 0);
1532
1533
1534 lmin = 64;
1535 lmax = 192;
1536
1537 i = 2;
1538
1539 /* Find first local max/min */
1540 if(GraphBuffer[1] > GraphBuffer[0]) {
1541 while(i < GraphTraceLen) {
1542 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1543 break;
1544 i++;
1545 }
1546 dir = 0;
1547 }
1548 else {
1549 while(i < GraphTraceLen) {
1550 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1551 break;
1552 i++;
1553 }
1554 dir = 1;
1555 }
1556
1557 lastval = i++;
1558 half_switch = 0;
1559 pmc = 0;
1560 block_done = 0;
1561
1562 for (bitidx = 0; i < GraphTraceLen; i++)
1563 {
1564 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1565 {
1566 lc = i - lastval;
1567 lastval = i;
1568
1569 // Switch depending on lc length:
1570 // Tolerance is 1/8 of clock rate (arbitrary)
1571 if (abs(lc-clock/4) < tolerance) {
1572 // 16T0
1573 if((i - pmc) == lc) { /* 16T0 was previous one */
1574 /* It's a PMC ! */
1575 i += (128+127+16+32+33+16)-1;
1576 lastval = i;
1577 pmc = 0;
1578 block_done = 1;
1579 }
1580 else {
1581 pmc = i;
1582 }
1583 } else if (abs(lc-clock/2) < tolerance) {
1584 // 32TO
1585 if((i - pmc) == lc) { /* 16T0 was previous one */
1586 /* It's a PMC ! */
1587 i += (128+127+16+32+33)-1;
1588 lastval = i;
1589 pmc = 0;
1590 block_done = 1;
1591 }
1592 else if(half_switch == 1) {
1593 BitStream[bitidx++] = 0;
1594 half_switch = 0;
1595 }
1596 else
1597 half_switch++;
1598 } else if (abs(lc-clock) < tolerance) {
1599 // 64TO
1600 BitStream[bitidx++] = 1;
1601 } else {
1602 // Error
1603 warnings++;
1604 if (warnings > 10)
1605 {
1606 Dbprintf("Error: too many detection errors, aborting.");
1607 return 0;
1608 }
1609 }
1610
1611 if(block_done == 1) {
1612 if(bitidx == 128) {
1613 for(j=0; j<16; j++) {
1614 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1615 64*BitStream[j*8+6]+
1616 32*BitStream[j*8+5]+
1617 16*BitStream[j*8+4]+
1618 8*BitStream[j*8+3]+
1619 4*BitStream[j*8+2]+
1620 2*BitStream[j*8+1]+
1621 BitStream[j*8];
1622 }
1623 num_blocks++;
1624 }
1625 bitidx = 0;
1626 block_done = 0;
1627 half_switch = 0;
1628 }
1629 if(i < GraphTraceLen)
1630 {
1631 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1632 else dir = 1;
1633 }
1634 }
1635 if(bitidx==255)
1636 bitidx=0;
1637 warnings = 0;
1638 if(num_blocks == 4) break;
1639 }
1640 memcpy(outBlocks, Blocks, 16*num_blocks);
1641 return num_blocks;
1642}
1643
1644int IsBlock0PCF7931(uint8_t *Block) {
1645 // Assume RFU means 0 :)
1646 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1647 return 1;
1648 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1649 return 1;
1650 return 0;
1651}
1652
1653int IsBlock1PCF7931(uint8_t *Block) {
1654 // Assume RFU means 0 :)
1655 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1656 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1657 return 1;
1658
1659 return 0;
1660}
1661
1662#define ALLOC 16
1663
1664void ReadPCF7931() {
1665 uint8_t Blocks[8][17];
1666 uint8_t tmpBlocks[4][16];
1667 int i, j, ind, ind2, n;
1668 int num_blocks = 0;
1669 int max_blocks = 8;
1670 int ident = 0;
1671 int error = 0;
1672 int tries = 0;
1673
1674 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1675
1676 do {
1677 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1678 n = DemodPCF7931((uint8_t**)tmpBlocks);
1679 if(!n)
1680 error++;
1681 if(error==10 && num_blocks == 0) {
1682 Dbprintf("Error, no tag or bad tag");
1683 return;
1684 }
1685 else if (tries==20 || error==10) {
1686 Dbprintf("Error reading the tag");
1687 Dbprintf("Here is the partial content");
1688 goto end;
1689 }
1690
1691 for(i=0; i<n; i++)
1692 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1693 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1694 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1695 if(!ident) {
1696 for(i=0; i<n; i++) {
1697 if(IsBlock0PCF7931(tmpBlocks[i])) {
1698 // Found block 0 ?
1699 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1700 // Found block 1!
1701 // \o/
1702 ident = 1;
1703 memcpy(Blocks[0], tmpBlocks[i], 16);
1704 Blocks[0][ALLOC] = 1;
1705 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1706 Blocks[1][ALLOC] = 1;
1707 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1708 // Debug print
1709 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1710 num_blocks = 2;
1711 // Handle following blocks
1712 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1713 if(j==n) j=0;
1714 if(j==i) break;
1715 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1716 Blocks[ind2][ALLOC] = 1;
1717 }
1718 break;
1719 }
1720 }
1721 }
1722 }
1723 else {
1724 for(i=0; i<n; i++) { // Look for identical block in known blocks
1725 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1726 for(j=0; j<max_blocks; j++) {
1727 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1728 // Found an identical block
1729 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1730 if(ind2 < 0)
1731 ind2 = max_blocks;
1732 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1733 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1734 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1735 Blocks[ind2][ALLOC] = 1;
1736 num_blocks++;
1737 if(num_blocks == max_blocks) goto end;
1738 }
1739 }
1740 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1741 if(ind2 > max_blocks)
1742 ind2 = 0;
1743 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1744 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1745 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1746 Blocks[ind2][ALLOC] = 1;
1747 num_blocks++;
1748 if(num_blocks == max_blocks) goto end;
1749 }
1750 }
1751 }
1752 }
1753 }
1754 }
1755 }
1756 tries++;
1757 if (BUTTON_PRESS()) return;
1758 } while (num_blocks != max_blocks);
1759 end:
1760 Dbprintf("-----------------------------------------");
1761 Dbprintf("Memory content:");
1762 Dbprintf("-----------------------------------------");
1763 for(i=0; i<max_blocks; i++) {
1764 if(Blocks[i][ALLOC]==1)
1765 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1766 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1767 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1768 else
1769 Dbprintf("<missing block %d>", i);
1770 }
1771 Dbprintf("-----------------------------------------");
1772
1773 return ;
1774}
1775
1776
1777//-----------------------------------
1778// EM4469 / EM4305 routines
1779//-----------------------------------
1780#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1781#define FWD_CMD_WRITE 0xA
1782#define FWD_CMD_READ 0x9
1783#define FWD_CMD_DISABLE 0x5
1784
1785
1786uint8_t forwardLink_data[64]; //array of forwarded bits
1787uint8_t * forward_ptr; //ptr for forward message preparation
1788uint8_t fwd_bit_sz; //forwardlink bit counter
1789uint8_t * fwd_write_ptr; //forwardlink bit pointer
1790
1791//====================================================================
1792// prepares command bits
1793// see EM4469 spec
1794//====================================================================
1795//--------------------------------------------------------------------
1796uint8_t Prepare_Cmd( uint8_t cmd ) {
1797 //--------------------------------------------------------------------
1798
1799 *forward_ptr++ = 0; //start bit
1800 *forward_ptr++ = 0; //second pause for 4050 code
1801
1802 *forward_ptr++ = cmd;
1803 cmd >>= 1;
1804 *forward_ptr++ = cmd;
1805 cmd >>= 1;
1806 *forward_ptr++ = cmd;
1807 cmd >>= 1;
1808 *forward_ptr++ = cmd;
1809
1810 return 6; //return number of emited bits
1811}
1812
1813//====================================================================
1814// prepares address bits
1815// see EM4469 spec
1816//====================================================================
1817
1818//--------------------------------------------------------------------
1819uint8_t Prepare_Addr( uint8_t addr ) {
1820 //--------------------------------------------------------------------
1821
1822 register uint8_t line_parity;
1823
1824 uint8_t i;
1825 line_parity = 0;
1826 for(i=0;i<6;i++) {
1827 *forward_ptr++ = addr;
1828 line_parity ^= addr;
1829 addr >>= 1;
1830 }
1831
1832 *forward_ptr++ = (line_parity & 1);
1833
1834 return 7; //return number of emited bits
1835}
1836
1837//====================================================================
1838// prepares data bits intreleaved with parity bits
1839// see EM4469 spec
1840//====================================================================
1841
1842//--------------------------------------------------------------------
1843uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1844 //--------------------------------------------------------------------
1845
1846 register uint8_t line_parity;
1847 register uint8_t column_parity;
1848 register uint8_t i, j;
1849 register uint16_t data;
1850
1851 data = data_low;
1852 column_parity = 0;
1853
1854 for(i=0; i<4; i++) {
1855 line_parity = 0;
1856 for(j=0; j<8; j++) {
1857 line_parity ^= data;
1858 column_parity ^= (data & 1) << j;
1859 *forward_ptr++ = data;
1860 data >>= 1;
1861 }
1862 *forward_ptr++ = line_parity;
1863 if(i == 1)
1864 data = data_hi;
1865 }
1866
1867 for(j=0; j<8; j++) {
1868 *forward_ptr++ = column_parity;
1869 column_parity >>= 1;
1870 }
1871 *forward_ptr = 0;
1872
1873 return 45; //return number of emited bits
1874}
1875
1876//====================================================================
1877// Forward Link send function
1878// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1879// fwd_bit_count set with number of bits to be sent
1880//====================================================================
1881void SendForward(uint8_t fwd_bit_count) {
1882
1883 fwd_write_ptr = forwardLink_data;
1884 fwd_bit_sz = fwd_bit_count;
1885
1886 LED_D_ON();
1887
1888 //Field on
1889 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1890 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1891 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1892
1893 // Give it a bit of time for the resonant antenna to settle.
1894 // And for the tag to fully power up
1895 SpinDelay(150);
1896
1897 // force 1st mod pulse (start gap must be longer for 4305)
1898 fwd_bit_sz--; //prepare next bit modulation
1899 fwd_write_ptr++;
1900 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1901 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1902 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1903 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1904 SpinDelayUs(16*8); //16 cycles on (8us each)
1905
1906 // now start writting
1907 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1908 if(((*fwd_write_ptr++) & 1) == 1)
1909 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1910 else {
1911 //These timings work for 4469/4269/4305 (with the 55*8 above)
1912 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1913 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1914 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1915 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1916 SpinDelayUs(9*8); //16 cycles on (8us each)
1917 }
1918 }
1919}
1920
1921void EM4xLogin(uint32_t Password) {
1922
1923 uint8_t fwd_bit_count;
1924
1925 forward_ptr = forwardLink_data;
1926 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1927 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1928
1929 SendForward(fwd_bit_count);
1930
1931 //Wait for command to complete
1932 SpinDelay(20);
1933
1934}
1935
1936void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1937
1938 uint8_t fwd_bit_count;
1939 uint8_t *dest = BigBuf_get_addr();
1940 int m=0, i=0;
1941
1942 //If password mode do login
1943 if (PwdMode == 1) EM4xLogin(Pwd);
1944
1945 forward_ptr = forwardLink_data;
1946 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1947 fwd_bit_count += Prepare_Addr( Address );
1948
1949 m = BigBuf_max_traceLen();
1950 // Clear destination buffer before sending the command
1951 memset(dest, 128, m);
1952 // Connect the A/D to the peak-detected low-frequency path.
1953 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1954 // Now set up the SSC to get the ADC samples that are now streaming at us.
1955 FpgaSetupSsc();
1956
1957 SendForward(fwd_bit_count);
1958
1959 // Now do the acquisition
1960 i = 0;
1961 for(;;) {
1962 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1963 AT91C_BASE_SSC->SSC_THR = 0x43;
1964 }
1965 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1966 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1967 i++;
1968 if (i >= m) break;
1969 }
1970 }
1971 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1972 LED_D_OFF();
1973}
1974
1975void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1976
1977 uint8_t fwd_bit_count;
1978
1979 //If password mode do login
1980 if (PwdMode == 1) EM4xLogin(Pwd);
1981
1982 forward_ptr = forwardLink_data;
1983 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1984 fwd_bit_count += Prepare_Addr( Address );
1985 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1986
1987 SendForward(fwd_bit_count);
1988
1989 //Wait for write to complete
1990 SpinDelay(20);
1991 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1992 LED_D_OFF();
1993}
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