updated code to follow same blinking patterns with leds during flashing/holding button
[proxmark3-svn] / bootrom / bootrom.c
CommitLineData
bd20f8f4 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Main code for the bootloader
7//-----------------------------------------------------------------------------
8
15c4dc5a 9#include <proxmark3.h>
28fdb04f 10#include "usb_cdc.h"
11#include "cmd.h"
12//#include "usb_hid.h"
13
14void DbpString(char *str) {
15 byte_t len = 0;
16 while (str[len] != 0x00) {
17 len++;
18 }
19 cmd_send(CMD_DEBUG_PRINT_STRING,len,0,0,(byte_t*)str,len);
20}
15c4dc5a 21
22struct common_area common_area __attribute__((section(".commonarea")));
23unsigned int start_addr, end_addr, bootrom_unlocked;
24extern char _bootrom_start, _bootrom_end, _flash_start, _flash_end;
25
26static void ConfigClocks(void)
27{
28 // we are using a 16 MHz crystal as the basis for everything
29 // slow clock runs at 32Khz typical regardless of crystal
30
31 // enable system clock and USB clock
32 AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK | AT91C_PMC_UDP;
33
34 // enable the clock to the following peripherals
35 AT91C_BASE_PMC->PMC_PCER =
36 (1<<AT91C_ID_PIOA) |
37 (1<<AT91C_ID_ADC) |
38 (1<<AT91C_ID_SPI) |
39 (1<<AT91C_ID_SSC) |
40 (1<<AT91C_ID_PWMC) |
41 (1<<AT91C_ID_UDP);
42
0aa4cfc2 43 // worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
44 // if SLCK slow clock runs at its worst case (max) frequency of 42khz
45 // max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
15c4dc5a 46
47 // enable main oscillator and set startup delay
48 AT91C_BASE_PMC->PMC_MOR =
0aa4cfc2 49 AT91C_CKGR_MOSCEN |
50 PMC_MAIN_OSC_STARTUP_DELAY(8);
15c4dc5a 51
52 // wait for main oscillator to stabilize
0aa4cfc2 53 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) )
15c4dc5a 54 ;
55
0aa4cfc2 56 // PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
57 // PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
58 // PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
15c4dc5a 59 AT91C_BASE_PMC->PMC_PLLR =
60 PMC_PLL_DIVISOR(2) |
61 PMC_PLL_COUNT_BEFORE_LOCK(0x50) |
62 PMC_PLL_FREQUENCY_RANGE(0) |
63 PMC_PLL_MULTIPLIER(12) |
64 PMC_PLL_USB_DIVISOR(1);
65
66 // wait for PLL to lock
0aa4cfc2 67 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) )
15c4dc5a 68 ;
69
70 // we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
0aa4cfc2 71 // datasheet recommends that this register is programmed in two operations
15c4dc5a 72 // when changing to PLL, program the prescaler first then the source
0aa4cfc2 73 AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
15c4dc5a 74
75 // wait for main clock ready signal
0aa4cfc2 76 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
15c4dc5a 77 ;
78
79 // set the source to PLL
0aa4cfc2 80 AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
15c4dc5a 81
82 // wait for main clock ready signal
0aa4cfc2 83 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
15c4dc5a 84 ;
85}
86
87static void Fatal(void)
88{
28fdb04f 89 for(;;);
15c4dc5a 90}
91
28fdb04f 92void UsbPacketReceived(uint8_t *packet, int len) {
93 int i, dont_ack=0;
94 UsbCommand* c = (UsbCommand *)packet;
95 volatile uint32_t *p;
96
97 if(len != sizeof(UsbCommand)) {
98 Fatal();
99 }
100
101 uint32_t arg0 = (uint32_t)c->arg[0];
102
103 switch(c->cmd) {
104 case CMD_DEVICE_INFO: {
105 dont_ack = 1;
106// c->cmd = CMD_DEVICE_INFO;
107 arg0 = DEVICE_INFO_FLAG_BOOTROM_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM |
108 DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;
109 if(common_area.flags.osimage_present) {
110 arg0 |= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;
111 }
112// UsbSendPacket(packet, len);
113 cmd_send(CMD_DEVICE_INFO,arg0,1,2,0,0);
114 } break;
115
116 case CMD_SETUP_WRITE: {
117 /* The temporary write buffer of the embedded flash controller is mapped to the
118 * whole memory region, only the last 8 bits are decoded.
119 */
120 p = (volatile uint32_t *)&_flash_start;
121 for(i = 0; i < 12; i++) {
122 p[i+arg0] = c->d.asDwords[i];
123 }
124 } break;
125
126 case CMD_FINISH_WRITE: {
127 uint32_t* flash_mem = (uint32_t*)(&_flash_start);
128// p = (volatile uint32_t *)&_flash_start;
129 for (size_t j=0; j<2; j++) {
130 for(i = 0+(64*j); i < 64+(64*j); i++) {
131 //p[i+60] = c->d.asDwords[i];
132 flash_mem[i] = c->d.asDwords[i];
133 }
134
135 uint32_t flash_address = arg0 + (0x100*j);
136
137 /* Check that the address that we are supposed to write to is within our allowed region */
138 if( ((flash_address+AT91C_IFLASH_PAGE_SIZE-1) >= end_addr) || (flash_address < start_addr) ) {
139 /* Disallow write */
140 dont_ack = 1;
141 // c->cmd = CMD_NACK;
142 // UsbSendPacket(packet, len);
143 cmd_send(CMD_NACK,0,0,0,0,0);
144 } else {
145 uint32_t page_n = (flash_address - ((uint32_t)flash_mem)) / AT91C_IFLASH_PAGE_SIZE;
146 /* Translate address to flash page and do flash, update here for the 512k part */
147 AT91C_BASE_EFC0->EFC_FCR = MC_FLASH_COMMAND_KEY |
148 MC_FLASH_COMMAND_PAGEN(page_n) |
149 AT91C_MC_FCMD_START_PROG;
150 // arg0 = (address - ((uint32_t)flash_s));
151 }
152
153 // Wait until flashing of page finishes
154 uint32_t sr;
155 while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & AT91C_MC_FRDY));
156 if(sr & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) {
157 dont_ack = 1;
158 // c->cmd = CMD_NACK;
159 cmd_send(CMD_NACK,0,0,0,0,0);
160 // UsbSendPacket(packet, len);
161 }
162 }
163 } break;
164
165 case CMD_HARDWARE_RESET: {
166// USB_D_PLUS_PULLUP_OFF();
167 usb_disable();
168 AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
169 } break;
170
171 case CMD_START_FLASH: {
172 if(c->arg[2] == START_FLASH_MAGIC) bootrom_unlocked = 1;
173 else bootrom_unlocked = 0;
174 {
175 int prot_start = (int)&_bootrom_start;
176 int prot_end = (int)&_bootrom_end;
177 int allow_start = (int)&_flash_start;
178 int allow_end = (int)&_flash_end;
179 int cmd_start = c->arg[0];
180 int cmd_end = c->arg[1];
181
182 /* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected
183 * bootrom area. In any case they must be within the flash area.
184 */
185 if( (bootrom_unlocked || ((cmd_start >= prot_end) || (cmd_end < prot_start)))
186 && (cmd_start >= allow_start) && (cmd_end <= allow_end) ) {
187 start_addr = cmd_start;
188 end_addr = cmd_end;
189 } else {
190 start_addr = end_addr = 0;
191 dont_ack = 1;
192// c->cmd = CMD_NACK;
193// UsbSendPacket(packet, len);
194 cmd_send(CMD_NACK,0,0,0,0,0);
195 }
196 }
197 } break;
198
199 default: {
200 Fatal();
201 } break;
202 }
203
204 if(!dont_ack) {
205// c->cmd = CMD_ACK;
206// UsbSendPacket(packet, len);
207 cmd_send(CMD_ACK,arg0,0,0,0,0);
208 }
15c4dc5a 209}
210
211static void flash_mode(int externally_entered)
212{
213 start_addr = 0;
214 end_addr = 0;
215 bootrom_unlocked = 0;
28fdb04f 216 byte_t rx[sizeof(UsbCommand)];
217 size_t rx_len;
218
219 usb_enable();
220 for (volatile size_t i=0; i<0x100000; i++);
15c4dc5a 221
28fdb04f 222// UsbStart();
15c4dc5a 223 for(;;) {
224 WDT_HIT();
225
28fdb04f 226 if (usb_poll()) {
227 rx_len = usb_read(rx,sizeof(UsbCommand));
228 if (rx_len) {
229// DbpString("starting to flash");
230 UsbPacketReceived(rx,rx_len);
231 }
232 }
233
234// UsbPoll(TRUE);
15c4dc5a 235
236 if(!externally_entered && !BUTTON_PRESS()) {
237 /* Perform a reset to leave flash mode */
28fdb04f 238// USB_D_PLUS_PULLUP_OFF();
239 usb_disable();
15c4dc5a 240 LED_B_ON();
241 AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
242 for(;;);
243 }
244 if(externally_entered && BUTTON_PRESS()) {
245 /* Let the user's button press override the automatic leave */
246 externally_entered = 0;
247 }
248 }
249}
250
28fdb04f 251extern uint32_t _osimage_entry;
15c4dc5a 252void BootROM(void)
253{
254 //------------
255 // First set up all the I/O pins; GPIOs configured directly, other ones
256 // just need to be assigned to the appropriate peripheral.
257
258 // Kill all the pullups, especially the one on USB D+; leave them for
259 // the unused pins, though.
260 AT91C_BASE_PIOA->PIO_PPUDR =
261 GPIO_USB_PU |
262 GPIO_LED_A |
263 GPIO_LED_B |
264 GPIO_LED_C |
265 GPIO_LED_D |
266 GPIO_FPGA_DIN |
267 GPIO_FPGA_DOUT |
268 GPIO_FPGA_CCLK |
269 GPIO_FPGA_NINIT |
270 GPIO_FPGA_NPROGRAM |
271 GPIO_FPGA_DONE |
272 GPIO_MUXSEL_HIPKD |
273 GPIO_MUXSEL_HIRAW |
274 GPIO_MUXSEL_LOPKD |
275 GPIO_MUXSEL_LORAW |
276 GPIO_RELAY |
277 GPIO_NVDD_ON;
278 // (and add GPIO_FPGA_ON)
279 // These pins are outputs
280 AT91C_BASE_PIOA->PIO_OER =
281 GPIO_LED_A |
282 GPIO_LED_B |
283 GPIO_LED_C |
284 GPIO_LED_D |
285 GPIO_RELAY |
286 GPIO_NVDD_ON;
287 // PIO controls the following pins
288 AT91C_BASE_PIOA->PIO_PER =
289 GPIO_USB_PU |
290 GPIO_LED_A |
291 GPIO_LED_B |
292 GPIO_LED_C |
293 GPIO_LED_D;
294
28fdb04f 295// USB_D_PLUS_PULLUP_OFF();
296 usb_disable();
15c4dc5a 297 LED_D_OFF();
298 LED_C_ON();
299 LED_B_OFF();
300 LED_A_OFF();
301
24b182d0 302 AT91C_BASE_EFC0->EFC_FMR =
0aa4cfc2 303 AT91C_MC_FWS_1FWS |
24b182d0 304 MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
15c4dc5a 305
306 // Initialize all system clocks
307 ConfigClocks();
308
309 LED_A_ON();
310
311 int common_area_present = 0;
312 switch(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_RSTTYP) {
313 case AT91C_RSTC_RSTTYP_WATCHDOG:
314 case AT91C_RSTC_RSTTYP_SOFTWARE:
315 case AT91C_RSTC_RSTTYP_USER:
316 /* In these cases the common_area in RAM should be ok, retain it if it's there */
317 if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1) {
318 common_area_present = 1;
319 }
320 break;
321 default: /* Otherwise, initialize it from scratch */
322 break;
323 }
324
325 if(!common_area_present){
326 /* Common area not ok, initialize it */
327 int i; for(i=0; i<sizeof(common_area); i++) { /* Makeshift memset, no need to drag util.c into this */
328 ((char*)&common_area)[i] = 0;
329 }
330 common_area.magic = COMMON_AREA_MAGIC;
331 common_area.version = 1;
332 common_area.flags.bootrom_present = 1;
333 }
334
335 common_area.flags.bootrom_present = 1;
336 if(common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {
337 common_area.command = COMMON_AREA_COMMAND_NONE;
338 flash_mode(1);
339 } else if(BUTTON_PRESS()) {
340 flash_mode(0);
28fdb04f 341 } else if(_osimage_entry == 0xffffffffU) {
15c4dc5a 342 flash_mode(1);
343 } else {
344 // jump to Flash address of the osimage entry point (LSBit set for thumb mode)
902cb3c0 345 __asm("bx %0\n" : : "r" ( ((int)&_osimage_entry) | 0x1 ) );
15c4dc5a 346 }
347}
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