refactor lfops t55xx functions
[proxmark3-svn] / armsrc / lfops.c
CommitLineData
e09f21fa 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
9//-----------------------------------------------------------------------------
10
11#include "proxmark3.h"
12#include "apps.h"
13#include "util.h"
14#include "hitag2.h"
15#include "crc16.h"
16#include "string.h"
17#include "lfdemod.h"
18#include "lfsampling.h"
3606ac0a 19#include "protocols.h"
dc4300ba 20#include "usb_cdc.h" //test
e09f21fa 21
22/**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
21a615cb 29void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)
e09f21fa 30{
31
e0165dcf 32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
e09f21fa 34
e0165dcf 35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
e09f21fa 37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
e0165dcf 51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
e09f21fa 56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
e0165dcf 58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
e09f21fa 68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
e0165dcf 70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
e09f21fa 71
e0165dcf 72 // now do the read
e09f21fa 73 DoAcquisition_config(false);
74}
75
76
77
78/* blank r/w tag data stream
79...0000000000000000 01111111
801010101010101010101010101010101010101010101010101010101010101010
810011010010100001
8201111111
83101010101010101[0]000...
84
85[5555fe852c5555555555555555fe0000]
86*/
87void ReadTItag(void)
88{
e0165dcf 89 // some hardcoded initial params
90 // when we read a TI tag we sample the zerocross line at 2Mhz
91 // TI tags modulate a 1 as 16 cycles of 123.2Khz
92 // TI tags modulate a 0 as 16 cycles of 134.2Khz
e09f21fa 93 #define FSAMPLE 2000000
94 #define FREQLO 123200
95 #define FREQHI 134200
96
e0165dcf 97 signed char *dest = (signed char *)BigBuf_get_addr();
98 uint16_t n = BigBuf_max_traceLen();
99 // 128 bit shift register [shift3:shift2:shift1:shift0]
100 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
101
102 int i, cycles=0, samples=0;
103 // how many sample points fit in 16 cycles of each frequency
104 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
105 // when to tell if we're close enough to one freq or another
106 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
107
108 // TI tags charge at 134.2Khz
109 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
111
112 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
113 // connects to SSP_DIN and the SSP_DOUT logic level controls
114 // whether we're modulating the antenna (high)
115 // or listening to the antenna (low)
116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
117
118 // get TI tag data into the buffer
119 AcquireTiType();
120
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
122
123 for (i=0; i<n-1; i++) {
124 // count cycles by looking for lo to hi zero crossings
125 if ( (dest[i]<0) && (dest[i+1]>0) ) {
126 cycles++;
127 // after 16 cycles, measure the frequency
128 if (cycles>15) {
129 cycles=0;
130 samples=i-samples; // number of samples in these 16 cycles
131
132 // TI bits are coming to us lsb first so shift them
133 // right through our 128 bit right shift register
134 shift0 = (shift0>>1) | (shift1 << 31);
135 shift1 = (shift1>>1) | (shift2 << 31);
136 shift2 = (shift2>>1) | (shift3 << 31);
137 shift3 >>= 1;
138
139 // check if the cycles fall close to the number
140 // expected for either the low or high frequency
141 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
142 // low frequency represents a 1
143 shift3 |= (1<<31);
144 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
145 // high frequency represents a 0
146 } else {
147 // probably detected a gay waveform or noise
148 // use this as gaydar or discard shift register and start again
149 shift3 = shift2 = shift1 = shift0 = 0;
150 }
151 samples = i;
152
153 // for each bit we receive, test if we've detected a valid tag
154
155 // if we see 17 zeroes followed by 6 ones, we might have a tag
156 // remember the bits are backwards
157 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
158 // if start and end bytes match, we have a tag so break out of the loop
159 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
160 cycles = 0xF0B; //use this as a flag (ugly but whatever)
161 break;
162 }
163 }
164 }
165 }
166 }
167
168 // if flag is set we have a tag
169 if (cycles!=0xF0B) {
170 DbpString("Info: No valid tag detected.");
171 } else {
172 // put 64 bit data into shift1 and shift0
173 shift0 = (shift0>>24) | (shift1 << 8);
174 shift1 = (shift1>>24) | (shift2 << 8);
175
176 // align 16 bit crc into lower half of shift2
177 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
178
179 // if r/w tag, check ident match
e09f21fa 180 if (shift3 & (1<<15) ) {
e0165dcf 181 DbpString("Info: TI tag is rewriteable");
182 // only 15 bits compare, last bit of ident is not valid
e09f21fa 183 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
e0165dcf 184 DbpString("Error: Ident mismatch!");
185 } else {
186 DbpString("Info: TI tag ident is valid");
187 }
188 } else {
189 DbpString("Info: TI tag is readonly");
190 }
191
192 // WARNING the order of the bytes in which we calc crc below needs checking
193 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
194 // bytes in reverse or something
195 // calculate CRC
196 uint32_t crc=0;
197
198 crc = update_crc16(crc, (shift0)&0xff);
199 crc = update_crc16(crc, (shift0>>8)&0xff);
200 crc = update_crc16(crc, (shift0>>16)&0xff);
201 crc = update_crc16(crc, (shift0>>24)&0xff);
202 crc = update_crc16(crc, (shift1)&0xff);
203 crc = update_crc16(crc, (shift1>>8)&0xff);
204 crc = update_crc16(crc, (shift1>>16)&0xff);
205 crc = update_crc16(crc, (shift1>>24)&0xff);
206
207 Dbprintf("Info: Tag data: %x%08x, crc=%x",
208 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
209 if (crc != (shift2&0xffff)) {
210 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
211 } else {
212 DbpString("Info: CRC is good");
213 }
214 }
e09f21fa 215}
216
dc4300ba
D
217
218
e09f21fa 219void WriteTIbyte(uint8_t b)
220{
e0165dcf 221 int i = 0;
222
223 // modulate 8 bits out to the antenna
224 for (i=0; i<8; i++)
225 {
226 if (b&(1<<i)) {
227 // stop modulating antenna
228 LOW(GPIO_SSC_DOUT);
229 SpinDelayUs(1000);
230 // modulate antenna
231 HIGH(GPIO_SSC_DOUT);
232 SpinDelayUs(1000);
233 } else {
234 // stop modulating antenna
235 LOW(GPIO_SSC_DOUT);
236 SpinDelayUs(300);
237 // modulate antenna
238 HIGH(GPIO_SSC_DOUT);
239 SpinDelayUs(1700);
240 }
241 }
e09f21fa 242}
243
244void AcquireTiType(void)
245{
e0165dcf 246 int i, j, n;
247 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
248 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
e09f21fa 249 #define TIBUFLEN 1250
250
e0165dcf 251 // clear buffer
e09f21fa 252 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
e0165dcf 253 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
254
255 // Set up the synchronous serial port
256 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
257 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
258
259 // steal this pin from the SSP and use it to control the modulation
260 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
261 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
262
263 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
264 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
265
266 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
267 // 48/2 = 24 MHz clock must be divided by 12
268 AT91C_BASE_SSC->SSC_CMR = 12;
269
270 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
271 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
272 AT91C_BASE_SSC->SSC_TCMR = 0;
273 AT91C_BASE_SSC->SSC_TFMR = 0;
274
275 LED_D_ON();
276
277 // modulate antenna
278 HIGH(GPIO_SSC_DOUT);
279
280 // Charge TI tag for 50ms.
281 SpinDelay(50);
282
283 // stop modulating antenna and listen
284 LOW(GPIO_SSC_DOUT);
285
286 LED_D_OFF();
287
288 i = 0;
289 for(;;) {
290 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
291 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
292 i++; if(i >= TIBUFLEN) break;
293 }
294 WDT_HIT();
295 }
296
297 // return stolen pin to SSP
298 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
299 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
300
301 char *dest = (char *)BigBuf_get_addr();
302 n = TIBUFLEN*32;
303 // unpack buffer
304 for (i=TIBUFLEN-1; i>=0; i--) {
305 for (j=0; j<32; j++) {
306 if(BigBuf[i] & (1 << j)) {
307 dest[--n] = 1;
308 } else {
309 dest[--n] = -1;
310 }
311 }
312 }
e09f21fa 313}
314
dc4300ba
D
315
316
317
e09f21fa 318// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
319// if crc provided, it will be written with the data verbatim (even if bogus)
320// if not provided a valid crc will be computed from the data and written.
321void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
322{
dc4300ba
D
323
324
fff58476 325 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
e0165dcf 326 if(crc == 0) {
327 crc = update_crc16(crc, (idlo)&0xff);
328 crc = update_crc16(crc, (idlo>>8)&0xff);
329 crc = update_crc16(crc, (idlo>>16)&0xff);
330 crc = update_crc16(crc, (idlo>>24)&0xff);
331 crc = update_crc16(crc, (idhi)&0xff);
332 crc = update_crc16(crc, (idhi>>8)&0xff);
333 crc = update_crc16(crc, (idhi>>16)&0xff);
334 crc = update_crc16(crc, (idhi>>24)&0xff);
335 }
336 Dbprintf("Writing to tag: %x%08x, crc=%x",
337 (unsigned int) idhi, (unsigned int) idlo, crc);
338
339 // TI tags charge at 134.2Khz
340 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
341 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
342 // connects to SSP_DIN and the SSP_DOUT logic level controls
343 // whether we're modulating the antenna (high)
344 // or listening to the antenna (low)
345 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
346 LED_A_ON();
347
348 // steal this pin from the SSP and use it to control the modulation
349 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
350 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
351
352 // writing algorithm:
353 // a high bit consists of a field off for 1ms and field on for 1ms
354 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
355 // initiate a charge time of 50ms (field on) then immediately start writing bits
356 // start by writing 0xBB (keyword) and 0xEB (password)
357 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
358 // finally end with 0x0300 (write frame)
359 // all data is sent lsb firts
360 // finish with 15ms programming time
361
362 // modulate antenna
363 HIGH(GPIO_SSC_DOUT);
364 SpinDelay(50); // charge time
365
366 WriteTIbyte(0xbb); // keyword
367 WriteTIbyte(0xeb); // password
368 WriteTIbyte( (idlo )&0xff );
369 WriteTIbyte( (idlo>>8 )&0xff );
370 WriteTIbyte( (idlo>>16)&0xff );
371 WriteTIbyte( (idlo>>24)&0xff );
372 WriteTIbyte( (idhi )&0xff );
373 WriteTIbyte( (idhi>>8 )&0xff );
374 WriteTIbyte( (idhi>>16)&0xff );
375 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
376 WriteTIbyte( (crc )&0xff ); // crc lo
377 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
378 WriteTIbyte(0x00); // write frame lo
379 WriteTIbyte(0x03); // write frame hi
380 HIGH(GPIO_SSC_DOUT);
381 SpinDelay(50); // programming time
382
383 LED_A_OFF();
384
385 // get TI tag data into the buffer
386 AcquireTiType();
387
388 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
389 DbpString("Now use tiread to check");
e09f21fa 390}
391
392void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
393{
e0165dcf 394 int i;
395 uint8_t *tab = BigBuf_get_addr();
e09f21fa 396
e0165dcf 397 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
398 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
e09f21fa 399
e0165dcf 400 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
e09f21fa 401
e0165dcf 402 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
403 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
e09f21fa 404
405 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
406 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
407
e0165dcf 408 i = 0;
409 for(;;) {
410 //wait until SSC_CLK goes HIGH
411 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
83f3f8ac 412 if(BUTTON_PRESS() || (usb_poll_validate_length() )) {
e0165dcf 413 DbpString("Stopped");
414 return;
415 }
416 WDT_HIT();
417 }
418 if (ledcontrol)
419 LED_D_ON();
420
421 if(tab[i])
422 OPEN_COIL();
423 else
424 SHORT_COIL();
425
426 if (ledcontrol)
427 LED_D_OFF();
428 //wait until SSC_CLK goes LOW
429 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
430 if(BUTTON_PRESS()) {
431 DbpString("Stopped");
432 return;
433 }
434 WDT_HIT();
435 }
436
437 i++;
438 if(i == period) {
439
440 i = 0;
441 if (gap) {
442 SHORT_COIL();
443 SpinDelayUs(gap);
444 }
445 }
446 }
e09f21fa 447}
448
e09f21fa 449#define DEBUG_FRAME_CONTENTS 1
450void SimulateTagLowFrequencyBidir(int divisor, int t0)
451{
452}
453
454// compose fc/8 fc/10 waveform (FSK2)
455static void fc(int c, int *n)
456{
e0165dcf 457 uint8_t *dest = BigBuf_get_addr();
458 int idx;
459
460 // for when we want an fc8 pattern every 4 logical bits
461 if(c==0) {
462 dest[((*n)++)]=1;
463 dest[((*n)++)]=1;
464 dest[((*n)++)]=1;
465 dest[((*n)++)]=1;
466 dest[((*n)++)]=0;
467 dest[((*n)++)]=0;
468 dest[((*n)++)]=0;
469 dest[((*n)++)]=0;
470 }
471
472 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
473 if(c==8) {
474 for (idx=0; idx<6; idx++) {
475 dest[((*n)++)]=1;
476 dest[((*n)++)]=1;
477 dest[((*n)++)]=1;
478 dest[((*n)++)]=1;
479 dest[((*n)++)]=0;
480 dest[((*n)++)]=0;
481 dest[((*n)++)]=0;
482 dest[((*n)++)]=0;
483 }
484 }
485
486 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
487 if(c==10) {
488 for (idx=0; idx<5; idx++) {
489 dest[((*n)++)]=1;
490 dest[((*n)++)]=1;
491 dest[((*n)++)]=1;
492 dest[((*n)++)]=1;
493 dest[((*n)++)]=1;
494 dest[((*n)++)]=0;
495 dest[((*n)++)]=0;
496 dest[((*n)++)]=0;
497 dest[((*n)++)]=0;
498 dest[((*n)++)]=0;
499 }
500 }
e09f21fa 501}
502// compose fc/X fc/Y waveform (FSKx)
712ebfa6 503static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 504{
e0165dcf 505 uint8_t *dest = BigBuf_get_addr();
506 uint8_t halfFC = fc/2;
507 uint8_t wavesPerClock = clock/fc;
508 uint8_t mod = clock % fc; //modifier
509 uint8_t modAdj = fc/mod; //how often to apply modifier
510 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
511 // loop through clock - step field clock
512 for (uint8_t idx=0; idx < wavesPerClock; idx++){
513 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
514 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
515 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
516 *n += fc;
517 }
518 if (mod>0) (*modCnt)++;
519 if ((mod>0) && modAdjOk){ //fsk2
520 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
521 memset(dest+(*n), 0, fc-halfFC);
522 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
523 *n += fc;
524 }
525 }
526 if (mod>0 && !modAdjOk){ //fsk1
527 memset(dest+(*n), 0, mod-(mod/2));
528 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
529 *n += mod;
530 }
e09f21fa 531}
532
533// prepare a waveform pattern in the buffer based on the ID given then
534// simulate a HID tag until the button is pressed
535void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
536{
e0165dcf 537 int n=0, i=0;
538 /*
539 HID tag bitstream format
540 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
541 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
542 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
543 A fc8 is inserted before every 4 bits
544 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
545 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
546 */
547
548 if (hi>0xFFF) {
549 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
550 return;
551 }
552 fc(0,&n);
553 // special start of frame marker containing invalid bit sequences
554 fc(8, &n); fc(8, &n); // invalid
555 fc(8, &n); fc(10, &n); // logical 0
556 fc(10, &n); fc(10, &n); // invalid
557 fc(8, &n); fc(10, &n); // logical 0
558
559 WDT_HIT();
560 // manchester encode bits 43 to 32
561 for (i=11; i>=0; i--) {
562 if ((i%4)==3) fc(0,&n);
563 if ((hi>>i)&1) {
564 fc(10, &n); fc(8, &n); // low-high transition
565 } else {
566 fc(8, &n); fc(10, &n); // high-low transition
567 }
568 }
569
570 WDT_HIT();
571 // manchester encode bits 31 to 0
572 for (i=31; i>=0; i--) {
573 if ((i%4)==3) fc(0,&n);
574 if ((lo>>i)&1) {
575 fc(10, &n); fc(8, &n); // low-high transition
576 } else {
577 fc(8, &n); fc(10, &n); // high-low transition
578 }
579 }
580
581 if (ledcontrol)
582 LED_A_ON();
583 SimulateTagLowFrequency(n, 0, ledcontrol);
584
585 if (ledcontrol)
586 LED_A_OFF();
e09f21fa 587}
588
589// prepare a waveform pattern in the buffer based on the ID given then
590// simulate a FSK tag until the button is pressed
591// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
592void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
593{
e0165dcf 594 int ledcontrol=1;
595 int n=0, i=0;
596 uint8_t fcHigh = arg1 >> 8;
597 uint8_t fcLow = arg1 & 0xFF;
598 uint16_t modCnt = 0;
599 uint8_t clk = arg2 & 0xFF;
600 uint8_t invert = (arg2 >> 8) & 1;
601
602 for (i=0; i<size; i++){
603 if (BitStream[i] == invert){
604 fcAll(fcLow, &n, clk, &modCnt);
605 } else {
606 fcAll(fcHigh, &n, clk, &modCnt);
607 }
608 }
609 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
610 /*Dbprintf("DEBUG: First 32:");
611 uint8_t *dest = BigBuf_get_addr();
612 i=0;
613 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
614 i+=16;
615 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
616 */
617 if (ledcontrol)
618 LED_A_ON();
619
620 SimulateTagLowFrequency(n, 0, ledcontrol);
621
622 if (ledcontrol)
623 LED_A_OFF();
e09f21fa 624}
625
626// compose ask waveform for one bit(ASK)
e0165dcf 627static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
e09f21fa 628{
e0165dcf 629 uint8_t *dest = BigBuf_get_addr();
630 uint8_t halfClk = clock/2;
631 // c = current bit 1 or 0
632 if (manchester==1){
633 memset(dest+(*n), c, halfClk);
634 memset(dest+(*n) + halfClk, c^1, halfClk);
635 } else {
636 memset(dest+(*n), c, clock);
637 }
638 *n += clock;
e09f21fa 639}
640
b41534d1 641static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
642{
e0165dcf 643 uint8_t *dest = BigBuf_get_addr();
644 uint8_t halfClk = clock/2;
645 if (c){
646 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
647 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
648 } else {
649 memset(dest+(*n), c ^ *phase, clock);
650 *phase ^= 1;
651 }
b41534d1 652}
653
e09f21fa 654// args clock, ask/man or askraw, invert, transmission separator
655void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
656{
e0165dcf 657 int ledcontrol = 1;
658 int n=0, i=0;
659 uint8_t clk = (arg1 >> 8) & 0xFF;
2b3af97d 660 uint8_t encoding = arg1 & 0xFF;
e0165dcf 661 uint8_t separator = arg2 & 1;
662 uint8_t invert = (arg2 >> 8) & 1;
663
664 if (encoding==2){ //biphase
665 uint8_t phase=0;
666 for (i=0; i<size; i++){
667 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
668 }
669 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
670 for (i=0; i<size; i++){
671 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
672 }
673 }
674 } else { // ask/manchester || ask/raw
675 for (i=0; i<size; i++){
676 askSimBit(BitStream[i]^invert, &n, clk, encoding);
677 }
678 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
679 for (i=0; i<size; i++){
680 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
681 }
682 }
683 }
684
685 if (separator==1) Dbprintf("sorry but separator option not yet available");
686
687 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
688 //DEBUG
689 //Dbprintf("First 32:");
690 //uint8_t *dest = BigBuf_get_addr();
691 //i=0;
692 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
693 //i+=16;
694 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
695
696 if (ledcontrol)
697 LED_A_ON();
698
699 SimulateTagLowFrequency(n, 0, ledcontrol);
700
701 if (ledcontrol)
702 LED_A_OFF();
e09f21fa 703}
704
705//carrier can be 2,4 or 8
706static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
707{
e0165dcf 708 uint8_t *dest = BigBuf_get_addr();
709 uint8_t halfWave = waveLen/2;
710 //uint8_t idx;
711 int i = 0;
712 if (phaseChg){
713 // write phase change
714 memset(dest+(*n), *curPhase^1, halfWave);
715 memset(dest+(*n) + halfWave, *curPhase, halfWave);
716 *n += waveLen;
717 *curPhase ^= 1;
718 i += waveLen;
719 }
720 //write each normal clock wave for the clock duration
721 for (; i < clk; i+=waveLen){
722 memset(dest+(*n), *curPhase, halfWave);
723 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
724 *n += waveLen;
725 }
e09f21fa 726}
727
728// args clock, carrier, invert,
729void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
730{
e0165dcf 731 int ledcontrol=1;
732 int n=0, i=0;
733 uint8_t clk = arg1 >> 8;
734 uint8_t carrier = arg1 & 0xFF;
735 uint8_t invert = arg2 & 0xFF;
736 uint8_t curPhase = 0;
737 for (i=0; i<size; i++){
738 if (BitStream[i] == curPhase){
739 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
740 } else {
741 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
742 }
743 }
744 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
745 //Dbprintf("DEBUG: First 32:");
746 //uint8_t *dest = BigBuf_get_addr();
747 //i=0;
748 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
749 //i+=16;
750 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
751
752 if (ledcontrol)
753 LED_A_ON();
754 SimulateTagLowFrequency(n, 0, ledcontrol);
755
756 if (ledcontrol)
757 LED_A_OFF();
e09f21fa 758}
759
760// loop to get raw HID waveform then FSK demodulate the TAG ID from it
761void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
762{
e0165dcf 763 uint8_t *dest = BigBuf_get_addr();
2eec55c8 764 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
765 size_t size;
e0165dcf 766 uint32_t hi2=0, hi=0, lo=0;
767 int idx=0;
768 // Configure to go in 125Khz listen mode
769 LFSetupFPGAForADC(95, true);
e09f21fa 770
d10e08ae 771 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
e09f21fa 772
e0165dcf 773 WDT_HIT();
774 if (ledcontrol) LED_A_ON();
e09f21fa 775
776 DoAcquisition_default(-1,true);
777 // FSK demodulator
2eec55c8 778 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
779 size = 50*128*2; //big enough to catch 2 sequences of largest format
e09f21fa 780 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
e0165dcf 781
2eec55c8 782 if (idx>0 && lo>0 && (size==96 || size==192)){
783 // go over previously decoded manchester data and decode into usable tag ID
784 if (hi2 != 0){ //extra large HID tags 88/192 bits
e0165dcf 785 Dbprintf("TAG ID: %x%08x%08x (%d)",
786 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
2eec55c8 787 }else { //standard HID tags 44/96 bits
e0165dcf 788 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
789 uint8_t bitlen = 0;
790 uint32_t fc = 0;
791 uint32_t cardnum = 0;
e09f21fa 792 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
e0165dcf 793 uint32_t lo2=0;
794 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
795 uint8_t idx3 = 1;
e09f21fa 796 while(lo2 > 1){ //find last bit set to 1 (format len bit)
797 lo2=lo2 >> 1;
e0165dcf 798 idx3++;
799 }
e09f21fa 800 bitlen = idx3+19;
e0165dcf 801 fc =0;
802 cardnum=0;
e09f21fa 803 if(bitlen == 26){
e0165dcf 804 cardnum = (lo>>1)&0xFFFF;
805 fc = (lo>>17)&0xFF;
806 }
e09f21fa 807 if(bitlen == 37){
e0165dcf 808 cardnum = (lo>>1)&0x7FFFF;
809 fc = ((hi&0xF)<<12)|(lo>>20);
810 }
e09f21fa 811 if(bitlen == 34){
e0165dcf 812 cardnum = (lo>>1)&0xFFFF;
813 fc= ((hi&1)<<15)|(lo>>17);
814 }
e09f21fa 815 if(bitlen == 35){
e0165dcf 816 cardnum = (lo>>1)&0xFFFFF;
817 fc = ((hi&1)<<11)|(lo>>21);
818 }
819 }
820 else { //if bit 38 is not set then 37 bit format is used
821 bitlen= 37;
822 fc =0;
823 cardnum=0;
824 if(bitlen==37){
825 cardnum = (lo>>1)&0x7FFFF;
826 fc = ((hi&0xF)<<12)|(lo>>20);
827 }
828 }
829 //Dbprintf("TAG ID: %x%08x (%d)",
830 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
831 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
832 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
833 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
834 }
835 if (findone){
836 if (ledcontrol) LED_A_OFF();
837 *high = hi;
838 *low = lo;
839 return;
840 }
841 // reset
e0165dcf 842 }
2eec55c8 843 hi2 = hi = lo = idx = 0;
e0165dcf 844 WDT_HIT();
845 }
846 DbpString("Stopped");
847 if (ledcontrol) LED_A_OFF();
e09f21fa 848}
849
dbf6e824
CY
850// loop to get raw HID waveform then FSK demodulate the TAG ID from it
851void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
852{
853 uint8_t *dest = BigBuf_get_addr();
854 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
855 size_t size;
856 int idx=0;
857 // Configure to go in 125Khz listen mode
858 LFSetupFPGAForADC(95, true);
859
d10e08ae 860 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
dbf6e824
CY
861
862 WDT_HIT();
863 if (ledcontrol) LED_A_ON();
864
865 DoAcquisition_default(-1,true);
866 // FSK demodulator
867 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
868 size = 50*128*2; //big enough to catch 2 sequences of largest format
869 idx = AWIDdemodFSK(dest, &size);
870
871 if (idx>0 && size==96){
872 // Index map
873 // 0 10 20 30 40 50 60
874 // | | | | | | |
875 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
876 // -----------------------------------------------------------------------------
877 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
878 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
879 // |---26 bit---| |-----117----||-------------142-------------|
880 // b = format bit len, o = odd parity of last 3 bits
881 // f = facility code, c = card number
882 // w = wiegand parity
883 // (26 bit format shown)
884
885 //get raw ID before removing parities
886 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
887 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
888 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
889
890 size = removeParity(dest, idx+8, 4, 1, 88);
891 // ok valid card found!
892
893 // Index map
894 // 0 10 20 30 40 50 60
895 // | | | | | | |
896 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
897 // -----------------------------------------------------------------------------
898 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
899 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
900 // |26 bit| |-117--| |-----142------|
901 // b = format bit len, o = odd parity of last 3 bits
902 // f = facility code, c = card number
903 // w = wiegand parity
904 // (26 bit format shown)
905
906 uint32_t fc = 0;
907 uint32_t cardnum = 0;
908 uint32_t code1 = 0;
909 uint32_t code2 = 0;
910 uint8_t fmtLen = bytebits_to_byte(dest,8);
911 if (fmtLen==26){
912 fc = bytebits_to_byte(dest+9, 8);
913 cardnum = bytebits_to_byte(dest+17, 16);
914 code1 = bytebits_to_byte(dest+8,fmtLen);
915 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
916 } else {
917 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
918 if (fmtLen>32){
919 code1 = bytebits_to_byte(dest+8,fmtLen-32);
920 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
921 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
922 } else{
923 code1 = bytebits_to_byte(dest+8,fmtLen);
924 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
925 }
926 }
927 if (findone){
928 if (ledcontrol) LED_A_OFF();
929 return;
930 }
931 // reset
932 }
933 idx = 0;
934 WDT_HIT();
935 }
936 DbpString("Stopped");
937 if (ledcontrol) LED_A_OFF();
938}
939
e09f21fa 940void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
941{
e0165dcf 942 uint8_t *dest = BigBuf_get_addr();
943
944 size_t size=0, idx=0;
945 int clk=0, invert=0, errCnt=0, maxErr=20;
946 uint32_t hi=0;
947 uint64_t lo=0;
948 // Configure to go in 125Khz listen mode
949 LFSetupFPGAForADC(95, true);
950
d10e08ae 951 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
e0165dcf 952
953 WDT_HIT();
954 if (ledcontrol) LED_A_ON();
955
956 DoAcquisition_default(-1,true);
957 size = BigBuf_max_traceLen();
e0165dcf 958 //askdemod and manchester decode
2eec55c8 959 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
fef74fdc 960 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
e0165dcf 961 WDT_HIT();
962
2eec55c8 963 if (errCnt<0) continue;
964
965 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
966 if (errCnt){
967 if (size>64){
968 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
969 hi,
970 (uint32_t)(lo>>32),
971 (uint32_t)lo,
972 (uint32_t)(lo&0xFFFF),
973 (uint32_t)((lo>>16LL) & 0xFF),
974 (uint32_t)(lo & 0xFFFFFF));
975 } else {
976 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
977 (uint32_t)(lo>>32),
978 (uint32_t)lo,
979 (uint32_t)(lo&0xFFFF),
980 (uint32_t)((lo>>16LL) & 0xFF),
981 (uint32_t)(lo & 0xFFFFFF));
e0165dcf 982 }
2eec55c8 983
e0165dcf 984 if (findone){
985 if (ledcontrol) LED_A_OFF();
986 *high=lo>>32;
987 *low=lo & 0xFFFFFFFF;
988 return;
989 }
e0165dcf 990 }
991 WDT_HIT();
2eec55c8 992 hi = lo = size = idx = 0;
993 clk = invert = errCnt = 0;
e0165dcf 994 }
995 DbpString("Stopped");
996 if (ledcontrol) LED_A_OFF();
e09f21fa 997}
998
999void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
1000{
e0165dcf 1001 uint8_t *dest = BigBuf_get_addr();
1002 int idx=0;
1003 uint32_t code=0, code2=0;
1004 uint8_t version=0;
1005 uint8_t facilitycode=0;
1006 uint16_t number=0;
1007 // Configure to go in 125Khz listen mode
1008 LFSetupFPGAForADC(95, true);
1009
d10e08ae 1010 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
e0165dcf 1011 WDT_HIT();
1012 if (ledcontrol) LED_A_ON();
e09f21fa 1013 DoAcquisition_default(-1,true);
1014 //fskdemod and get start index
e0165dcf 1015 WDT_HIT();
1016 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
2eec55c8 1017 if (idx<0) continue;
1018 //valid tag found
1019
1020 //Index map
1021 //0 10 20 30 40 50 60
1022 //| | | | | | |
1023 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1024 //-----------------------------------------------------------------------------
1025 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
1026 //
1027 //XSF(version)facility:codeone+codetwo
1028 //Handle the data
1029 if(findone){ //only print binary if we are doing one
1030 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1031 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1032 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1033 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1034 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1035 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1036 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1037 }
1038 code = bytebits_to_byte(dest+idx,32);
1039 code2 = bytebits_to_byte(dest+idx+32,32);
1040 version = bytebits_to_byte(dest+idx+27,8); //14,4
1041 facilitycode = bytebits_to_byte(dest+idx+18,8);
1042 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1043
1044 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
1045 // if we're only looking for one tag
1046 if (findone){
1047 if (ledcontrol) LED_A_OFF();
1048 //LED_A_OFF();
1049 *high=code;
1050 *low=code2;
1051 return;
e0165dcf 1052 }
2eec55c8 1053 code=code2=0;
1054 version=facilitycode=0;
1055 number=0;
1056 idx=0;
1057
e0165dcf 1058 WDT_HIT();
1059 }
1060 DbpString("Stopped");
1061 if (ledcontrol) LED_A_OFF();
e09f21fa 1062}
1063
1064/*------------------------------
3606ac0a 1065 * T5555/T5557/T5567/T5577 routines
e09f21fa 1066 *------------------------------
1067 */
1068
3606ac0a 1069/* NOTE: T55x7/T5555 configuration register definitions moved to protocols.h */
e09f21fa 1070
1071/*
3606ac0a 1072 * Relevant communication times in microsecond
e09f21fa 1073 * To compensate antenna falling times shorten the write times
1074 * and enlarge the gap ones.
7cfc777b 1075 * Q5 tags seems to have issues when these values changes.
e09f21fa 1076 */
4a3f1a37 1077#define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
1078#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
1079#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
1080#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
7cfc777b 1081#define READ_GAP 52*8
1082
1083// VALUES TAKEN FROM EM4x function: SendForward
1084// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1085// WRITE_GAP = 128; (16*8)
1086// WRITE_1 = 256 32*8; (32*8)
1087
1088// These timings work for 4469/4269/4305 (with the 55*8 above)
1089// WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1090
1091// Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1092// TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1093// Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1094// T0 = TIMER_CLOCK1 / 125000 = 192
1095// 1 Cycle = 8 microseconds(us) == 1 field clock
1096
1097void TurnReadLFOn(int delay) {
1098 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1099 // Give it a bit of time for the resonant antenna to settle.
1100 SpinDelayUs(delay); //155*8 //50*8
1101}
13d77ef9 1102
e09f21fa 1103// Write one bit to card
7cfc777b 1104void T55xxWriteBit(int bit) {
7cfc777b 1105 if (!bit)
3606ac0a 1106 TurnReadLFOn(WRITE_0);
e0165dcf 1107 else
3606ac0a 1108 TurnReadLFOn(WRITE_1);
e0165dcf 1109 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1110 SpinDelayUs(WRITE_GAP);
e09f21fa 1111}
1112
1113// Write one card block in page 0, no lock
be2d41b7 1114void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
7cfc777b 1115 LED_A_ON();
be2d41b7 1116 bool PwdMode = arg & 0x1;
1117 uint8_t Page = (arg & 0x2)>>1;
e0165dcf 1118 uint32_t i = 0;
1119
1120 // Set up FPGA, 125kHz
f4eadf8a 1121 LFSetupFPGAForADC(95, true);
e0165dcf 1122
7cfc777b 1123 // Trigger T55x7 in mode.
e0165dcf 1124 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1125 SpinDelayUs(START_GAP);
1126
7cfc777b 1127 // Opcode 10
e0165dcf 1128 T55xxWriteBit(1);
be2d41b7 1129 T55xxWriteBit(Page); //Page 0
1130 if (PwdMode){
7cfc777b 1131 // Send Pwd
e0165dcf 1132 for (i = 0x80000000; i != 0; i >>= 1)
1133 T55xxWriteBit(Pwd & i);
1134 }
7cfc777b 1135 // Send Lock bit
e0165dcf 1136 T55xxWriteBit(0);
1137
7cfc777b 1138 // Send Data
e0165dcf 1139 for (i = 0x80000000; i != 0; i >>= 1)
1140 T55xxWriteBit(Data & i);
1141
7cfc777b 1142 // Send Block number
e0165dcf 1143 for (i = 0x04; i != 0; i >>= 1)
1144 T55xxWriteBit(Block & i);
1145
7cfc777b 1146 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
e0165dcf 1147 // so wait a little more)
7cfc777b 1148 TurnReadLFOn(20 * 1000);
be2d41b7 1149 //could attempt to do a read to confirm write took
1150 // as the tag should repeat back the new block
1151 // until it is reset, but to confirm it we would
1152 // need to know the current block 0 config mode
e09f21fa 1153
7cfc777b 1154 // turn field off
1155 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1156 cmd_send(CMD_ACK,0,0,0,0,0);
1157 LED_A_OFF();
13d77ef9 1158}
1159
e09f21fa 1160// Read one card block in page 0
8e99ec25 1161void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
7cfc777b 1162 LED_A_ON();
be2d41b7 1163 bool PwdMode = arg0 & 0x1;
1164 uint8_t Page = (arg0 & 0x2) >> 1;
e0165dcf 1165 uint32_t i = 0;
be2d41b7 1166 bool RegReadMode = (Block == 0xFF);
e0165dcf 1167
7cfc777b 1168 //clear buffer now so it does not interfere with timing later
1169 BigBuf_Clear_ext(false);
f4eadf8a 1170
7cfc777b 1171 //make sure block is at max 7
1172 Block &= 0x7;
1173
0c8200f1 1174 // Set up FPGA, 125kHz to power up the tag
f4eadf8a 1175 LFSetupFPGAForADC(95, true);
f4eadf8a 1176
0c8200f1 1177 // Trigger T55x7 Direct Access Mode with start gap
e0165dcf 1178 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1179 SpinDelayUs(START_GAP);
1180
3606ac0a 1181 // Opcode 1[page]
e0165dcf 1182 T55xxWriteBit(1);
be2d41b7 1183 T55xxWriteBit(Page); //Page 0
7cfc777b 1184
be2d41b7 1185 if (PwdMode){
7cfc777b 1186 // Send Pwd
e0165dcf 1187 for (i = 0x80000000; i != 0; i >>= 1)
1188 T55xxWriteBit(Pwd & i);
1189 }
be2d41b7 1190 // Send a zero bit separation
1191 T55xxWriteBit(0);
7cfc777b 1192
be2d41b7 1193 // Send Block number (if direct access mode)
1194 if (!RegReadMode)
8e99ec25 1195 for (i = 0x04; i != 0; i >>= 1)
1196 T55xxWriteBit(Block & i);
e0165dcf 1197
1198 // Turn field on to read the response
7cfc777b 1199 TurnReadLFOn(READ_GAP);
f4eadf8a 1200
7cfc777b 1201 // Acquisition
1202 doT55x7Acquisition();
e0165dcf 1203
7cfc777b 1204 // Turn the field off
e0165dcf 1205 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
7cfc777b 1206 cmd_send(CMD_ACK,0,0,0,0,0);
1207 LED_A_OFF();
e09f21fa 1208}
1209
be2d41b7 1210void T55xxWakeUp(uint32_t Pwd){
1211 LED_B_ON();
1212 uint32_t i = 0;
1213
1214 // Set up FPGA, 125kHz
1215 LFSetupFPGAForADC(95, true);
1216
1217 // Trigger T55x7 Direct Access Mode
1218 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1219 SpinDelayUs(START_GAP);
1220
1221 // Opcode 10
1222 T55xxWriteBit(1);
1223 T55xxWriteBit(0); //Page 0
1224
1225 // Send Pwd
1226 for (i = 0x80000000; i != 0; i >>= 1)
1227 T55xxWriteBit(Pwd & i);
1228
1229 // Turn and leave field on to let the begin repeating transmission
1230 TurnReadLFOn(20*1000);
1231}
e09f21fa 1232
1233/*-------------- Cloning routines -----------*/
3606ac0a 1234
1235void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1236 // write last block first and config block last (if included)
1237 for (uint8_t i = numblocks; i > startblock; i--)
1238 T55xxWriteBlock(blockdata[i-1],i-1,0,0);
1239}
1240
e09f21fa 1241// Copy HID id to card and setup block 0 config
3606ac0a 1242void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1243 uint32_t data[] = {0,0,0,0,0,0,0};
1244 //int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1245 uint8_t last_block = 0;
e0165dcf 1246
3606ac0a 1247 if (longFMT) {
e0165dcf 1248 // Ensure no more than 84 bits supplied
1249 if (hi2>0xFFFFF) {
1250 DbpString("Tags can only have 84 bits.");
1251 return;
1252 }
1253 // Build the 6 data blocks for supplied 84bit ID
1254 last_block = 6;
3606ac0a 1255 // load preamble (1D) & long format identifier (9E manchester encoded)
1256 data[1] = 0x1D96A900 | manchesterEncode2Bytes((hi2 >> 16) & 0xF);
1257 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1258 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1259 data[3] = manchesterEncode2Bytes(hi >> 16);
1260 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1261 data[5] = manchesterEncode2Bytes(lo >> 16);
1262 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1263 } else {
e0165dcf 1264 // Ensure no more than 44 bits supplied
1265 if (hi>0xFFF) {
1266 DbpString("Tags can only have 44 bits.");
1267 return;
1268 }
e0165dcf 1269 // Build the 3 data blocks for supplied 44bit ID
1270 last_block = 3;
3606ac0a 1271 // load preamble
1272 data[1] = 0x1D000000 | manchesterEncode2Bytes(hi & 0xFFF);
1273 data[2] = manchesterEncode2Bytes(lo >> 16);
1274 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
e0165dcf 1275 }
3606ac0a 1276 // load chip config block
1277 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
e0165dcf 1278
1279 LED_D_ON();
1280 // Program the data blocks for supplied ID
1281 // and the block 0 for HID format
3606ac0a 1282 WriteT55xx(data, 0, last_block+1);
e0165dcf 1283
1284 LED_D_OFF();
1285
1286 DbpString("DONE!");
e09f21fa 1287}
1288
1289void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1290{
3606ac0a 1291 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
e09f21fa 1292
e0165dcf 1293 LED_D_ON();
1294 // Program the data blocks for supplied ID
3606ac0a 1295 // and the block 0 config
1296 WriteT55xx(data, 0, 3);
e09f21fa 1297
e0165dcf 1298 LED_D_OFF();
e09f21fa 1299
e0165dcf 1300 DbpString("DONE!");
e09f21fa 1301}
1302
3606ac0a 1303// Clone Indala 64-bit tag by UID to T55x7
1304void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1305 //Program the 2 data blocks for supplied 64bit UID
1306 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1307 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1308 WriteT55xx(data, 0, 3);
1309 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1310 // T5567WriteBlock(0x603E1042,0);
1311 DbpString("DONE!");
1312}
1313// Clone Indala 224-bit tag by UID to T55x7
1314void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7)
1315{
1316 //Program the 7 data blocks for supplied 224bit UID
1317 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1318 // and the block 0 for Indala224 format
1319 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1320 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1321 WriteT55xx(data, 0, 8);
1322 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1323 // T5567WriteBlock(0x603E10E2,0);
1324 DbpString("DONE!");
1325}
1326
e09f21fa 1327// Define 9bit header for EM410x tags
3606ac0a 1328#define EM410X_HEADER 0x1FF
e09f21fa 1329#define EM410X_ID_LENGTH 40
1330
1331void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1332{
e0165dcf 1333 int i, id_bit;
1334 uint64_t id = EM410X_HEADER;
1335 uint64_t rev_id = 0; // reversed ID
1336 int c_parity[4]; // column parity
1337 int r_parity = 0; // row parity
1338 uint32_t clock = 0;
1339
1340 // Reverse ID bits given as parameter (for simpler operations)
1341 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1342 if (i < 32) {
1343 rev_id = (rev_id << 1) | (id_lo & 1);
1344 id_lo >>= 1;
1345 } else {
1346 rev_id = (rev_id << 1) | (id_hi & 1);
1347 id_hi >>= 1;
1348 }
1349 }
1350
1351 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1352 id_bit = rev_id & 1;
1353
1354 if (i % 4 == 0) {
1355 // Don't write row parity bit at start of parsing
1356 if (i)
1357 id = (id << 1) | r_parity;
1358 // Start counting parity for new row
1359 r_parity = id_bit;
1360 } else {
1361 // Count row parity
1362 r_parity ^= id_bit;
1363 }
1364
1365 // First elements in column?
1366 if (i < 4)
1367 // Fill out first elements
1368 c_parity[i] = id_bit;
1369 else
1370 // Count column parity
1371 c_parity[i % 4] ^= id_bit;
1372
1373 // Insert ID bit
1374 id = (id << 1) | id_bit;
1375 rev_id >>= 1;
1376 }
1377
1378 // Insert parity bit of last row
1379 id = (id << 1) | r_parity;
1380
1381 // Fill out column parity at the end of tag
1382 for (i = 0; i < 4; ++i)
1383 id = (id << 1) | c_parity[i];
1384
1385 // Add stop bit
1386 id <<= 1;
1387
1388 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1389 LED_D_ON();
1390
1391 // Write EM410x ID
3606ac0a 1392 uint32_t data[] = {0, id>>32, id & 0xFFFF};
e0165dcf 1393 if (card) {
e0165dcf 1394 clock = (card & 0xFF00) >> 8;
3606ac0a 1395 clock = (clock == 0) ? 64 : clock;
e0165dcf 1396 Dbprintf("Clock rate: %d", clock);
3606ac0a 1397 clock = GetT55xxClockBit(clock);
1398 if (clock == 0) {
e0165dcf 1399 Dbprintf("Invalid clock rate: %d", clock);
1400 return;
1401 }
1402
3606ac0a 1403 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1404 } else {
1405 data[0] = (0x1F << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
e0165dcf 1406 }
3606ac0a 1407
1408 WriteT55xx(data, 0, 3);
e0165dcf 1409
1410 LED_D_OFF();
1411 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1412 (uint32_t)(id >> 32), (uint32_t)id);
e09f21fa 1413}
1414
e09f21fa 1415//-----------------------------------
1416// EM4469 / EM4305 routines
1417//-----------------------------------
1418#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1419#define FWD_CMD_WRITE 0xA
1420#define FWD_CMD_READ 0x9
1421#define FWD_CMD_DISABLE 0x5
1422
1423
1424uint8_t forwardLink_data[64]; //array of forwarded bits
1425uint8_t * forward_ptr; //ptr for forward message preparation
1426uint8_t fwd_bit_sz; //forwardlink bit counter
1427uint8_t * fwd_write_ptr; //forwardlink bit pointer
1428
1429//====================================================================
1430// prepares command bits
1431// see EM4469 spec
1432//====================================================================
1433//--------------------------------------------------------------------
1434uint8_t Prepare_Cmd( uint8_t cmd ) {
e0165dcf 1435 //--------------------------------------------------------------------
e09f21fa 1436
e0165dcf 1437 *forward_ptr++ = 0; //start bit
1438 *forward_ptr++ = 0; //second pause for 4050 code
e09f21fa 1439
e0165dcf 1440 *forward_ptr++ = cmd;
1441 cmd >>= 1;
1442 *forward_ptr++ = cmd;
1443 cmd >>= 1;
1444 *forward_ptr++ = cmd;
1445 cmd >>= 1;
1446 *forward_ptr++ = cmd;
e09f21fa 1447
e0165dcf 1448 return 6; //return number of emited bits
e09f21fa 1449}
1450
1451//====================================================================
1452// prepares address bits
1453// see EM4469 spec
1454//====================================================================
1455
1456//--------------------------------------------------------------------
1457uint8_t Prepare_Addr( uint8_t addr ) {
e0165dcf 1458 //--------------------------------------------------------------------
e09f21fa 1459
e0165dcf 1460 register uint8_t line_parity;
e09f21fa 1461
e0165dcf 1462 uint8_t i;
1463 line_parity = 0;
1464 for(i=0;i<6;i++) {
1465 *forward_ptr++ = addr;
1466 line_parity ^= addr;
1467 addr >>= 1;
1468 }
e09f21fa 1469
e0165dcf 1470 *forward_ptr++ = (line_parity & 1);
e09f21fa 1471
e0165dcf 1472 return 7; //return number of emited bits
e09f21fa 1473}
1474
1475//====================================================================
1476// prepares data bits intreleaved with parity bits
1477// see EM4469 spec
1478//====================================================================
1479
1480//--------------------------------------------------------------------
1481uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
e0165dcf 1482 //--------------------------------------------------------------------
1483
1484 register uint8_t line_parity;
1485 register uint8_t column_parity;
1486 register uint8_t i, j;
1487 register uint16_t data;
1488
1489 data = data_low;
1490 column_parity = 0;
1491
1492 for(i=0; i<4; i++) {
1493 line_parity = 0;
1494 for(j=0; j<8; j++) {
1495 line_parity ^= data;
1496 column_parity ^= (data & 1) << j;
1497 *forward_ptr++ = data;
1498 data >>= 1;
1499 }
1500 *forward_ptr++ = line_parity;
1501 if(i == 1)
1502 data = data_hi;
1503 }
1504
1505 for(j=0; j<8; j++) {
1506 *forward_ptr++ = column_parity;
1507 column_parity >>= 1;
1508 }
1509 *forward_ptr = 0;
1510
1511 return 45; //return number of emited bits
e09f21fa 1512}
1513
1514//====================================================================
1515// Forward Link send function
1516// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1517// fwd_bit_count set with number of bits to be sent
1518//====================================================================
1519void SendForward(uint8_t fwd_bit_count) {
1520
e0165dcf 1521 fwd_write_ptr = forwardLink_data;
1522 fwd_bit_sz = fwd_bit_count;
1523
1524 LED_D_ON();
1525
7cfc777b 1526 // Set up FPGA, 125kHz
1527 LFSetupFPGAForADC(95, true);
e0165dcf 1528
1529 // force 1st mod pulse (start gap must be longer for 4305)
1530 fwd_bit_sz--; //prepare next bit modulation
1531 fwd_write_ptr++;
1532 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1533 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1534 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1535 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1536 SpinDelayUs(16*8); //16 cycles on (8us each)
1537
1538 // now start writting
1539 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1540 if(((*fwd_write_ptr++) & 1) == 1)
1541 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1542 else {
1543 //These timings work for 4469/4269/4305 (with the 55*8 above)
1544 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1545 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1546 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1547 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1548 SpinDelayUs(9*8); //16 cycles on (8us each)
1549 }
1550 }
e09f21fa 1551}
1552
1553void EM4xLogin(uint32_t Password) {
1554
e0165dcf 1555 uint8_t fwd_bit_count;
e09f21fa 1556
e0165dcf 1557 forward_ptr = forwardLink_data;
1558 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1559 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
e09f21fa 1560
e0165dcf 1561 SendForward(fwd_bit_count);
e09f21fa 1562
e0165dcf 1563 //Wait for command to complete
1564 SpinDelay(20);
e09f21fa 1565
1566}
1567
1568void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1569
e0165dcf 1570 uint8_t fwd_bit_count;
1571 uint8_t *dest = BigBuf_get_addr();
7cfc777b 1572 uint16_t bufferlength = BigBuf_max_traceLen();
1573 uint32_t i = 0;
1574
1575 // Clear destination buffer before sending the command
1576 memset(dest, 0x80, bufferlength);
e0165dcf 1577
1578 //If password mode do login
1579 if (PwdMode == 1) EM4xLogin(Pwd);
1580
1581 forward_ptr = forwardLink_data;
1582 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1583 fwd_bit_count += Prepare_Addr( Address );
1584
e0165dcf 1585 // Connect the A/D to the peak-detected low-frequency path.
1586 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1587 // Now set up the SSC to get the ADC samples that are now streaming at us.
1588 FpgaSetupSsc();
1589
1590 SendForward(fwd_bit_count);
1591
1592 // Now do the acquisition
1593 i = 0;
1594 for(;;) {
1595 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1596 AT91C_BASE_SSC->SSC_THR = 0x43;
1597 }
1598 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1599 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1600 i++;
7cfc777b 1601 if (i >= bufferlength) break;
e0165dcf 1602 }
1603 }
1604 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
7cfc777b 1605 cmd_send(CMD_ACK,0,0,0,0,0);
e0165dcf 1606 LED_D_OFF();
e09f21fa 1607}
1608
1609void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1610
e0165dcf 1611 uint8_t fwd_bit_count;
e09f21fa 1612
e0165dcf 1613 //If password mode do login
1614 if (PwdMode == 1) EM4xLogin(Pwd);
e09f21fa 1615
e0165dcf 1616 forward_ptr = forwardLink_data;
1617 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1618 fwd_bit_count += Prepare_Addr( Address );
1619 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
e09f21fa 1620
e0165dcf 1621 SendForward(fwd_bit_count);
e09f21fa 1622
e0165dcf 1623 //Wait for write to complete
1624 SpinDelay(20);
1625 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1626 LED_D_OFF();
e09f21fa 1627}
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