Add: Emv first part of commands
[proxmark3-svn] / armsrc / iso14443a.c
CommitLineData
15c4dc5a 1//-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
12
de77d4ac 13#include "iso14443a.h"
14
b7d3e899 15#include <stdio.h>
16#include <string.h>
e30c654b 17#include "proxmark3.h"
15c4dc5a 18#include "apps.h"
f7e3ed82 19#include "util.h"
902cb3c0 20#include "cmd.h"
15c4dc5a 21#include "iso14443crc.h"
33443e7c 22#include "crapto1/crapto1.h"
20f9a2a1 23#include "mifareutil.h"
de77d4ac 24#include "mifaresniff.h"
3000dc4e 25#include "BigBuf.h"
c872d8c1 26#include "protocols.h"
1f065e1d 27#include "parity.h"
28
de77d4ac 29typedef struct {
30 enum {
31 DEMOD_UNSYNCD,
32 // DEMOD_HALF_SYNCD,
33 // DEMOD_MOD_FIRST_HALF,
34 // DEMOD_NOMOD_FIRST_HALF,
35 DEMOD_MANCHESTER_DATA
36 } state;
37 uint16_t twoBits;
38 uint16_t highCnt;
39 uint16_t bitCount;
40 uint16_t collisionPos;
41 uint16_t syncBit;
42 uint8_t parityBits;
43 uint8_t parityLen;
44 uint16_t shiftReg;
45 uint16_t samples;
46 uint16_t len;
47 uint32_t startTime, endTime;
48 uint8_t *output;
49 uint8_t *parity;
50} tDemod;
51
52typedef enum {
53 MOD_NOMOD = 0,
54 MOD_SECOND_HALF,
55 MOD_FIRST_HALF,
56 MOD_BOTH_HALVES
57 } Modulation_t;
58
59typedef struct {
60 enum {
61 STATE_UNSYNCD,
62 STATE_START_OF_COMMUNICATION,
63 STATE_MILLER_X,
64 STATE_MILLER_Y,
65 STATE_MILLER_Z,
66 // DROP_NONE,
67 // DROP_FIRST_HALF,
68 } state;
69 uint16_t shiftReg;
70 int16_t bitCount;
71 uint16_t len;
72 uint16_t byteCntMax;
73 uint16_t posCnt;
74 uint16_t syncBit;
75 uint8_t parityBits;
76 uint8_t parityLen;
77 uint32_t fourBits;
78 uint32_t startTime, endTime;
79 uint8_t *output;
80 uint8_t *parity;
81} tUart;
c872d8c1 82
534983d7 83static uint32_t iso14a_timeout;
db68bcdb 84#define MAX_ISO14A_TIMEOUT 524288
85
1e262141 86int rsamples = 0;
1e262141 87uint8_t trigger = 0;
b0127e65 88// the block number for the ISO14443-4 PCB
89static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 90
7bc95e2e 91//
92// ISO14443 timing:
93//
94// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
95#define REQUEST_GUARD_TIME (7000/16 + 1)
96// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
97#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
de77d4ac 98// bool LastCommandWasRequest = false;
7bc95e2e 99
100//
101// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
102//
d714d3ef 103// When the PM acts as reader and is receiving tag data, it takes
104// 3 ticks delay in the AD converter
105// 16 ticks until the modulation detector completes and sets curbit
106// 8 ticks until bit_to_arm is assigned from curbit
107// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 108// 4*16 ticks until we measure the time
109// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 110#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 111
112// When the PM acts as a reader and is sending, it takes
113// 4*16 ticks until we can write data to the sending hold register
114// 8*16 ticks until the SHR is transferred to the Sending Shift Register
115// 8 ticks until the first transfer starts
116// 8 ticks later the FPGA samples the data
117// 1 tick to assign mod_sig_coil
118#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
119
120// When the PM acts as tag and is receiving it takes
d714d3ef 121// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 122// 3 ticks for the A/D conversion,
123// 8 ticks on average until the start of the SSC transfer,
124// 8 ticks until the SSC samples the first data
125// 7*16 ticks to complete the transfer from FPGA to ARM
126// 8 ticks until the next ssp_clk rising edge
d714d3ef 127// 4*16 ticks until we measure the time
7bc95e2e 128// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 129#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
7bc95e2e 130
131// The FPGA will report its internal sending delay in
132uint16_t FpgaSendQueueDelay;
133// the 5 first bits are the number of bits buffered in mod_sig_buf
134// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
135#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
136
137// When the PM acts as tag and is sending, it takes
6e49717b 138// 4*16 + 8 ticks until we can write data to the sending hold register
7bc95e2e 139// 8*16 ticks until the SHR is transferred to the Sending Shift Register
6e49717b 140// 8 ticks later the FPGA samples the first data
141// + 16 ticks until assigned to mod_sig
7bc95e2e 142// + 1 tick to assign mod_sig_coil
6e49717b 143// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
144#define DELAY_ARM2AIR_AS_TAG (4*16 + 8 + 8*16 + 8 + 16 + 1 + DELAY_FPGA_QUEUE)
7bc95e2e 145
146// When the PM acts as sniffer and is receiving tag data, it takes
147// 3 ticks A/D conversion
d714d3ef 148// 14 ticks to complete the modulation detection
149// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 150// + the delays in transferring data - which is the same for
151// sniffing reader and tag data and therefore not relevant
d714d3ef 152#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
7bc95e2e 153
d714d3ef 154// When the PM acts as sniffer and is receiving reader data, it takes
155// 2 ticks delay in analogue RF receiver (for the falling edge of the
156// start bit, which marks the start of the communication)
7bc95e2e 157// 3 ticks A/D conversion
d714d3ef 158// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 159// + the delays in transferring data - which is the same for
160// sniffing reader and tag data and therefore not relevant
d714d3ef 161#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 162
163//variables used for timing purposes:
164//these are in ssp_clk cycles:
6a1f2d82 165static uint32_t NextTransferTime;
166static uint32_t LastTimeProxToAirStart;
167static uint32_t LastProxToAirDuration;
7bc95e2e 168
169
170
8f51ddb0 171// CARD TO READER - manchester
72934aa3 172// Sequence D: 11110000 modulation with subcarrier during first half
173// Sequence E: 00001111 modulation with subcarrier during second half
174// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 175// READER TO CARD - miller
72934aa3 176// Sequence X: 00001100 drop after half a period
177// Sequence Y: 00000000 no drop
178// Sequence Z: 11000000 drop at start
179#define SEC_D 0xf0
180#define SEC_E 0x0f
181#define SEC_F 0x00
182#define SEC_X 0x0c
183#define SEC_Y 0x00
184#define SEC_Z 0xc0
15c4dc5a 185
902cb3c0 186void iso14a_set_trigger(bool enable) {
534983d7 187 trigger = enable;
188}
189
d19929cb 190
bb04ef21 191void iso14a_set_timeout(uint32_t timeout) {
b0127e65 192 iso14a_timeout = timeout;
19a700a8 193 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
b0127e65 194}
8556b852 195
19a700a8 196
6e49717b 197static void iso14a_set_ATS_timeout(uint8_t *ats) {
19a700a8 198
199 uint8_t tb1;
200 uint8_t fwi;
201 uint32_t fwt;
202
203 if (ats[0] > 1) { // there is a format byte T0
204 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
205 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
206 tb1 = ats[3];
207 } else {
208 tb1 = ats[2];
209 }
210 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
211 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
212
213 iso14a_set_timeout(fwt/(8*16));
214 }
215 }
216}
217
218
15c4dc5a 219//-----------------------------------------------------------------------------
220// Generate the parity value for a byte sequence
e30c654b 221//
15c4dc5a 222//-----------------------------------------------------------------------------
6a1f2d82 223void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
15c4dc5a 224{
6a1f2d82 225 uint16_t paritybit_cnt = 0;
226 uint16_t paritybyte_cnt = 0;
227 uint8_t parityBits = 0;
228
229 for (uint16_t i = 0; i < iLen; i++) {
230 // Generate the parity bits
1f065e1d 231 parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt));
6a1f2d82 232 if (paritybit_cnt == 7) {
233 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
234 parityBits = 0; // and advance to next Parity Byte
235 paritybyte_cnt++;
236 paritybit_cnt = 0;
237 } else {
238 paritybit_cnt++;
239 }
5f6d6c90 240 }
6a1f2d82 241
242 // save remaining parity bits
243 par[paritybyte_cnt] = parityBits;
244
15c4dc5a 245}
246
534983d7 247void AppendCrc14443a(uint8_t* data, int len)
15c4dc5a 248{
5f6d6c90 249 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 250}
251
6e49717b 252static void AppendCrc14443b(uint8_t* data, int len)
48ece4a7 253{
254 ComputeCrc14443(CRC_14443_B,data,len,data+len,data+len+1);
255}
256
257
7bc95e2e 258//=============================================================================
259// ISO 14443 Type A - Miller decoder
260//=============================================================================
261// Basics:
262// This decoder is used when the PM3 acts as a tag.
263// The reader will generate "pauses" by temporarily switching of the field.
264// At the PM3 antenna we will therefore measure a modulated antenna voltage.
265// The FPGA does a comparison with a threshold and would deliver e.g.:
266// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
267// The Miller decoder needs to identify the following sequences:
268// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
269// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
270// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
271// Note 1: the bitstream may start at any time. We therefore need to sync.
272// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 273//-----------------------------------------------------------------------------
b62a5a84 274static tUart Uart;
15c4dc5a 275
d7aa3739 276// Lookup-Table to decide if 4 raw bits are a modulation.
05ddb52c 277// We accept the following:
278// 0001 - a 3 tick wide pause
279// 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
280// 0111 - a 2 tick wide pause shifted left
281// 1001 - a 2 tick wide pause shifted right
d7aa3739 282const bool Mod_Miller_LUT[] = {
de77d4ac 283 false, true, false, true, false, false, false, true,
284 false, true, false, false, false, false, false, false
d7aa3739 285};
05ddb52c 286#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
287#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
d7aa3739 288
6e49717b 289static void UartReset()
15c4dc5a 290{
7bc95e2e 291 Uart.state = STATE_UNSYNCD;
292 Uart.bitCount = 0;
293 Uart.len = 0; // number of decoded data bytes
6a1f2d82 294 Uart.parityLen = 0; // number of decoded parity bytes
7bc95e2e 295 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
6a1f2d82 296 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 297 Uart.startTime = 0;
298 Uart.endTime = 0;
299}
15c4dc5a 300
6e49717b 301static void UartInit(uint8_t *data, uint8_t *parity)
6a1f2d82 302{
303 Uart.output = data;
304 Uart.parity = parity;
05ddb52c 305 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
6a1f2d82 306 UartReset();
307}
d714d3ef 308
7bc95e2e 309// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
310static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
311{
15c4dc5a 312
ef00343c 313 Uart.fourBits = (Uart.fourBits << 8) | bit;
7bc95e2e 314
0c8d25eb 315 if (Uart.state == STATE_UNSYNCD) { // not yet synced
3fe4ff4f 316
ef00343c 317 Uart.syncBit = 9999; // not set
05ddb52c 318 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
319 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
320 // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern
321 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
48ece4a7 322 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000
323 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000
05ddb52c 324 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
325 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
326 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
327 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
328 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
329 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
330 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
331 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
332
ef00343c 333 if (Uart.syncBit != 9999) { // found a sync bit
334 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
335 Uart.startTime -= Uart.syncBit;
336 Uart.endTime = Uart.startTime;
337 Uart.state = STATE_START_OF_COMMUNICATION;
7bc95e2e 338 }
15c4dc5a 339
7bc95e2e 340 } else {
15c4dc5a 341
ef00343c 342 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
343 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
d7aa3739 344 UartReset();
d7aa3739 345 } else { // Modulation in first half = Sequence Z = logic "0"
7bc95e2e 346 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
347 UartReset();
7bc95e2e 348 } else {
349 Uart.bitCount++;
350 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
351 Uart.state = STATE_MILLER_Z;
352 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
353 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
354 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
355 Uart.parityBits <<= 1; // make room for the parity bit
356 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
357 Uart.bitCount = 0;
358 Uart.shiftReg = 0;
6a1f2d82 359 if((Uart.len&0x0007) == 0) { // every 8 data bytes
360 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
361 Uart.parityBits = 0;
362 }
15c4dc5a 363 }
7bc95e2e 364 }
d7aa3739 365 }
366 } else {
ef00343c 367 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 368 Uart.bitCount++;
369 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
370 Uart.state = STATE_MILLER_X;
371 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
372 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
373 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
374 Uart.parityBits <<= 1; // make room for the new parity bit
375 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
376 Uart.bitCount = 0;
377 Uart.shiftReg = 0;
6a1f2d82 378 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
379 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
380 Uart.parityBits = 0;
381 }
7bc95e2e 382 }
d7aa3739 383 } else { // no modulation in both halves - Sequence Y
7bc95e2e 384 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
15c4dc5a 385 Uart.state = STATE_UNSYNCD;
6a1f2d82 386 Uart.bitCount--; // last "0" was part of EOC sequence
387 Uart.shiftReg <<= 1; // drop it
388 if(Uart.bitCount > 0) { // if we decoded some bits
389 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
390 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
391 Uart.parityBits <<= 1; // add a (void) parity bit
392 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
393 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
de77d4ac 394 return true;
6a1f2d82 395 } else if (Uart.len & 0x0007) { // there are some parity bits to store
396 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
397 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
52bfb955 398 }
399 if (Uart.len) {
de77d4ac 400 return true; // we are finished with decoding the raw data sequence
52bfb955 401 } else {
0c8d25eb 402 UartReset(); // Nothing received - start over
7bc95e2e 403 }
15c4dc5a 404 }
7bc95e2e 405 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
406 UartReset();
7bc95e2e 407 } else { // a logic "0"
408 Uart.bitCount++;
409 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
410 Uart.state = STATE_MILLER_Y;
411 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
412 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
413 Uart.parityBits <<= 1; // make room for the parity bit
414 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
415 Uart.bitCount = 0;
416 Uart.shiftReg = 0;
6a1f2d82 417 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
418 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
419 Uart.parityBits = 0;
420 }
15c4dc5a 421 }
422 }
d7aa3739 423 }
15c4dc5a 424 }
7bc95e2e 425
426 }
15c4dc5a 427
de77d4ac 428 return false; // not finished yet, need more data
15c4dc5a 429}
430
7bc95e2e 431
432
15c4dc5a 433//=============================================================================
e691fc45 434// ISO 14443 Type A - Manchester decoder
15c4dc5a 435//=============================================================================
e691fc45 436// Basics:
7bc95e2e 437// This decoder is used when the PM3 acts as a reader.
e691fc45 438// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
439// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
440// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
441// The Manchester decoder needs to identify the following sequences:
442// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
443// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
444// 8 ticks unmodulated: Sequence F = end of communication
445// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 446// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 447// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 448static tDemod Demod;
15c4dc5a 449
d7aa3739 450// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 451// We accept three or four "1" in any position
7bc95e2e 452const bool Mod_Manchester_LUT[] = {
de77d4ac 453 false, false, false, false, false, false, false, true,
454 false, false, false, true, false, true, true, true
7bc95e2e 455};
456
457#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
458#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 459
2f2d9fc5 460
6e49717b 461static void DemodReset()
e691fc45 462{
7bc95e2e 463 Demod.state = DEMOD_UNSYNCD;
464 Demod.len = 0; // number of decoded data bytes
6a1f2d82 465 Demod.parityLen = 0;
7bc95e2e 466 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
467 Demod.parityBits = 0; //
468 Demod.collisionPos = 0; // Position of collision bit
469 Demod.twoBits = 0xffff; // buffer for 2 Bits
470 Demod.highCnt = 0;
471 Demod.startTime = 0;
472 Demod.endTime = 0;
e691fc45 473}
15c4dc5a 474
6e49717b 475static void DemodInit(uint8_t *data, uint8_t *parity)
6a1f2d82 476{
477 Demod.output = data;
478 Demod.parity = parity;
479 DemodReset();
480}
481
7bc95e2e 482// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
483static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
e691fc45 484{
7bc95e2e 485
486 Demod.twoBits = (Demod.twoBits << 8) | bit;
e691fc45 487
7bc95e2e 488 if (Demod.state == DEMOD_UNSYNCD) {
489
490 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
491 if (Demod.twoBits == 0x0000) {
492 Demod.highCnt++;
493 } else {
494 Demod.highCnt = 0;
495 }
496 } else {
497 Demod.syncBit = 0xFFFF; // not set
498 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
499 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
500 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
501 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
502 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
503 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
504 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
505 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 506 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 507 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
508 Demod.startTime -= Demod.syncBit;
509 Demod.bitCount = offset; // number of decoded data bits
e691fc45 510 Demod.state = DEMOD_MANCHESTER_DATA;
2f2d9fc5 511 }
7bc95e2e 512 }
15c4dc5a 513
7bc95e2e 514 } else {
15c4dc5a 515
7bc95e2e 516 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
517 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 518 if (!Demod.collisionPos) {
519 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
520 }
521 } // modulation in first half only - Sequence D = 1
7bc95e2e 522 Demod.bitCount++;
523 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
524 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 525 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 526 Demod.parityBits <<= 1; // make room for the parity bit
e691fc45 527 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
528 Demod.bitCount = 0;
529 Demod.shiftReg = 0;
6a1f2d82 530 if((Demod.len&0x0007) == 0) { // every 8 data bytes
531 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
532 Demod.parityBits = 0;
533 }
15c4dc5a 534 }
7bc95e2e 535 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
536 } else { // no modulation in first half
537 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 538 Demod.bitCount++;
7bc95e2e 539 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
e691fc45 540 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 541 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 542 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 543 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
544 Demod.bitCount = 0;
545 Demod.shiftReg = 0;
6a1f2d82 546 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
547 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
548 Demod.parityBits = 0;
549 }
15c4dc5a 550 }
7bc95e2e 551 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
e691fc45 552 } else { // no modulation in both halves - End of communication
6a1f2d82 553 if(Demod.bitCount > 0) { // there are some remaining data bits
554 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
555 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
556 Demod.parityBits <<= 1; // add a (void) parity bit
557 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
558 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
de77d4ac 559 return true;
6a1f2d82 560 } else if (Demod.len & 0x0007) { // there are some parity bits to store
561 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
562 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
52bfb955 563 }
564 if (Demod.len) {
de77d4ac 565 return true; // we are finished with decoding the raw data sequence
d7aa3739 566 } else { // nothing received. Start over
567 DemodReset();
e691fc45 568 }
15c4dc5a 569 }
7bc95e2e 570 }
e691fc45 571
572 }
15c4dc5a 573
de77d4ac 574 return false; // not finished yet, need more data
15c4dc5a 575}
576
577//=============================================================================
578// Finally, a `sniffer' for ISO 14443 Type A
579// Both sides of communication!
580//=============================================================================
581
582//-----------------------------------------------------------------------------
583// Record the sequence of commands sent by the reader to the tag, with
584// triggering so that we start recording at the point that the tag is moved
585// near the reader.
586//-----------------------------------------------------------------------------
5cd9ec01
M
587void RAMFUNC SnoopIso14443a(uint8_t param) {
588 // param:
589 // bit 0 - trigger from first card answer
590 // bit 1 - trigger from first reader 7-bit request
591
592 LEDsoff();
5cd9ec01 593
09ffd16e 594 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
595
f71f4deb 596 // Allocate memory from BigBuf for some buffers
597 // free all previous allocations first
598 BigBuf_free();
599
5cd9ec01 600 // The command (reader -> tag) that we're receiving.
f71f4deb 601 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
602 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
6a1f2d82 603
5cd9ec01 604 // The response (tag -> reader) that we're receiving.
f71f4deb 605 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
606 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
5cd9ec01
M
607
608 // The DMA buffer, used to stream samples from the FPGA
f71f4deb 609 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
610
611 // init trace buffer
3000dc4e 612 clear_trace();
de77d4ac 613 set_tracing(true);
f71f4deb 614
7bc95e2e 615 uint8_t *data = dmaBuf;
616 uint8_t previous_data = 0;
5cd9ec01
M
617 int maxDataLen = 0;
618 int dataLen = 0;
de77d4ac 619 bool TagIsActive = false;
620 bool ReaderIsActive = false;
7bc95e2e 621
5cd9ec01 622 // Set up the demodulator for tag -> reader responses.
6a1f2d82 623 DemodInit(receivedResponse, receivedResponsePar);
624
5cd9ec01 625 // Set up the demodulator for the reader -> tag commands
6a1f2d82 626 UartInit(receivedCmd, receivedCmdPar);
627
7bc95e2e 628 // Setup and start DMA.
5cd9ec01 629 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
7bc95e2e 630
09ffd16e 631 // We won't start recording the frames that we acquire until we trigger;
632 // a good trigger condition to get started is probably when we see a
633 // response from the tag.
de77d4ac 634 // triggered == false -- to wait first for card
09ffd16e 635 bool triggered = !(param & 0x03);
636
5cd9ec01 637 // And now we loop, receiving samples.
de77d4ac 638 for(uint32_t rsamples = 0; true; ) {
7bc95e2e 639
5cd9ec01
M
640 if(BUTTON_PRESS()) {
641 DbpString("cancelled by button");
7bc95e2e 642 break;
5cd9ec01 643 }
15c4dc5a 644
5cd9ec01
M
645 LED_A_ON();
646 WDT_HIT();
15c4dc5a 647
5cd9ec01
M
648 int register readBufDataP = data - dmaBuf;
649 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
650 if (readBufDataP <= dmaBufDataP){
651 dataLen = dmaBufDataP - readBufDataP;
652 } else {
7bc95e2e 653 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
654 }
655 // test for length of buffer
656 if(dataLen > maxDataLen) {
657 maxDataLen = dataLen;
f71f4deb 658 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
7bc95e2e 659 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
660 break;
5cd9ec01
M
661 }
662 }
663 if(dataLen < 1) continue;
664
665 // primary buffer was stopped( <-- we lost data!
666 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
667 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
668 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 669 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
670 }
671 // secondary buffer sets as primary, secondary buffer was stopped
672 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
673 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
674 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
675 }
676
677 LED_A_OFF();
7bc95e2e 678
679 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 680
7bc95e2e 681 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
682 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
683 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
684 LED_C_ON();
5cd9ec01 685
7bc95e2e 686 // check - if there is a short 7bit request from reader
de77d4ac 687 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = true;
5cd9ec01 688
7bc95e2e 689 if(triggered) {
6a1f2d82 690 if (!LogTrace(receivedCmd,
691 Uart.len,
692 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
693 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
694 Uart.parity,
de77d4ac 695 true)) break;
7bc95e2e 696 }
697 /* And ready to receive another command. */
48ece4a7 698 UartReset();
7bc95e2e 699 /* And also reset the demod code, which might have been */
700 /* false-triggered by the commands from the reader. */
701 DemodReset();
702 LED_B_OFF();
703 }
704 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 705 }
3be2a5ae 706
7bc95e2e 707 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
708 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
709 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
710 LED_B_ON();
5cd9ec01 711
6a1f2d82 712 if (!LogTrace(receivedResponse,
713 Demod.len,
714 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
715 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
716 Demod.parity,
de77d4ac 717 false)) break;
5cd9ec01 718
de77d4ac 719 if ((!triggered) && (param & 0x01)) triggered = true;
5cd9ec01 720
7bc95e2e 721 // And ready to receive another response.
722 DemodReset();
48ece4a7 723 // And reset the Miller decoder including itS (now outdated) input buffer
724 UartInit(receivedCmd, receivedCmdPar);
725
7bc95e2e 726 LED_C_OFF();
727 }
728 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
729 }
5cd9ec01
M
730 }
731
7bc95e2e 732 previous_data = *data;
733 rsamples++;
5cd9ec01 734 data++;
d714d3ef 735 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
736 data = dmaBuf;
737 }
738 } // main cycle
739
740 DbpString("COMMAND FINISHED");
15c4dc5a 741
7bc95e2e 742 FpgaDisableSscDma();
743 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
3000dc4e 744 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
5cd9ec01 745 LEDsoff();
15c4dc5a 746}
747
15c4dc5a 748//-----------------------------------------------------------------------------
749// Prepare tag messages
750//-----------------------------------------------------------------------------
6a1f2d82 751static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
15c4dc5a 752{
8f51ddb0 753 ToSendReset();
15c4dc5a 754
755 // Correction bit, might be removed when not needed
756 ToSendStuffBit(0);
757 ToSendStuffBit(0);
758 ToSendStuffBit(0);
759 ToSendStuffBit(0);
760 ToSendStuffBit(1); // 1
761 ToSendStuffBit(0);
762 ToSendStuffBit(0);
763 ToSendStuffBit(0);
8f51ddb0 764
15c4dc5a 765 // Send startbit
72934aa3 766 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 767 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 768
6a1f2d82 769 for(uint16_t i = 0; i < len; i++) {
8f51ddb0 770 uint8_t b = cmd[i];
15c4dc5a 771
772 // Data bits
6a1f2d82 773 for(uint16_t j = 0; j < 8; j++) {
15c4dc5a 774 if(b & 1) {
72934aa3 775 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 776 } else {
72934aa3 777 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
778 }
779 b >>= 1;
780 }
15c4dc5a 781
0014cb46 782 // Get the parity bit
6a1f2d82 783 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 784 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 785 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 786 } else {
72934aa3 787 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 788 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 789 }
8f51ddb0 790 }
15c4dc5a 791
8f51ddb0
M
792 // Send stopbit
793 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 794
8f51ddb0
M
795 // Convert from last byte pos to length
796 ToSendMax++;
8f51ddb0
M
797}
798
15c4dc5a 799
8f51ddb0
M
800static void Code4bitAnswerAsTag(uint8_t cmd)
801{
802 int i;
803
5f6d6c90 804 ToSendReset();
8f51ddb0
M
805
806 // Correction bit, might be removed when not needed
807 ToSendStuffBit(0);
808 ToSendStuffBit(0);
809 ToSendStuffBit(0);
810 ToSendStuffBit(0);
811 ToSendStuffBit(1); // 1
812 ToSendStuffBit(0);
813 ToSendStuffBit(0);
814 ToSendStuffBit(0);
815
816 // Send startbit
817 ToSend[++ToSendMax] = SEC_D;
818
819 uint8_t b = cmd;
820 for(i = 0; i < 4; i++) {
821 if(b & 1) {
822 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 823 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
824 } else {
825 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 826 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
827 }
828 b >>= 1;
829 }
830
831 // Send stopbit
832 ToSend[++ToSendMax] = SEC_F;
833
5f6d6c90 834 // Convert from last byte pos to length
835 ToSendMax++;
15c4dc5a 836}
837
6e49717b 838
839static uint8_t *LastReaderTraceTime = NULL;
840
841static void EmLogTraceReader(void) {
842 // remember last reader trace start to fix timing info later
843 LastReaderTraceTime = BigBuf_get_addr() + BigBuf_get_traceLen();
844 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, true);
845}
846
847
848static void FixLastReaderTraceTime(uint32_t tag_StartTime) {
849 uint32_t reader_EndTime = Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG;
850 uint32_t reader_StartTime = Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG;
851 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
852 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
853 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
854 reader_StartTime = tag_StartTime - exact_fdt - reader_modlen;
855 LastReaderTraceTime[0] = (reader_StartTime >> 0) & 0xff;
856 LastReaderTraceTime[1] = (reader_StartTime >> 8) & 0xff;
857 LastReaderTraceTime[2] = (reader_StartTime >> 16) & 0xff;
858 LastReaderTraceTime[3] = (reader_StartTime >> 24) & 0xff;
859}
860
861
862static void EmLogTraceTag(uint8_t *tag_data, uint16_t tag_len, uint8_t *tag_Parity, uint32_t ProxToAirDuration) {
863 uint32_t tag_StartTime = LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG;
864 uint32_t tag_EndTime = (LastTimeProxToAirStart + ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG;
865 LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, false);
866 FixLastReaderTraceTime(tag_StartTime);
867}
868
869
15c4dc5a 870//-----------------------------------------------------------------------------
871// Wait for commands from reader
872// Stop when button is pressed
de77d4ac 873// Or return true when command is captured
15c4dc5a 874//-----------------------------------------------------------------------------
6a1f2d82 875static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
15c4dc5a 876{
877 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
878 // only, since we are receiving, not transmitting).
879 // Signal field is off with the appropriate LED
880 LED_D_OFF();
881 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
882
883 // Now run a `software UART' on the stream of incoming samples.
6a1f2d82 884 UartInit(received, parity);
7bc95e2e 885
886 // clear RXRDY:
887 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 888
889 for(;;) {
890 WDT_HIT();
891
de77d4ac 892 if(BUTTON_PRESS()) return false;
7bc95e2e 893
15c4dc5a 894 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
7bc95e2e 895 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
896 if(MillerDecoding(b, 0)) {
897 *len = Uart.len;
6e49717b 898 EmLogTraceReader();
de77d4ac 899 return true;
15c4dc5a 900 }
7bc95e2e 901 }
15c4dc5a 902 }
903}
28afbd2b 904
6e49717b 905
b35e04a7 906static int EmSend4bitEx(uint8_t resp);
28afbd2b 907int EmSend4bit(uint8_t resp);
b35e04a7 908static int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
909int EmSendCmdEx(uint8_t *resp, uint16_t respLen);
910int EmSendPrecompiledCmd(tag_response_info_t *response_info);
15c4dc5a 911
ce02f6f9 912
6e49717b 913static bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 914 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 915 // This will need the following byte array for a modulation sequence
916 // 144 data bits (18 * 8)
917 // 18 parity bits
918 // 2 Start and stop
919 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
920 // 1 just for the case
921 // ----------- +
922 // 166 bytes, since every bit that needs to be send costs us a byte
923 //
f71f4deb 924
925
ce02f6f9 926 // Prepare the tag modulation bits from the message
6e49717b 927 GetParity(response_info->response, response_info->response_n, &(response_info->par));
928 CodeIso14443aAsTagPar(response_info->response,response_info->response_n, &(response_info->par));
ce02f6f9 929
930 // Make sure we do not exceed the free buffer space
931 if (ToSendMax > max_buffer_size) {
932 Dbprintf("Out of memory, when modulating bits for tag answer:");
6e49717b 933 Dbhexdump(response_info->response_n, response_info->response, false);
ce02f6f9 934 return false;
935 }
936
937 // Copy the byte array, used for this modulation to the buffer position
6e49717b 938 memcpy(response_info->modulation, ToSend, ToSendMax);
ce02f6f9 939
7bc95e2e 940 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
ce02f6f9 941 response_info->modulation_n = ToSendMax;
7bc95e2e 942 response_info->ProxToAirDuration = LastProxToAirDuration;
ce02f6f9 943
944 return true;
945}
946
f71f4deb 947
948// "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
949// Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
6e49717b 950// 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits for the modulation
f71f4deb 951// -> need 273 bytes buffer
952#define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
953
6e49717b 954bool prepare_allocated_tag_modulation(tag_response_info_t* response_info, uint8_t **buffer, size_t *max_buffer_size) {
955
ce02f6f9 956 // Retrieve and store the current buffer index
6e49717b 957 response_info->modulation = *buffer;
ce02f6f9 958
959 // Forward the prepare tag modulation function to the inner function
6e49717b 960 if (prepare_tag_modulation(response_info, *max_buffer_size)) {
961 // Update the free buffer offset and the remaining buffer size
962 *buffer += ToSendMax;
963 *max_buffer_size -= ToSendMax;
ce02f6f9 964 return true;
965 } else {
966 return false;
967 }
968}
969
15c4dc5a 970//-----------------------------------------------------------------------------
971// Main loop of simulated tag: receive commands from reader, decide what
972// response to send, and send it.
973//-----------------------------------------------------------------------------
28afbd2b 974void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
15c4dc5a 975{
81cd0474 976 uint8_t sak;
977
978 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
979 uint8_t response1[2];
980
981 switch (tagType) {
982 case 1: { // MIFARE Classic
983 // Says: I am Mifare 1k - original line
984 response1[0] = 0x04;
985 response1[1] = 0x00;
986 sak = 0x08;
987 } break;
988 case 2: { // MIFARE Ultralight
989 // Says: I am a stupid memory tag, no crypto
990 response1[0] = 0x04;
991 response1[1] = 0x00;
992 sak = 0x00;
993 } break;
994 case 3: { // MIFARE DESFire
995 // Says: I am a DESFire tag, ph33r me
996 response1[0] = 0x04;
997 response1[1] = 0x03;
998 sak = 0x20;
999 } break;
1000 case 4: { // ISO/IEC 14443-4
1001 // Says: I am a javacard (JCOP)
1002 response1[0] = 0x04;
1003 response1[1] = 0x00;
1004 sak = 0x28;
1005 } break;
3fe4ff4f 1006 case 5: { // MIFARE TNP3XXX
1007 // Says: I am a toy
1008 response1[0] = 0x01;
1009 response1[1] = 0x0f;
1010 sak = 0x01;
1011 } break;
81cd0474 1012 default: {
1013 Dbprintf("Error: unkown tagtype (%d)",tagType);
1014 return;
1015 } break;
1016 }
1017
1018 // The second response contains the (mandatory) first 24 bits of the UID
c8b6da22 1019 uint8_t response2[5] = {0x00};
81cd0474 1020
1021 // Check if the uid uses the (optional) part
c8b6da22 1022 uint8_t response2a[5] = {0x00};
1023
81cd0474 1024 if (uid_2nd) {
1025 response2[0] = 0x88;
1026 num_to_bytes(uid_1st,3,response2+1);
1027 num_to_bytes(uid_2nd,4,response2a);
1028 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
1029
1030 // Configure the ATQA and SAK accordingly
1031 response1[0] |= 0x40;
1032 sak |= 0x04;
1033 } else {
1034 num_to_bytes(uid_1st,4,response2);
1035 // Configure the ATQA and SAK accordingly
1036 response1[0] &= 0xBF;
1037 sak &= 0xFB;
1038 }
1039
1040 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1041 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
1042
1043 // Prepare the mandatory SAK (for 4 and 7 byte UID)
c8b6da22 1044 uint8_t response3[3] = {0x00};
81cd0474 1045 response3[0] = sak;
1046 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
1047
1048 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
c8b6da22 1049 uint8_t response3a[3] = {0x00};
81cd0474 1050 response3a[0] = sak & 0xFB;
1051 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1052
254b70a4 1053 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
6a1f2d82 1054 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1055 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1056 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1057 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1058 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 1059 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1060
7bc95e2e 1061 #define TAG_RESPONSE_COUNT 7
1062 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1063 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1064 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1065 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1066 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1067 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1068 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1069 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1070 };
1071
1072 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1073 // Such a response is less time critical, so we can prepare them on the fly
1074 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1075 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1076 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1077 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1078 tag_response_info_t dynamic_response_info = {
1079 .response = dynamic_response_buffer,
1080 .response_n = 0,
1081 .modulation = dynamic_modulation_buffer,
1082 .modulation_n = 0
1083 };
ce02f6f9 1084
09ffd16e 1085 // We need to listen to the high-frequency, peak-detected path.
1086 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1087
f71f4deb 1088 BigBuf_free_keep_EM();
1089
1090 // allocate buffers:
1091 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1092 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
6e49717b 1093 uint8_t *free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1094 size_t free_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
f71f4deb 1095 // clear trace
3000dc4e 1096 clear_trace();
de77d4ac 1097 set_tracing(true);
f71f4deb 1098
7bc95e2e 1099 // Prepare the responses of the anticollision phase
ce02f6f9 1100 // there will be not enough time to do this at the moment the reader sends it REQA
7bc95e2e 1101 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
6e49717b 1102 prepare_allocated_tag_modulation(&responses[i], &free_buffer_pointer, &free_buffer_size);
7bc95e2e 1103 }
15c4dc5a 1104
7bc95e2e 1105 int len = 0;
15c4dc5a 1106
1107 // To control where we are in the protocol
1108 int order = 0;
1109 int lastorder;
1110
1111 // Just to allow some checks
1112 int happened = 0;
1113 int happened2 = 0;
81cd0474 1114 int cmdsRecvd = 0;
15c4dc5a 1115
254b70a4 1116 cmdsRecvd = 0;
7bc95e2e 1117 tag_response_info_t* p_response;
15c4dc5a 1118
254b70a4 1119 LED_A_ON();
1120 for(;;) {
7bc95e2e 1121 // Clean receive command buffer
6a1f2d82 1122 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
ce02f6f9 1123 DbpString("Button press");
254b70a4 1124 break;
1125 }
7bc95e2e 1126
1127 p_response = NULL;
1128
254b70a4 1129 // Okay, look at the command now.
1130 lastorder = order;
1131 if(receivedCmd[0] == 0x26) { // Received a REQUEST
ce02f6f9 1132 p_response = &responses[0]; order = 1;
254b70a4 1133 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
ce02f6f9 1134 p_response = &responses[0]; order = 6;
254b70a4 1135 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
ce02f6f9 1136 p_response = &responses[1]; order = 2;
6a1f2d82 1137 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
ce02f6f9 1138 p_response = &responses[2]; order = 20;
254b70a4 1139 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
ce02f6f9 1140 p_response = &responses[3]; order = 3;
254b70a4 1141 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
ce02f6f9 1142 p_response = &responses[4]; order = 30;
254b70a4 1143 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
b35e04a7 1144 EmSendCmdEx(data+(4*receivedCmd[1]),16);
7bc95e2e 1145 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
5f6d6c90 1146 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
7bc95e2e 1147 p_response = NULL;
254b70a4 1148 } else if(receivedCmd[0] == 0x50) { // Received a HALT
7bc95e2e 1149 p_response = NULL;
254b70a4 1150 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
ce02f6f9 1151 p_response = &responses[5]; order = 7;
254b70a4 1152 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
7bc95e2e 1153 if (tagType == 1 || tagType == 2) { // RATS not supported
1154 EmSend4bit(CARD_NACK_NA);
1155 p_response = NULL;
1156 } else {
1157 p_response = &responses[6]; order = 70;
1158 }
6a1f2d82 1159 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
7bc95e2e 1160 uint32_t nr = bytes_to_num(receivedCmd,4);
1161 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1162 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1163 } else {
1164 // Check for ISO 14443A-4 compliant commands, look at left nibble
1165 switch (receivedCmd[0]) {
1166
1167 case 0x0B:
1168 case 0x0A: { // IBlock (command)
1169 dynamic_response_info.response[0] = receivedCmd[0];
1170 dynamic_response_info.response[1] = 0x00;
1171 dynamic_response_info.response[2] = 0x90;
1172 dynamic_response_info.response[3] = 0x00;
1173 dynamic_response_info.response_n = 4;
1174 } break;
1175
1176 case 0x1A:
1177 case 0x1B: { // Chaining command
1178 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1179 dynamic_response_info.response_n = 2;
1180 } break;
1181
1182 case 0xaa:
1183 case 0xbb: {
1184 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1185 dynamic_response_info.response_n = 2;
1186 } break;
1187
1188 case 0xBA: { //
1189 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1190 dynamic_response_info.response_n = 2;
1191 } break;
1192
1193 case 0xCA:
1194 case 0xC2: { // Readers sends deselect command
1195 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1196 dynamic_response_info.response_n = 2;
1197 } break;
1198
1199 default: {
1200 // Never seen this command before
7bc95e2e 1201 Dbprintf("Received unknown command (len=%d):",len);
1202 Dbhexdump(len,receivedCmd,false);
1203 // Do not respond
1204 dynamic_response_info.response_n = 0;
1205 } break;
1206 }
ce02f6f9 1207
7bc95e2e 1208 if (dynamic_response_info.response_n > 0) {
1209 // Copy the CID from the reader query
1210 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1211
7bc95e2e 1212 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1213 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1214 dynamic_response_info.response_n += 2;
ce02f6f9 1215
7bc95e2e 1216 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1217 Dbprintf("Error preparing tag response");
7bc95e2e 1218 break;
1219 }
1220 p_response = &dynamic_response_info;
1221 }
81cd0474 1222 }
15c4dc5a 1223
1224 // Count number of wakeups received after a halt
1225 if(order == 6 && lastorder == 5) { happened++; }
1226
1227 // Count number of other messages after a halt
1228 if(order != 6 && lastorder == 5) { happened2++; }
1229
15c4dc5a 1230 if(cmdsRecvd > 999) {
1231 DbpString("1000 commands later...");
254b70a4 1232 break;
15c4dc5a 1233 }
ce02f6f9 1234 cmdsRecvd++;
1235
1236 if (p_response != NULL) {
b35e04a7 1237 EmSendPrecompiledCmd(p_response);
7bc95e2e 1238 }
1239
1240 if (!tracing) {
1241 Dbprintf("Trace Full. Simulation stopped.");
1242 break;
1243 }
1244 }
15c4dc5a 1245
1246 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1247 LED_A_OFF();
f71f4deb 1248 BigBuf_free_keep_EM();
15c4dc5a 1249}
1250
9492e0b0 1251
1252// prepare a delayed transfer. This simply shifts ToSend[] by a number
1253// of bits specified in the delay parameter.
6e49717b 1254static void PrepareDelayedTransfer(uint16_t delay)
9492e0b0 1255{
1256 uint8_t bitmask = 0;
1257 uint8_t bits_to_shift = 0;
1258 uint8_t bits_shifted = 0;
1259
1260 delay &= 0x07;
1261 if (delay) {
1262 for (uint16_t i = 0; i < delay; i++) {
1263 bitmask |= (0x01 << i);
1264 }
7bc95e2e 1265 ToSend[ToSendMax++] = 0x00;
9492e0b0 1266 for (uint16_t i = 0; i < ToSendMax; i++) {
1267 bits_to_shift = ToSend[i] & bitmask;
1268 ToSend[i] = ToSend[i] >> delay;
1269 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1270 bits_shifted = bits_to_shift;
1271 }
1272 }
1273}
1274
7bc95e2e 1275
1276//-------------------------------------------------------------------------------------
15c4dc5a 1277// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1278// Parameter timing:
7bc95e2e 1279// if NULL: transfer at next possible time, taking into account
1280// request guard time and frame delay time
1281// if == 0: transfer immediately and return time of transfer
9492e0b0 1282// if != 0: delay transfer until time specified
7bc95e2e 1283//-------------------------------------------------------------------------------------
6a1f2d82 1284static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
15c4dc5a 1285{
7bc95e2e 1286
9492e0b0 1287 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1288
7bc95e2e 1289 uint32_t ThisTransferTime = 0;
e30c654b 1290
9492e0b0 1291 if (timing) {
1292 if(*timing == 0) { // Measure time
7bc95e2e 1293 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
9492e0b0 1294 } else {
1295 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1296 }
7bc95e2e 1297 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1298 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1299 LastTimeProxToAirStart = *timing;
1300 } else {
1301 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1302 while(GetCountSspClk() < ThisTransferTime);
1303 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1304 }
1305
7bc95e2e 1306 // clear TXRDY
1307 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1308
7bc95e2e 1309 uint16_t c = 0;
9492e0b0 1310 for(;;) {
1311 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1312 AT91C_BASE_SSC->SSC_THR = cmd[c];
1313 c++;
1314 if(c >= len) {
1315 break;
1316 }
1317 }
1318 }
7bc95e2e 1319
1320 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
15c4dc5a 1321}
1322
7bc95e2e 1323
15c4dc5a 1324//-----------------------------------------------------------------------------
195af472 1325// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1326//-----------------------------------------------------------------------------
6e49717b 1327static void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
15c4dc5a 1328{
7bc95e2e 1329 int i, j;
1330 int last;
1331 uint8_t b;
e30c654b 1332
7bc95e2e 1333 ToSendReset();
e30c654b 1334
7bc95e2e 1335 // Start of Communication (Seq. Z)
1336 ToSend[++ToSendMax] = SEC_Z;
1337 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1338 last = 0;
1339
1340 size_t bytecount = nbytes(bits);
1341 // Generate send structure for the data bits
1342 for (i = 0; i < bytecount; i++) {
1343 // Get the current byte to send
1344 b = cmd[i];
1345 size_t bitsleft = MIN((bits-(i*8)),8);
1346
1347 for (j = 0; j < bitsleft; j++) {
1348 if (b & 1) {
1349 // Sequence X
1350 ToSend[++ToSendMax] = SEC_X;
1351 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1352 last = 1;
1353 } else {
1354 if (last == 0) {
1355 // Sequence Z
1356 ToSend[++ToSendMax] = SEC_Z;
1357 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1358 } else {
1359 // Sequence Y
1360 ToSend[++ToSendMax] = SEC_Y;
1361 last = 0;
1362 }
1363 }
1364 b >>= 1;
1365 }
1366
6a1f2d82 1367 // Only transmit parity bit if we transmitted a complete byte
48ece4a7 1368 if (j == 8 && parity != NULL) {
7bc95e2e 1369 // Get the parity bit
6a1f2d82 1370 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1371 // Sequence X
1372 ToSend[++ToSendMax] = SEC_X;
1373 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1374 last = 1;
1375 } else {
1376 if (last == 0) {
1377 // Sequence Z
1378 ToSend[++ToSendMax] = SEC_Z;
1379 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1380 } else {
1381 // Sequence Y
1382 ToSend[++ToSendMax] = SEC_Y;
1383 last = 0;
1384 }
1385 }
1386 }
1387 }
e30c654b 1388
7bc95e2e 1389 // End of Communication: Logic 0 followed by Sequence Y
1390 if (last == 0) {
1391 // Sequence Z
1392 ToSend[++ToSendMax] = SEC_Z;
1393 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1394 } else {
1395 // Sequence Y
1396 ToSend[++ToSendMax] = SEC_Y;
1397 last = 0;
1398 }
1399 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1400
7bc95e2e 1401 // Convert to length of command:
1402 ToSendMax++;
15c4dc5a 1403}
1404
0c8d25eb 1405
9ca155ba
M
1406//-----------------------------------------------------------------------------
1407// Wait for commands from reader
1408// Stop when button is pressed (return 1) or field was gone (return 2)
1409// Or return 0 when command is captured
1410//-----------------------------------------------------------------------------
6e49717b 1411int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
9ca155ba
M
1412{
1413 *len = 0;
1414
1415 uint32_t timer = 0, vtime = 0;
1416 int analogCnt = 0;
1417 int analogAVG = 0;
1418
9ca155ba
M
1419 // Set ADC to read field strength
1420 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1421 AT91C_BASE_ADC->ADC_MR =
0c8d25eb 1422 ADC_MODE_PRESCALE(63) |
1423 ADC_MODE_STARTUP_TIME(1) |
1424 ADC_MODE_SAMPLE_HOLD_TIME(15);
9ca155ba
M
1425 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1426 // start ADC
1427 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1428
b35e04a7 1429 // Run a 'software UART' on the stream of incoming samples.
6a1f2d82 1430 UartInit(received, parity);
7bc95e2e 1431
b35e04a7 1432 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN
1433 do {
1434 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1435 AT91C_BASE_SSC->SSC_THR = SEC_F;
1436 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; (void) b;
1437 }
1438 } while (GetCountSspClk() < LastTimeProxToAirStart + LastProxToAirDuration + (FpgaSendQueueDelay>>3));
1439
1440 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1441 // only, since we are receiving, not transmitting).
1442 // Signal field is off with the appropriate LED
1443 LED_D_OFF();
1444 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1445
9ca155ba
M
1446 for(;;) {
1447 WDT_HIT();
1448
1449 if (BUTTON_PRESS()) return 1;
1450
1451 // test if the field exists
1452 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1453 analogCnt++;
1454 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1455 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1456 if (analogCnt >= 32) {
0c8d25eb 1457 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
9ca155ba
M
1458 vtime = GetTickCount();
1459 if (!timer) timer = vtime;
1460 // 50ms no field --> card to idle state
1461 if (vtime - timer > 50) return 2;
1462 } else
1463 if (timer) timer = 0;
1464 analogCnt = 0;
1465 analogAVG = 0;
1466 }
1467 }
7bc95e2e 1468
9ca155ba 1469 // receive and test the miller decoding
7bc95e2e 1470 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
b35e04a7 1471 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1472 if(MillerDecoding(b, 0)) {
1473 *len = Uart.len;
6e49717b 1474 EmLogTraceReader();
9ca155ba
M
1475 return 0;
1476 }
7bc95e2e 1477 }
1478
9ca155ba
M
1479 }
1480}
1481
9ca155ba 1482
b35e04a7 1483static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen)
7bc95e2e 1484{
1485 uint8_t b;
1486 uint16_t i = 0;
b35e04a7 1487 bool correctionNeeded;
1488
9ca155ba
M
1489 // Modulate Manchester
1490 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1491
1492 // include correction bit if necessary
b35e04a7 1493 if (Uart.bitCount == 7)
1494 {
1495 // Short tags (7 bits) don't have parity, determine the correct value from MSB
1496 correctionNeeded = Uart.output[0] & 0x40;
1497 }
1498 else
1499 {
1500 // Look at the last parity bit
1501 correctionNeeded = Uart.parity[(Uart.len-1)/8] & (0x80 >> ((Uart.len-1) & 7));
7bc95e2e 1502 }
b35e04a7 1503
7bc95e2e 1504 if(correctionNeeded) {
9ca155ba
M
1505 // 1236, so correction bit needed
1506 i = 0;
7bc95e2e 1507 } else {
1508 i = 1;
9ca155ba 1509 }
7bc95e2e 1510
d714d3ef 1511 // clear receiving shift register and holding register
7bc95e2e 1512 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1513 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1514 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1515 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
9ca155ba 1516
7bc95e2e 1517 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1518 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1519 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1520 if (AT91C_BASE_SSC->SSC_RHR) break;
1521 }
1522
6e49717b 1523 LastTimeProxToAirStart = (GetCountSspClk() & 0xfffffff8) + (correctionNeeded?8:0);
7bc95e2e 1524
9ca155ba 1525 // send cycle
bb42a03e 1526 for(; i < respLen; ) {
9ca155ba 1527 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1528 AT91C_BASE_SSC->SSC_THR = resp[i++];
1529 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1530 }
7bc95e2e 1531
9ca155ba
M
1532 if(BUTTON_PRESS()) {
1533 break;
1534 }
1535 }
1536
1537 return 0;
1538}
1539
6e49717b 1540
b35e04a7 1541static int EmSend4bitEx(uint8_t resp){
7bc95e2e 1542 Code4bitAnswerAsTag(resp);
b35e04a7 1543 int res = EmSendCmd14443aRaw(ToSend, ToSendMax);
7bc95e2e 1544 // do the tracing for the previous reader request and this tag answer:
6e49717b 1545 EmLogTraceTag(&resp, 1, NULL, LastProxToAirDuration);
0a39986e 1546 return res;
9ca155ba
M
1547}
1548
6e49717b 1549
8f51ddb0 1550int EmSend4bit(uint8_t resp){
b35e04a7 1551 return EmSend4bitEx(resp);
8f51ddb0
M
1552}
1553
6e49717b 1554
b35e04a7 1555static int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1556 CodeIso14443aAsTagPar(resp, respLen, par);
b35e04a7 1557 int res = EmSendCmd14443aRaw(ToSend, ToSendMax);
7bc95e2e 1558 // do the tracing for the previous reader request and this tag answer:
6e49717b 1559 EmLogTraceTag(resp, respLen, par, LastProxToAirDuration);
8f51ddb0
M
1560 return res;
1561}
1562
6e49717b 1563
b35e04a7 1564int EmSendCmdEx(uint8_t *resp, uint16_t respLen){
6a1f2d82 1565 uint8_t par[MAX_PARITY_SIZE];
1566 GetParity(resp, respLen, par);
b35e04a7 1567 return EmSendCmdExPar(resp, respLen, par);
8f51ddb0
M
1568}
1569
6e49717b 1570
6a1f2d82 1571int EmSendCmd(uint8_t *resp, uint16_t respLen){
1572 uint8_t par[MAX_PARITY_SIZE];
1573 GetParity(resp, respLen, par);
b35e04a7 1574 return EmSendCmdExPar(resp, respLen, par);
8f51ddb0
M
1575}
1576
6e49717b 1577
6a1f2d82 1578int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
b35e04a7 1579 return EmSendCmdExPar(resp, respLen, par);
7bc95e2e 1580}
1581
6e49717b 1582
b35e04a7 1583int EmSendPrecompiledCmd(tag_response_info_t *response_info) {
1584 int ret = EmSendCmd14443aRaw(response_info->modulation, response_info->modulation_n);
6e49717b 1585 // do the tracing for the previous reader request and this tag answer:
1586 EmLogTraceTag(response_info->response, response_info->response_n, &(response_info->par), response_info->ProxToAirDuration);
1587 return ret;
9ca155ba
M
1588}
1589
6e49717b 1590
15c4dc5a 1591//-----------------------------------------------------------------------------
1592// Wait a certain time for tag response
de77d4ac 1593// If a response is captured return true
1594// If it takes too long return false
15c4dc5a 1595//-----------------------------------------------------------------------------
6a1f2d82 1596static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
15c4dc5a 1597{
52bfb955 1598 uint32_t c;
e691fc45 1599
15c4dc5a 1600 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1601 // only, since we are receiving, not transmitting).
1602 // Signal field is on with the appropriate LED
1603 LED_D_ON();
1604 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1c611bbd 1605
534983d7 1606 // Now get the answer from the card
6a1f2d82 1607 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 1608
7bc95e2e 1609 // clear RXRDY:
1610 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1611
15c4dc5a 1612 c = 0;
1613 for(;;) {
534983d7 1614 WDT_HIT();
15c4dc5a 1615
534983d7 1616 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1617 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1618 if(ManchesterDecoding(b, offset, 0)) {
1619 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
de77d4ac 1620 return true;
19a700a8 1621 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
de77d4ac 1622 return false;
15c4dc5a 1623 }
534983d7 1624 }
1625 }
15c4dc5a 1626}
1627
48ece4a7 1628
6a1f2d82 1629void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
15c4dc5a 1630{
6a1f2d82 1631 CodeIso14443aBitsAsReaderPar(frame, bits, par);
dfc3c505 1632
7bc95e2e 1633 // Send command to tag
1634 TransmitFor14443a(ToSend, ToSendMax, timing);
1635 if(trigger)
1636 LED_A_ON();
dfc3c505 1637
7bc95e2e 1638 // Log reader command in trace buffer
1639 if (tracing) {
de77d4ac 1640 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, true);
7bc95e2e 1641 }
15c4dc5a 1642}
1643
48ece4a7 1644
6a1f2d82 1645void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
dfc3c505 1646{
6a1f2d82 1647 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1648}
15c4dc5a 1649
48ece4a7 1650
6e49717b 1651static void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
e691fc45 1652{
1653 // Generate parity and redirect
6a1f2d82 1654 uint8_t par[MAX_PARITY_SIZE];
1655 GetParity(frame, len/8, par);
1656 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1657}
1658
48ece4a7 1659
6a1f2d82 1660void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
15c4dc5a 1661{
1662 // Generate parity and redirect
6a1f2d82 1663 uint8_t par[MAX_PARITY_SIZE];
1664 GetParity(frame, len, par);
1665 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1666}
1667
6e49717b 1668
1669static int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
e691fc45 1670{
de77d4ac 1671 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return false;
7bc95e2e 1672 if (tracing) {
de77d4ac 1673 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, false);
7bc95e2e 1674 }
e691fc45 1675 return Demod.len;
1676}
1677
6e49717b 1678
6a1f2d82 1679int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
15c4dc5a 1680{
de77d4ac 1681 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return false;
7bc95e2e 1682 if (tracing) {
de77d4ac 1683 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, false);
7bc95e2e 1684 }
e691fc45 1685 return Demod.len;
f89c7050
M
1686}
1687
de77d4ac 1688// performs iso14443a anticollision (optional) and card select procedure
1689// fills the uid and cuid pointer unless NULL
1690// fills the card info record unless NULL
1691// if anticollision is false, then the UID must be provided in uid_ptr[]
1692// and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
c04a4b60 1693// requests ATS unless no_rats is true
1694int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades, bool no_rats) {
6a1f2d82 1695 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1696 uint8_t sel_all[] = { 0x93,0x20 };
1697 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1698 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
f71f4deb 1699 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1700 uint8_t resp_par[MAX_PARITY_SIZE];
6a1f2d82 1701 byte_t uid_resp[4];
1702 size_t uid_resp_len;
1703
1704 uint8_t sak = 0x04; // cascade uid
1705 int cascade_level = 0;
1706 int len;
1707
618c220c
OM
1708 // init card struct
1709 if(p_hi14a_card) {
1710 p_hi14a_card->uidlen = 0;
1711 memset(p_hi14a_card->uid, 0, 10);
1712 p_hi14a_card->ats_len = 0;
1713 }
1714
6a1f2d82 1715 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
de77d4ac 1716 ReaderTransmitBitsPar(wupa, 7, NULL, NULL);
7bc95e2e 1717
6a1f2d82 1718 // Receive the ATQA
1719 if(!ReaderReceive(resp, resp_par)) return 0;
6a1f2d82 1720
1721 if(p_hi14a_card) {
1722 memcpy(p_hi14a_card->atqa, resp, 2);
6a1f2d82 1723 }
5f6d6c90 1724
de77d4ac 1725 if (anticollision) {
1726 // clear uid
1727 if (uid_ptr) {
1728 memset(uid_ptr,0,10);
1729 }
6a1f2d82 1730 }
79a73ab2 1731
ee1eadee 1732 // check for proprietary anticollision:
1733 if ((resp[0] & 0x1F) == 0) {
1734 return 3;
1735 }
1736
6a1f2d82 1737 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1738 // which case we need to make a cascade 2 request and select - this is a long UID
1739 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1740 for(; sak & 0x04; cascade_level++) {
1741 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1742 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1743
de77d4ac 1744 if (anticollision) {
1745 // SELECT_ALL
1746 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1747 if (!ReaderReceive(resp, resp_par)) return 0;
1748
1749 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1750 memset(uid_resp, 0, 4);
1751 uint16_t uid_resp_bits = 0;
1752 uint16_t collision_answer_offset = 0;
1753 // anti-collision-loop:
1754 while (Demod.collisionPos) {
1755 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1756 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1757 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1758 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1759 }
1760 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1761 uid_resp_bits++;
1762 // construct anticollosion command:
1763 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1764 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1765 sel_uid[2+i] = uid_resp[i];
1766 }
1767 collision_answer_offset = uid_resp_bits%8;
1768 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1769 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
6a1f2d82 1770 }
de77d4ac 1771 // finally, add the last bits and BCC of the UID
1772 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1773 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1774 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
6a1f2d82 1775 }
de77d4ac 1776
1777 } else { // no collision, use the response to SELECT_ALL as current uid
1778 memcpy(uid_resp, resp, 4);
e691fc45 1779 }
de77d4ac 1780 } else {
1781 if (cascade_level < num_cascades - 1) {
1782 uid_resp[0] = 0x88;
1783 memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3);
1784 } else {
1785 memcpy(uid_resp, uid_ptr+cascade_level*3, 4);
e691fc45 1786 }
6a1f2d82 1787 }
1788 uid_resp_len = 4;
5f6d6c90 1789
6a1f2d82 1790 // calculate crypto UID. Always use last 4 Bytes.
1791 if(cuid_ptr) {
1792 *cuid_ptr = bytes_to_num(uid_resp, 4);
1793 }
e30c654b 1794
6a1f2d82 1795 // Construct SELECT UID command
1796 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
de77d4ac 1797 memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID
6a1f2d82 1798 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1799 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1800 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1801
1802 // Receive the SAK
1803 if (!ReaderReceive(resp, resp_par)) return 0;
1804 sak = resp[0];
de77d4ac 1805
1806 // Test if more parts of the uid are coming
6a1f2d82 1807 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1808 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1809 // http://www.nxp.com/documents/application_note/AN10927.pdf
6a1f2d82 1810 uid_resp[0] = uid_resp[1];
1811 uid_resp[1] = uid_resp[2];
1812 uid_resp[2] = uid_resp[3];
6a1f2d82 1813 uid_resp_len = 3;
1814 }
5f6d6c90 1815
de77d4ac 1816 if(uid_ptr && anticollision) {
6a1f2d82 1817 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1818 }
5f6d6c90 1819
6a1f2d82 1820 if(p_hi14a_card) {
1821 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1822 p_hi14a_card->uidlen += uid_resp_len;
1823 }
1824 }
79a73ab2 1825
6a1f2d82 1826 if(p_hi14a_card) {
1827 p_hi14a_card->sak = sak;
6a1f2d82 1828 }
534983d7 1829
7376da5c 1830 // PICC compilant with iso14443a-4 ---> (SAK & 0x20 != 0)
3fe4ff4f 1831 if( (sak & 0x20) == 0) return 2;
534983d7 1832
c04a4b60 1833 if (!no_rats) {
1834 // Request for answer to select
1835 AppendCrc14443a(rats, 2);
1836 ReaderTransmit(rats, sizeof(rats), NULL);
1c611bbd 1837
c04a4b60 1838 if (!(len = ReaderReceive(resp, resp_par))) return 0;
5191b3d1 1839
c04a4b60 1840 if(p_hi14a_card) {
1841 memcpy(p_hi14a_card->ats, resp, len);
1842 p_hi14a_card->ats_len = len;
1843 }
19a700a8 1844
c04a4b60 1845 // reset the PCB block number
1846 iso14_pcb_blocknum = 0;
19a700a8 1847
c04a4b60 1848 // set default timeout based on ATS
1849 iso14a_set_ATS_timeout(resp);
1850 }
6a1f2d82 1851 return 1;
7e758047 1852}
15c4dc5a 1853
6e49717b 1854
7bc95e2e 1855void iso14443a_setup(uint8_t fpga_minor_mode) {
7cc204bf 1856 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 1857 // Set up the synchronous serial port
1858 FpgaSetupSsc();
7bc95e2e 1859 // connect Demodulated Signal to ADC:
7e758047 1860 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
e30c654b 1861
7e758047 1862 // Signal field is on with the appropriate LED
7bc95e2e 1863 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1864 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1865 LED_D_ON();
1866 } else {
1867 LED_D_OFF();
1868 }
1869 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
534983d7 1870
7bc95e2e 1871 // Start the timer
1872 StartCountSspClk();
1873
1874 DemodReset();
1875 UartReset();
1876 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
6e49717b 1877 iso14a_set_timeout(1060); // 10ms default
7e758047 1878}
15c4dc5a 1879
ba4f95b4 1880/* Peter Fillmore 2015
1881Added card id field to the function
1882 info from ISO14443A standard
1883b1 = Block Number
1884b2 = RFU (always 1)
1885b3 = depends on block
1886b4 = Card ID following if set to 1
1887b5 = depends on block type
1888b6 = depends on block type
1889b7,b8 = block type.
1890Coding of I-BLOCK:
1891b8 b7 b6 b5 b4 b3 b2 b1
18920 0 0 x x x 1 x
1893b5 = chaining bit
1894Coding of R-block:
1895b8 b7 b6 b5 b4 b3 b2 b1
18961 0 1 x x 0 1 x
1897b5 = ACK/NACK
1898Coding of S-block:
1899b8 b7 b6 b5 b4 b3 b2 b1
19001 1 x x x 0 1 0
1901b5,b6 = 00 - DESELECT
1902 11 - WTX
1903*/
6a1f2d82 1904int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1905 uint8_t parity[MAX_PARITY_SIZE];
b7d3e899 1906 uint8_t real_cmd[cmd_len + 4];
1907
1908 // ISO 14443 APDU frame: PCB [CID] [NAD] APDU CRC PCB=0x02
1909 real_cmd[0] = 0x02; // bnr,nad,cid,chn=0; i-block(0x00)
b0127e65 1910 // put block number into the PCB
1911 real_cmd[0] |= iso14_pcb_blocknum;
b7d3e899 1912 memcpy(real_cmd + 1, cmd, cmd_len);
1913 AppendCrc14443a(real_cmd, cmd_len + 1);
534983d7 1914
b7d3e899 1915 ReaderTransmit(real_cmd, cmd_len + 3, NULL);
1916
6a1f2d82 1917 size_t len = ReaderReceive(data, parity);
1918 uint8_t *data_bytes = (uint8_t *) data;
b7d3e899 1919
1920 if (!len) {
b0127e65 1921 return 0; //DATA LINK ERROR
b7d3e899 1922 } else{
a63505c9 1923 // S-Block WTX
1924 while((data_bytes[0] & 0xF2) == 0xF2) {
db68bcdb 1925 uint32_t save_iso14a_timeout = iso14a_timeout;
1926 // temporarily increase timeout
1927 iso14a_timeout = MAX((data_bytes[1] & 0x3f) * iso14a_timeout, MAX_ISO14A_TIMEOUT);
a63505c9 1928 // Transmit WTX back
1929 // byte1 - WTXM [1..59]. command FWT=FWT*WTXM
1930 data_bytes[1] = data_bytes[1] & 0x3f; // 2 high bits mandatory set to 0b
1931 // now need to fix CRC.
1932 AppendCrc14443a(data_bytes, len - 2);
1933 // transmit S-Block
1934 ReaderTransmit(data_bytes, len, NULL);
db68bcdb 1935 // retrieve the result again (with increased timeout)
a63505c9 1936 len = ReaderReceive(data, parity);
1937 data_bytes = data;
db68bcdb 1938 // restore timeout
1939 iso14a_timeout = save_iso14a_timeout;
a63505c9 1940 }
1941
1942 // if we received an I- or R(ACK)-Block with a block number equal to the
1943 // current block number, toggle the current block number
b7d3e899 1944 if (len >= 3 // PCB+CRC = 3 bytes
b0127e65 1945 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1946 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1947 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
b7d3e899 1948 {
1949 iso14_pcb_blocknum ^= 1;
1950 }
b0127e65 1951
b7d3e899 1952 // crc check
1953 if (len >=3 && !CheckCrc14443(CRC_14443_A, data_bytes, len)) {
1954 return -1;
1955 }
1956
1957 }
1958
1959 // cut frame byte
1960 len -= 1;
1961 // memmove(data_bytes, data_bytes + 1, len);
1962 for (int i = 0; i < len; i++)
1963 data_bytes[i] = data_bytes[i + 1];
1964
534983d7 1965 return len;
1966}
1967
6e49717b 1968
7e758047 1969//-----------------------------------------------------------------------------
1970// Read an ISO 14443a tag. Send out commands and store answers.
1971//
1972//-----------------------------------------------------------------------------
7bc95e2e 1973void ReaderIso14443a(UsbCommand *c)
7e758047 1974{
534983d7 1975 iso14a_command_t param = c->arg[0];
7bc95e2e 1976 uint8_t *cmd = c->d.asBytes;
04bc1c66 1977 size_t len = c->arg[1] & 0xffff;
1978 size_t lenbits = c->arg[1] >> 16;
1979 uint32_t timeout = c->arg[2];
9492e0b0 1980 uint32_t arg0 = 0;
618c220c 1981 byte_t buf[USB_CMD_DATA_SIZE] = {0};
6a1f2d82 1982 uint8_t par[MAX_PARITY_SIZE];
f1a983a3 1983 bool cantSELECT = false;
902cb3c0 1984
eb6e8de4 1985 set_tracing(true);
1986
1987 if(param & ISO14A_CLEAR_TRACE) {
3000dc4e 1988 clear_trace();
5f6d6c90 1989 }
e691fc45 1990
79a73ab2 1991 if(param & ISO14A_REQUEST_TRIGGER) {
de77d4ac 1992 iso14a_set_trigger(true);
9492e0b0 1993 }
15c4dc5a 1994
534983d7 1995 if(param & ISO14A_CONNECT) {
f1a983a3 1996 LED_A_ON();
7bc95e2e 1997 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 1998 if(!(param & ISO14A_NO_SELECT)) {
1999 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
c04a4b60 2000 arg0 = iso14443a_select_card(NULL, card, NULL, true, 0, param & ISO14A_NO_RATS);
f1a983a3 2001
2002 // if we cant select then we cant send data
499df908 2003 if (arg0 != 1 && arg0 != 2) {
2004 // 1 - all is OK with ATS, 2 - without ATS
2005 cantSELECT = true;
2006 }
f1a983a3 2007
2008 LED_B_ON();
5f6d6c90 2009 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
f1a983a3 2010 LED_B_OFF();
5f6d6c90 2011 }
534983d7 2012 }
e30c654b 2013
534983d7 2014 if(param & ISO14A_SET_TIMEOUT) {
04bc1c66 2015 iso14a_set_timeout(timeout);
534983d7 2016 }
e30c654b 2017
f1a983a3 2018 if(param & ISO14A_APDU && !cantSELECT) {
902cb3c0 2019 arg0 = iso14_apdu(cmd, len, buf);
f1a983a3 2020 LED_B_ON();
b7d3e899 2021 cmd_send(CMD_ACK, arg0, 0, 0, buf, sizeof(buf));
f1a983a3 2022 LED_B_OFF();
534983d7 2023 }
e30c654b 2024
f1a983a3 2025 if(param & ISO14A_RAW && !cantSELECT) {
534983d7 2026 if(param & ISO14A_APPEND_CRC) {
48ece4a7 2027 if(param & ISO14A_TOPAZMODE) {
2028 AppendCrc14443b(cmd,len);
2029 } else {
2030 AppendCrc14443a(cmd,len);
2031 }
534983d7 2032 len += 2;
c7324bef 2033 if (lenbits) lenbits += 16;
15c4dc5a 2034 }
48ece4a7 2035 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
2036 if(param & ISO14A_TOPAZMODE) {
2037 int bits_to_send = lenbits;
2038 uint16_t i = 0;
2039 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
2040 bits_to_send -= 7;
2041 while (bits_to_send > 0) {
2042 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
2043 bits_to_send -= 8;
2044 }
2045 } else {
2046 GetParity(cmd, lenbits/8, par);
2047 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
2048 }
2049 } else { // want to send complete bytes only
2050 if(param & ISO14A_TOPAZMODE) {
2051 uint16_t i = 0;
2052 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
2053 while (i < len) {
2054 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
2055 }
2056 } else {
2057 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
2058 }
5f6d6c90 2059 }
6a1f2d82 2060 arg0 = ReaderReceive(buf, par);
f1a983a3 2061
2062 LED_B_ON();
9492e0b0 2063 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
f1a983a3 2064 LED_B_OFF();
534983d7 2065 }
15c4dc5a 2066
79a73ab2 2067 if(param & ISO14A_REQUEST_TRIGGER) {
de77d4ac 2068 iso14a_set_trigger(false);
9492e0b0 2069 }
15c4dc5a 2070
79a73ab2 2071 if(param & ISO14A_NO_DISCONNECT) {
534983d7 2072 return;
9492e0b0 2073 }
15c4dc5a 2074
15c4dc5a 2075 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2076 LEDsoff();
15c4dc5a 2077}
b0127e65 2078
1c611bbd 2079
1c611bbd 2080// Determine the distance between two nonces.
2081// Assume that the difference is small, but we don't know which is first.
2082// Therefore try in alternating directions.
6e49717b 2083static int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
1c611bbd 2084
2085 uint16_t i;
2086 uint32_t nttmp1, nttmp2;
e772353f 2087
1c611bbd 2088 if (nt1 == nt2) return 0;
2089
2090 nttmp1 = nt1;
2091 nttmp2 = nt2;
2092
2093 for (i = 1; i < 32768; i++) {
2094 nttmp1 = prng_successor(nttmp1, 1);
2095 if (nttmp1 == nt2) return i;
2096 nttmp2 = prng_successor(nttmp2, 1);
dc8ba239 2097 if (nttmp2 == nt1) return -i;
1c611bbd 2098 }
2099
2100 return(-99999); // either nt1 or nt2 are invalid nonces
e772353f 2101}
2102
e772353f 2103
1c611bbd 2104//-----------------------------------------------------------------------------
2105// Recover several bits of the cypher stream. This implements (first stages of)
2106// the algorithm described in "The Dark Side of Security by Obscurity and
2107// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2108// (article by Nicolas T. Courtois, 2009)
2109//-----------------------------------------------------------------------------
2110void ReaderMifare(bool first_try)
2111{
2112 // Mifare AUTH
2113 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2114 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2115 static uint8_t mf_nr_ar3;
e772353f 2116
f71f4deb 2117 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
2118 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
7bc95e2e 2119
09ffd16e 2120 if (first_try) {
2121 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2122 }
2123
f71f4deb 2124 // free eventually allocated BigBuf memory. We want all for tracing.
2125 BigBuf_free();
2126
3000dc4e 2127 clear_trace();
de77d4ac 2128 set_tracing(true);
e772353f 2129
1c611bbd 2130 byte_t nt_diff = 0;
6a1f2d82 2131 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
1c611bbd 2132 static byte_t par_low = 0;
de77d4ac 2133 bool led_on = true;
ca4714cd 2134 uint8_t uid[10] ={0};
1c611bbd 2135 uint32_t cuid;
e772353f 2136
6a1f2d82 2137 uint32_t nt = 0;
2ed270a8 2138 uint32_t previous_nt = 0;
1c611bbd 2139 static uint32_t nt_attacked = 0;
3fe4ff4f 2140 byte_t par_list[8] = {0x00};
2141 byte_t ks_list[8] = {0x00};
e772353f 2142
dfb387bf 2143 #define PRNG_SEQUENCE_LENGTH (1 << 16);
1c611bbd 2144 static uint32_t sync_time;
8c6b2298 2145 static int32_t sync_cycles;
1c611bbd 2146 int catch_up_cycles = 0;
2147 int last_catch_up = 0;
8c6b2298 2148 uint16_t elapsed_prng_sequences;
1c611bbd 2149 uint16_t consecutive_resyncs = 0;
2150 int isOK = 0;
e772353f 2151
1c611bbd 2152 if (first_try) {
1c611bbd 2153 mf_nr_ar3 = 0;
7bc95e2e 2154 sync_time = GetCountSspClk() & 0xfffffff8;
dfb387bf 2155 sync_cycles = PRNG_SEQUENCE_LENGTH; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the tag nonces).
1c611bbd 2156 nt_attacked = 0;
6a1f2d82 2157 par[0] = 0;
1c611bbd 2158 }
2159 else {
2160 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
1c611bbd 2161 mf_nr_ar3++;
2162 mf_nr_ar[3] = mf_nr_ar3;
6a1f2d82 2163 par[0] = par_low;
1c611bbd 2164 }
e30c654b 2165
15c4dc5a 2166 LED_A_ON();
2167 LED_B_OFF();
2168 LED_C_OFF();
1c611bbd 2169
dc8ba239 2170
dfb387bf 2171 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
8c6b2298 2172 #define MAX_SYNC_TRIES 32
2173 #define NUM_DEBUG_INFOS 8 // per strategy
2174 #define MAX_STRATEGY 3
dfb387bf 2175 uint16_t unexpected_random = 0;
2176 uint16_t sync_tries = 0;
2177 int16_t debug_info_nr = -1;
8c6b2298 2178 uint16_t strategy = 0;
2179 int32_t debug_info[MAX_STRATEGY][NUM_DEBUG_INFOS];
2180 uint32_t select_time;
2181 uint32_t halt_time;
dc8ba239 2182
de77d4ac 2183 for(uint16_t i = 0; true; i++) {
1c611bbd 2184
dc8ba239 2185 LED_C_ON();
1c611bbd 2186 WDT_HIT();
e30c654b 2187
1c611bbd 2188 // Test if the action was cancelled
2189 if(BUTTON_PRESS()) {
dc8ba239 2190 isOK = -1;
1c611bbd 2191 break;
2192 }
2193
8c6b2298 2194 if (strategy == 2) {
2195 // test with additional hlt command
2196 halt_time = 0;
2197 int len = mifare_sendcmd_short(NULL, false, 0x50, 0x00, receivedAnswer, receivedAnswerPar, &halt_time);
2198 if (len && MF_DBGLEVEL >= 3) {
2199 Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len);
2200 }
2201 }
2202
2203 if (strategy == 3) {
2204 // test with FPGA power off/on
2205 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2206 SpinDelay(200);
2207 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2208 SpinDelay(100);
2209 }
2210
c04a4b60 2211 if(!iso14443a_select_card(uid, NULL, &cuid, true, 0, true)) {
9492e0b0 2212 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
1c611bbd 2213 continue;
2214 }
8c6b2298 2215 select_time = GetCountSspClk();
1c611bbd 2216
8c6b2298 2217 elapsed_prng_sequences = 1;
dfb387bf 2218 if (debug_info_nr == -1) {
2219 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2220 catch_up_cycles = 0;
1c611bbd 2221
dfb387bf 2222 // if we missed the sync time already, advance to the next nonce repeat
2223 while(GetCountSspClk() > sync_time) {
8c6b2298 2224 elapsed_prng_sequences++;
dfb387bf 2225 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2226 }
e30c654b 2227
dfb387bf 2228 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2229 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2230 } else {
8c6b2298 2231 // collect some information on tag nonces for debugging:
2232 #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH
2233 if (strategy == 0) {
2234 // nonce distances at fixed time after card select:
2235 sync_time = select_time + DEBUG_FIXED_SYNC_CYCLES;
2236 } else if (strategy == 1) {
2237 // nonce distances at fixed time between authentications:
2238 sync_time = sync_time + DEBUG_FIXED_SYNC_CYCLES;
2239 } else if (strategy == 2) {
2240 // nonce distances at fixed time after halt:
2241 sync_time = halt_time + DEBUG_FIXED_SYNC_CYCLES;
2242 } else {
2243 // nonce_distances at fixed time after power on
2244 sync_time = DEBUG_FIXED_SYNC_CYCLES;
2245 }
2246 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
dfb387bf 2247 }
f89c7050 2248
1c611bbd 2249 // Receive the (4 Byte) "random" nonce
6a1f2d82 2250 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2251 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
1c611bbd 2252 continue;
2253 }
2254
1c611bbd 2255 previous_nt = nt;
2256 nt = bytes_to_num(receivedAnswer, 4);
2257
2258 // Transmit reader nonce with fake par
9492e0b0 2259 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
1c611bbd 2260
2261 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2262 int nt_distance = dist_nt(previous_nt, nt);
2263 if (nt_distance == 0) {
2264 nt_attacked = nt;
dfb387bf 2265 } else {
dc8ba239 2266 if (nt_distance == -99999) { // invalid nonce received
dfb387bf 2267 unexpected_random++;
8c6b2298 2268 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
dc8ba239 2269 isOK = -3; // Card has an unpredictable PRNG. Give up
2270 break;
2271 } else {
2272 continue; // continue trying...
2273 }
1c611bbd 2274 }
dfb387bf 2275 if (++sync_tries > MAX_SYNC_TRIES) {
8c6b2298 2276 if (strategy > MAX_STRATEGY || MF_DBGLEVEL < 3) {
dfb387bf 2277 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2278 break;
2279 } else { // continue for a while, just to collect some debug info
8c6b2298 2280 debug_info[strategy][debug_info_nr] = nt_distance;
2281 debug_info_nr++;
2282 if (debug_info_nr == NUM_DEBUG_INFOS) {
2283 strategy++;
2284 debug_info_nr = 0;
2285 }
dfb387bf 2286 continue;
2287 }
2288 }
8c6b2298 2289 sync_cycles = (sync_cycles - nt_distance/elapsed_prng_sequences);
dfb387bf 2290 if (sync_cycles <= 0) {
2291 sync_cycles += PRNG_SEQUENCE_LENGTH;
2292 }
2293 if (MF_DBGLEVEL >= 3) {
8c6b2298 2294 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
dfb387bf 2295 }
1c611bbd 2296 continue;
2297 }
2298 }
2299
2300 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2301 catch_up_cycles = -dist_nt(nt_attacked, nt);
2302 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2303 catch_up_cycles = 0;
2304 continue;
2305 }
8c6b2298 2306 catch_up_cycles /= elapsed_prng_sequences;
1c611bbd 2307 if (catch_up_cycles == last_catch_up) {
2308 consecutive_resyncs++;
2309 }
2310 else {
2311 last_catch_up = catch_up_cycles;
2312 consecutive_resyncs = 0;
2313 }
2314 if (consecutive_resyncs < 3) {
9492e0b0 2315 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
1c611bbd 2316 }
2317 else {
2318 sync_cycles = sync_cycles + catch_up_cycles;
9492e0b0 2319 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
8c6b2298 2320 last_catch_up = 0;
2321 catch_up_cycles = 0;
2322 consecutive_resyncs = 0;
1c611bbd 2323 }
2324 continue;
2325 }
2326
2327 consecutive_resyncs = 0;
2328
2329 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
8c6b2298 2330 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2331 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
1c611bbd 2332
8c6b2298 2333 if (nt_diff == 0) {
6a1f2d82 2334 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2335 }
2336
2337 led_on = !led_on;
2338 if(led_on) LED_B_ON(); else LED_B_OFF();
2339
6a1f2d82 2340 par_list[nt_diff] = SwapBits(par[0], 8);
1c611bbd 2341 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2342
2343 // Test if the information is complete
2344 if (nt_diff == 0x07) {
2345 isOK = 1;
2346 break;
2347 }
2348
2349 nt_diff = (nt_diff + 1) & 0x07;
2350 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
6a1f2d82 2351 par[0] = par_low;
1c611bbd 2352 } else {
2353 if (nt_diff == 0 && first_try)
2354 {
6a1f2d82 2355 par[0]++;
dc8ba239 2356 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2357 isOK = -2;
2358 break;
2359 }
1c611bbd 2360 } else {
6a1f2d82 2361 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2362 }
2363 }
2364 }
2365
1c611bbd 2366
2367 mf_nr_ar[3] &= 0x1F;
dfb387bf 2368
2369 if (isOK == -4) {
2370 if (MF_DBGLEVEL >= 3) {
8c6b2298 2371 for (uint16_t i = 0; i <= MAX_STRATEGY; i++) {
2372 for(uint16_t j = 0; j < NUM_DEBUG_INFOS; j++) {
2373 Dbprintf("collected debug info[%d][%d] = %d", i, j, debug_info[i][j]);
2374 }
dfb387bf 2375 }
2376 }
2377 }
1c611bbd 2378
2379 byte_t buf[28];
2380 memcpy(buf + 0, uid, 4);
2381 num_to_bytes(nt, 4, buf + 4);
2382 memcpy(buf + 8, par_list, 8);
2383 memcpy(buf + 16, ks_list, 8);
2384 memcpy(buf + 24, mf_nr_ar, 4);
2385
dc8ba239 2386 cmd_send(CMD_ACK, isOK, 0, 0, buf, 28);
1c611bbd 2387
2388 // Thats it...
2389 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2390 LEDsoff();
7bc95e2e 2391
de77d4ac 2392 set_tracing(false);
20f9a2a1 2393}
1c611bbd 2394
d2f487af 2395
b62a5a84
M
2396//-----------------------------------------------------------------------------
2397// MIFARE sniffer.
2398//
2399//-----------------------------------------------------------------------------
5cd9ec01
M
2400void RAMFUNC SniffMifare(uint8_t param) {
2401 // param:
2402 // bit 0 - trigger from first card answer
2403 // bit 1 - trigger from first reader 7-bit request
39864b0b
M
2404
2405 // C(red) A(yellow) B(green)
b62a5a84
M
2406 LEDsoff();
2407 // init trace buffer
3000dc4e 2408 clear_trace();
de77d4ac 2409 set_tracing(true);
b62a5a84 2410
b62a5a84
M
2411 // The command (reader -> tag) that we're receiving.
2412 // The length of a received command will in most cases be no more than 18 bytes.
2413 // So 32 should be enough!
f71f4deb 2414 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2415 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
b62a5a84 2416 // The response (tag -> reader) that we're receiving.
f71f4deb 2417 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
2418 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
b62a5a84 2419
09ffd16e 2420 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2421
f71f4deb 2422 // free eventually allocated BigBuf memory
2423 BigBuf_free();
2424 // allocate the DMA buffer, used to stream samples from the FPGA
2425 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
7bc95e2e 2426 uint8_t *data = dmaBuf;
2427 uint8_t previous_data = 0;
5cd9ec01
M
2428 int maxDataLen = 0;
2429 int dataLen = 0;
de77d4ac 2430 bool ReaderIsActive = false;
2431 bool TagIsActive = false;
7bc95e2e 2432
b62a5a84 2433 // Set up the demodulator for tag -> reader responses.
6a1f2d82 2434 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
2435
2436 // Set up the demodulator for the reader -> tag commands
6a1f2d82 2437 UartInit(receivedCmd, receivedCmdPar);
b62a5a84
M
2438
2439 // Setup for the DMA.
7bc95e2e 2440 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
b62a5a84 2441
b62a5a84 2442 LED_D_OFF();
39864b0b
M
2443
2444 // init sniffer
2445 MfSniffInit();
b62a5a84 2446
b62a5a84 2447 // And now we loop, receiving samples.
de77d4ac 2448 for(uint32_t sniffCounter = 0; true; ) {
7bc95e2e 2449
5cd9ec01
M
2450 if(BUTTON_PRESS()) {
2451 DbpString("cancelled by button");
7bc95e2e 2452 break;
5cd9ec01
M
2453 }
2454
b62a5a84
M
2455 LED_A_ON();
2456 WDT_HIT();
39864b0b 2457
7bc95e2e 2458 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2459 // check if a transaction is completed (timeout after 2000ms).
2460 // if yes, stop the DMA transfer and send what we have so far to the client
2461 if (MfSniffSend(2000)) {
2462 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2463 sniffCounter = 0;
2464 data = dmaBuf;
2465 maxDataLen = 0;
de77d4ac 2466 ReaderIsActive = false;
2467 TagIsActive = false;
7bc95e2e 2468 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
39864b0b 2469 }
39864b0b 2470 }
7bc95e2e 2471
2472 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2473 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2474 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2475 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2476 } else {
2477 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
5cd9ec01
M
2478 }
2479 // test for length of buffer
7bc95e2e 2480 if(dataLen > maxDataLen) { // we are more behind than ever...
2481 maxDataLen = dataLen;
f71f4deb 2482 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
5cd9ec01 2483 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 2484 break;
b62a5a84
M
2485 }
2486 }
5cd9ec01 2487 if(dataLen < 1) continue;
b62a5a84 2488
7bc95e2e 2489 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
2490 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2491 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2492 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
55acbb2a 2493 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
2494 }
2495 // secondary buffer sets as primary, secondary buffer was stopped
2496 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2497 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
2498 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2499 }
5cd9ec01
M
2500
2501 LED_A_OFF();
b62a5a84 2502
7bc95e2e 2503 if (sniffCounter & 0x01) {
b62a5a84 2504
7bc95e2e 2505 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2506 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2507 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2508 LED_C_INV();
de77d4ac 2509 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, true)) break;
b62a5a84 2510
7bc95e2e 2511 /* And ready to receive another command. */
05ddb52c 2512 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 2513
2514 /* And also reset the demod code */
2515 DemodReset();
2516 }
2517 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2518 }
2519
2520 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2521 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2522 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2523 LED_C_INV();
b62a5a84 2524
de77d4ac 2525 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, false)) break;
39864b0b 2526
7bc95e2e 2527 // And ready to receive another response.
2528 DemodReset();
48ece4a7 2529 // And reset the Miller decoder including its (now outdated) input buffer
2530 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 2531 }
2532 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2533 }
b62a5a84
M
2534 }
2535
7bc95e2e 2536 previous_data = *data;
2537 sniffCounter++;
5cd9ec01 2538 data++;
d714d3ef 2539 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01 2540 data = dmaBuf;
b62a5a84 2541 }
7bc95e2e 2542
b62a5a84
M
2543 } // main cycle
2544
2545 DbpString("COMMAND FINISHED");
2546
55acbb2a 2547 FpgaDisableSscDma();
39864b0b
M
2548 MfSniffEnd();
2549
7bc95e2e 2550 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
b62a5a84 2551 LEDsoff();
3803d529 2552}
Impressum, Datenschutz