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replaced obsolete config options with current
[proxmark3-svn] / armsrc / lfops.c
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9bea179a 1//-----------------------------------------------------------------------------\r
2// Miscellaneous routines for low frequency tag operations.\r
3// Tags supported here so far are Texas Instruments (TI), HID\r
4// Also routines for raw mode reading/simulating of LF waveform\r
5//\r
6//-----------------------------------------------------------------------------\r
7#include <proxmark3.h>\r
8#include "apps.h"\r
0fa9ca5b 9#include "hitag2.h"\r
9bea179a 10#include "../common/crc16.c"\r
11\r
6f5cb60c 12int sprintf(char *dest, const char *fmt, ...);\r
13\r
9bea179a 14void AcquireRawAdcSamples125k(BOOL at134khz)\r
15{\r
0d974852 16 if (at134khz)\r
9bea179a 17 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 18 else\r
9bea179a 19 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 20\r
21 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 22\r
23 // Connect the A/D to the peak-detected low-frequency path.\r
24 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
25\r
26 // Give it a bit of time for the resonant antenna to settle.\r
27 SpinDelay(50);\r
28\r
29 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
30 FpgaSetupSsc();\r
31\r
32 // Now call the acquisition routine\r
0d974852 33 DoAcquisition125k();\r
9bea179a 34}\r
35\r
36// split into two routines so we can avoid timing issues after sending commands //\r
0d974852 37void DoAcquisition125k(void)\r
9bea179a 38{\r
39 BYTE *dest = (BYTE *)BigBuf;\r
40 int n = sizeof(BigBuf);\r
41 int i;\r
6f5cb60c 42 \r
0d974852 43 memset(dest, 0, n);\r
9bea179a 44 i = 0;\r
45 for(;;) {\r
6f5cb60c 46 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {\r
6949aca9 47 AT91C_BASE_SSC->SSC_THR = 0x43;\r
9bea179a 48 LED_D_ON();\r
49 }\r
0d974852 50 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r
6949aca9 51 dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
9bea179a 52 i++;\r
53 LED_D_OFF();\r
6f5cb60c 54 if (i >= n) break;\r
9bea179a 55 }\r
56 }\r
a9bc033b 57 Dbprintf("read samples, dest[0]=%x dest[1]=%x", dest[0], dest[1]);\r
9bea179a 58}\r
59\r
0d974852 60void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, BYTE *command)\r
9bea179a 61{\r
62 BOOL at134khz;\r
63\r
0fa9ca5b 64 /* Make sure the tag is reset */\r
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
66 SpinDelay(2500);\r
67 \r
9bea179a 68 // see if 'h' was specified\r
0d974852 69 if (command[strlen((char *) command) - 1] == 'h')\r
70 at134khz = TRUE;\r
9bea179a 71 else\r
0d974852 72 at134khz = FALSE;\r
9bea179a 73\r
0d974852 74 if (at134khz)\r
9bea179a 75 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 76 else\r
9bea179a 77 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 78\r
79 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 80\r
81 // Give it a bit of time for the resonant antenna to settle.\r
82 SpinDelay(50);\r
0fa9ca5b 83 // And a little more time for the tag to fully power up\r
84 SpinDelay(2000);\r
9bea179a 85\r
86 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
87 FpgaSetupSsc();\r
88\r
89 // now modulate the reader field\r
0d974852 90 while(*command != '\0' && *command != ' ') {\r
9bea179a 91 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
92 LED_D_OFF();\r
93 SpinDelayUs(delay_off);\r
0d974852 94 if (at134khz)\r
9bea179a 95 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 96 else\r
9bea179a 97 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 98\r
99 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 100 LED_D_ON();\r
0d974852 101 if(*(command++) == '0')\r
9bea179a 102 SpinDelayUs(period_0);\r
0d974852 103 else\r
9bea179a 104 SpinDelayUs(period_1);\r
0d974852 105 }\r
9bea179a 106 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
107 LED_D_OFF();\r
108 SpinDelayUs(delay_off);\r
0d974852 109 if (at134khz)\r
9bea179a 110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
0d974852 111 else\r
9bea179a 112 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
0d974852 113\r
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
9bea179a 115\r
116 // now do the read\r
0d974852 117 DoAcquisition125k();\r
9bea179a 118}\r
119\r
7381e8f2 120/* blank r/w tag data stream\r
121...0000000000000000 01111111\r
1221010101010101010101010101010101010101010101010101010101010101010\r
1230011010010100001\r
12401111111\r
125101010101010101[0]000...\r
126\r
127[5555fe852c5555555555555555fe0000]\r
128*/\r
0d974852 129void ReadTItag(void)\r
7381e8f2 130{\r
131 // some hardcoded initial params\r
132 // when we read a TI tag we sample the zerocross line at 2Mhz\r
133 // TI tags modulate a 1 as 16 cycles of 123.2Khz\r
134 // TI tags modulate a 0 as 16 cycles of 134.2Khz\r
135 #define FSAMPLE 2000000\r
136 #define FREQLO 123200\r
137 #define FREQHI 134200\r
138\r
139 signed char *dest = (signed char *)BigBuf;\r
140 int n = sizeof(BigBuf);\r
141// int *dest = GraphBuffer;\r
142// int n = GraphTraceLen;\r
143\r
144 // 128 bit shift register [shift3:shift2:shift1:shift0]\r
145 DWORD shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;\r
146\r
147 int i, cycles=0, samples=0;\r
148 // how many sample points fit in 16 cycles of each frequency\r
149 DWORD sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;\r
150 // when to tell if we're close enough to one freq or another\r
151 DWORD threshold = (sampleslo - sampleshi + 1)>>1;\r
152\r
153 // TI tags charge at 134.2Khz\r
154 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
155\r
156 // Place FPGA in passthrough mode, in this mode the CROSS_LO line\r
157 // connects to SSP_DIN and the SSP_DOUT logic level controls\r
158 // whether we're modulating the antenna (high)\r
159 // or listening to the antenna (low)\r
160 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r
161\r
162 // get TI tag data into the buffer\r
163 AcquireTiType();\r
164\r
165 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
166\r
167 for (i=0; i<n-1; i++) {\r
168 // count cycles by looking for lo to hi zero crossings\r
169 if ( (dest[i]<0) && (dest[i+1]>0) ) {\r
170 cycles++;\r
171 // after 16 cycles, measure the frequency\r
172 if (cycles>15) {\r
173 cycles=0;\r
174 samples=i-samples; // number of samples in these 16 cycles\r
175\r
176 // TI bits are coming to us lsb first so shift them\r
177 // right through our 128 bit right shift register\r
178 shift0 = (shift0>>1) | (shift1 << 31);\r
179 shift1 = (shift1>>1) | (shift2 << 31);\r
180 shift2 = (shift2>>1) | (shift3 << 31);\r
181 shift3 >>= 1;\r
182\r
183 // check if the cycles fall close to the number\r
184 // expected for either the low or high frequency\r
185 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {\r
186 // low frequency represents a 1\r
187 shift3 |= (1<<31);\r
188 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {\r
189 // high frequency represents a 0\r
190 } else {\r
191 // probably detected a gay waveform or noise\r
192 // use this as gaydar or discard shift register and start again\r
193 shift3 = shift2 = shift1 = shift0 = 0;\r
194 }\r
195 samples = i;\r
196\r
197 // for each bit we receive, test if we've detected a valid tag\r
198\r
199 // if we see 17 zeroes followed by 6 ones, we might have a tag\r
200 // remember the bits are backwards\r
201 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {\r
202 // if start and end bytes match, we have a tag so break out of the loop\r
203 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {\r
204 cycles = 0xF0B; //use this as a flag (ugly but whatever)\r
205 break;\r
206 }\r
207 }\r
208 }\r
209 }\r
210 }\r
211\r
212 // if flag is set we have a tag\r
213 if (cycles!=0xF0B) {\r
214 DbpString("Info: No valid tag detected.");\r
215 } else {\r
216 // put 64 bit data into shift1 and shift0\r
217 shift0 = (shift0>>24) | (shift1 << 8);\r
218 shift1 = (shift1>>24) | (shift2 << 8);\r
219\r
220 // align 16 bit crc into lower half of shift2\r
221 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;\r
222\r
223 // if r/w tag, check ident match\r
224 if ( shift3&(1<<15) ) {\r
225 DbpString("Info: TI tag is rewriteable");\r
226 // only 15 bits compare, last bit of ident is not valid\r
227 if ( ((shift3>>16)^shift0)&0x7fff ) {\r
228 DbpString("Error: Ident mismatch!");\r
229 } else {\r
230 DbpString("Info: TI tag ident is valid");\r
231 }\r
232 } else {\r
233 DbpString("Info: TI tag is readonly");\r
234 }\r
235\r
236 // WARNING the order of the bytes in which we calc crc below needs checking\r
237 // i'm 99% sure the crc algorithm is correct, but it may need to eat the\r
238 // bytes in reverse or something\r
239 // calculate CRC\r
240 DWORD crc=0;\r
241\r
242 crc = update_crc16(crc, (shift0)&0xff);\r
243 crc = update_crc16(crc, (shift0>>8)&0xff);\r
244 crc = update_crc16(crc, (shift0>>16)&0xff);\r
245 crc = update_crc16(crc, (shift0>>24)&0xff);\r
246 crc = update_crc16(crc, (shift1)&0xff);\r
247 crc = update_crc16(crc, (shift1>>8)&0xff);\r
248 crc = update_crc16(crc, (shift1>>16)&0xff);\r
249 crc = update_crc16(crc, (shift1>>24)&0xff);\r
250\r
a9bc033b 251 Dbprintf("Info: Tag data_hi=%x, data_lo=%x, crc=%x",\r
6f5cb60c 252 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);\r
7381e8f2 253 if (crc != (shift2&0xffff)) {\r
a9bc033b 254 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);\r
7381e8f2 255 } else {\r
256 DbpString("Info: CRC is good");\r
257 }\r
258 }\r
259}\r
260\r
261void WriteTIbyte(BYTE b)\r
262{\r
263 int i = 0;\r
264\r
265 // modulate 8 bits out to the antenna\r
266 for (i=0; i<8; i++)\r
267 {\r
268 if (b&(1<<i)) {\r
269 // stop modulating antenna\r
6949aca9 270 LOW(GPIO_SSC_DOUT);\r
7381e8f2 271 SpinDelayUs(1000);\r
272 // modulate antenna\r
6949aca9 273 HIGH(GPIO_SSC_DOUT);\r
7381e8f2 274 SpinDelayUs(1000);\r
275 } else {\r
276 // stop modulating antenna\r
6949aca9 277 LOW(GPIO_SSC_DOUT);\r
7381e8f2 278 SpinDelayUs(300);\r
279 // modulate antenna\r
6949aca9 280 HIGH(GPIO_SSC_DOUT);\r
7381e8f2 281 SpinDelayUs(1700);\r
282 }\r
283 }\r
284}\r
285\r
9bea179a 286void AcquireTiType(void)\r
287{\r
7381e8f2 288 int i, j, n;\r
9bea179a 289 // tag transmission is <20ms, sampling at 2M gives us 40K samples max\r
290 // each sample is 1 bit stuffed into a DWORD so we need 1250 DWORDS\r
7381e8f2 291 #define TIBUFLEN 1250\r
9bea179a 292\r
293 // clear buffer\r
294 memset(BigBuf,0,sizeof(BigBuf));\r
295\r
296 // Set up the synchronous serial port\r
6949aca9 297 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;\r
298 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;\r
9bea179a 299\r
300 // steal this pin from the SSP and use it to control the modulation\r
6949aca9 301 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
0d974852 302 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
9bea179a 303\r
6949aca9 304 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r
305 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;\r
9bea179a 306\r
6949aca9 307 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long\r
308 // 48/2 = 24 MHz clock must be divided by 12\r
309 AT91C_BASE_SSC->SSC_CMR = 12;\r
9bea179a 310\r
6949aca9 311 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);\r
312 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;\r
313 AT91C_BASE_SSC->SSC_TCMR = 0;\r
314 AT91C_BASE_SSC->SSC_TFMR = 0;\r
9bea179a 315\r
316 LED_D_ON();\r
317\r
318 // modulate antenna\r
6949aca9 319 HIGH(GPIO_SSC_DOUT);\r
9bea179a 320\r
321 // Charge TI tag for 50ms.\r
322 SpinDelay(50);\r
323\r
324 // stop modulating antenna and listen\r
6949aca9 325 LOW(GPIO_SSC_DOUT);\r
9bea179a 326\r
327 LED_D_OFF();\r
328\r
329 i = 0;\r
330 for(;;) {\r
6949aca9 331 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r
332 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer\r
333 i++; if(i >= TIBUFLEN) break;\r
334 }\r
335 WDT_HIT();\r
9bea179a 336 }\r
337\r
338 // return stolen pin to SSP\r
6949aca9 339 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;\r
340 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;\r
9bea179a 341\r
7381e8f2 342 char *dest = (char *)BigBuf;\r
343 n = TIBUFLEN*32;\r
344 // unpack buffer\r
345 for (i=TIBUFLEN-1; i>=0; i--) {\r
346// DbpIntegers(0, 0, BigBuf[i]);\r
347 for (j=0; j<32; j++) {\r
348 if(BigBuf[i] & (1 << j)) {\r
349 dest[--n] = 1;\r
350 } else {\r
351 dest[--n] = -1;\r
352 }\r
9bea179a 353 }\r
354 }\r
355}\r
356\r
9bea179a 357// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc\r
358// if crc provided, it will be written with the data verbatim (even if bogus)\r
359// if not provided a valid crc will be computed from the data and written.\r
360void WriteTItag(DWORD idhi, DWORD idlo, WORD crc)\r
361{\r
362\r
363 // WARNING the order of the bytes in which we calc crc below needs checking\r
364 // i'm 99% sure the crc algorithm is correct, but it may need to eat the\r
365 // bytes in reverse or something\r
366\r
367 if(crc == 0) {\r
368 crc = update_crc16(crc, (idlo)&0xff);\r
369 crc = update_crc16(crc, (idlo>>8)&0xff);\r
370 crc = update_crc16(crc, (idlo>>16)&0xff);\r
371 crc = update_crc16(crc, (idlo>>24)&0xff);\r
372 crc = update_crc16(crc, (idhi)&0xff);\r
373 crc = update_crc16(crc, (idhi>>8)&0xff);\r
374 crc = update_crc16(crc, (idhi>>16)&0xff);\r
375 crc = update_crc16(crc, (idhi>>24)&0xff);\r
376 }\r
a9bc033b 377 Dbprintf("Writing the following data to tag: %x, %x, %x",\r
6f5cb60c 378 (unsigned int) idhi, (unsigned int) idlo, crc);\r
9bea179a 379\r
380 // TI tags charge at 134.2Khz\r
381 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
382 // Place FPGA in passthrough mode, in this mode the CROSS_LO line\r
383 // connects to SSP_DIN and the SSP_DOUT logic level controls\r
384 // whether we're modulating the antenna (high)\r
385 // or listening to the antenna (low)\r
386 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r
387 LED_A_ON();\r
388\r
389 // steal this pin from the SSP and use it to control the modulation\r
6949aca9 390 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
6f5cb60c 391 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
9bea179a 392\r
393 // writing algorithm:\r
394 // a high bit consists of a field off for 1ms and field on for 1ms\r
395 // a low bit consists of a field off for 0.3ms and field on for 1.7ms\r
396 // initiate a charge time of 50ms (field on) then immediately start writing bits\r
397 // start by writing 0xBB (keyword) and 0xEB (password)\r
398 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)\r
399 // finally end with 0x0300 (write frame)\r
400 // all data is sent lsb firts\r
401 // finish with 15ms programming time\r
402\r
403 // modulate antenna\r
6949aca9 404 HIGH(GPIO_SSC_DOUT);\r
9bea179a 405 SpinDelay(50); // charge time\r
406\r
407 WriteTIbyte(0xbb); // keyword\r
408 WriteTIbyte(0xeb); // password\r
409 WriteTIbyte( (idlo )&0xff );\r
410 WriteTIbyte( (idlo>>8 )&0xff );\r
411 WriteTIbyte( (idlo>>16)&0xff );\r
412 WriteTIbyte( (idlo>>24)&0xff );\r
413 WriteTIbyte( (idhi )&0xff );\r
414 WriteTIbyte( (idhi>>8 )&0xff );\r
415 WriteTIbyte( (idhi>>16)&0xff );\r
416 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo\r
417 WriteTIbyte( (crc )&0xff ); // crc lo\r
418 WriteTIbyte( (crc>>8 )&0xff ); // crc hi\r
419 WriteTIbyte(0x00); // write frame lo\r
420 WriteTIbyte(0x03); // write frame hi\r
6949aca9 421 HIGH(GPIO_SSC_DOUT);\r
9bea179a 422 SpinDelay(50); // programming time\r
423\r
424 LED_A_OFF();\r
425\r
426 // get TI tag data into the buffer\r
427 AcquireTiType();\r
428\r
429 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
7381e8f2 430 DbpString("Now use tiread to check");\r
9bea179a 431}\r
432\r
433void SimulateTagLowFrequency(int period, int ledcontrol)\r
434{\r
435 int i;\r
436 BYTE *tab = (BYTE *)BigBuf;\r
437\r
438 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
439\r
6949aca9 440 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;\r
9bea179a 441\r
6949aca9 442 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
443 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;\r
9bea179a 444\r
445#define SHORT_COIL() LOW(GPIO_SSC_DOUT)\r
6949aca9 446#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)\r
9bea179a 447\r
448 i = 0;\r
449 for(;;) {\r
6949aca9 450 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {\r
9bea179a 451 if(BUTTON_PRESS()) {\r
452 DbpString("Stopped");\r
453 return;\r
454 }\r
455 WDT_HIT();\r
456 }\r
457\r
458 if (ledcontrol)\r
459 LED_D_ON();\r
460\r
461 if(tab[i])\r
462 OPEN_COIL();\r
463 else\r
464 SHORT_COIL();\r
465\r
466 if (ledcontrol)\r
467 LED_D_OFF();\r
468\r
6949aca9 469 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {\r
9bea179a 470 if(BUTTON_PRESS()) {\r
471 DbpString("Stopped");\r
472 return;\r
473 }\r
474 WDT_HIT();\r
475 }\r
476\r
477 i++;\r
478 if(i == period) i = 0;\r
479 }\r
480}\r
481\r
0fa9ca5b 482/* Provides a framework for bidirectional LF tag communication\r
483 * Encoding is currently Hitag2, but the general idea can probably\r
484 * be transferred to other encodings.\r
485 * \r
486 * The new FPGA code will, for the LF simulator mode, give on SSC_FRAME\r
487 * (PA15) a thresholded version of the signal from the ADC. Setting the\r
488 * ADC path to the low frequency peak detection signal, will enable a\r
489 * somewhat reasonable receiver for modulation on the carrier signal\r
490 * that is generated by the reader. The signal is low when the reader\r
491 * field is switched off, and high when the reader field is active. Due\r
492 * to the way that the signal looks like, mostly only the rising edge is\r
493 * useful, your mileage may vary.\r
494 * \r
495 * Neat perk: PA15 can not only be used as a bit-banging GPIO, but is also\r
496 * TIOA1, which can be used as the capture input for timer 1. This should\r
497 * make it possible to measure the exact edge-to-edge time, without processor\r
498 * intervention.\r
499 * \r
500 * Arguments: divisor is the divisor to be sent to the FPGA (e.g. 95 for 125kHz)\r
501 * t0 is the carrier frequency cycle duration in terms of MCK (384 for 125kHz)\r
502 * \r
503 * The following defines are in carrier periods: \r
504 */\r
505#define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */ \r
506#define HITAG_T_1_MIN 24 /* T[1] should be 26..30 */\r
507#define HITAG_T_EOF 40 /* T_EOF should be > 36 */\r
508#define HITAG_T_WRESP 208 /* T_wresp should be 204..212 */\r
509\r
510static void hitag_handle_frame(int t0, int frame_len, char *frame);\r
511//#define DEBUG_RA_VALUES 1\r
512#define DEBUG_FRAME_CONTENTS 1\r
513void SimulateTagLowFrequencyBidir(int divisor, int t0)\r
514{\r
515#if DEBUG_RA_VALUES || DEBUG_FRAME_CONTENTS\r
516 int i = 0;\r
517#endif\r
518 char frame[10];\r
519 int frame_pos=0;\r
520 \r
521 DbpString("Starting Hitag2 emulator, press button to end");\r
522 hitag2_init();\r
523 \r
524 /* Set up simulator mode, frequency divisor which will drive the FPGA\r
6949aca9 525 * and analog mux selection.\r
0fa9ca5b 526 */\r
527 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
528 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);\r
529 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
530 RELAY_OFF();\r
531 \r
532 /* Set up Timer 1:\r
533 * Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,\r
534 * external trigger rising edge, load RA on rising edge of TIOA, load RB on rising\r
6949aca9 535 * edge of TIOA. Assign PA15 to TIOA1 (peripheral B)\r
0fa9ca5b 536 */\r
537 \r
6949aca9 538 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);\r
539 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;\r
540 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r
541 AT91C_BASE_TC1->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 |\r
542 AT91C_TC_ETRGEDG_RISING |\r
543 AT91C_TC_ABETRG |\r
544 AT91C_TC_LDRA_RISING |\r
545 AT91C_TC_LDRB_RISING;\r
546 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN |\r
547 AT91C_TC_SWTRG;\r
0fa9ca5b 548 \r
549 /* calculate the new value for the carrier period in terms of TC1 values */\r
550 t0 = t0/2;\r
551 \r
552 int overflow = 0;\r
553 while(!BUTTON_PRESS()) {\r
554 WDT_HIT();\r
6949aca9 555 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {\r
556 int ra = AT91C_BASE_TC1->TC_RA;\r
0fa9ca5b 557 if((ra > t0*HITAG_T_EOF) | overflow) ra = t0*HITAG_T_EOF+1;\r
558#if DEBUG_RA_VALUES\r
559 if(ra > 255 || overflow) ra = 255;\r
560 ((char*)BigBuf)[i] = ra;\r
561 i = (i+1) % 8000;\r
562#endif\r
563 \r
564 if(overflow || (ra > t0*HITAG_T_EOF) || (ra < t0*HITAG_T_0_MIN)) {\r
565 /* Ignore */\r
566 } else if(ra >= t0*HITAG_T_1_MIN ) {\r
567 /* '1' bit */\r
568 if(frame_pos < 8*sizeof(frame)) {\r
569 frame[frame_pos / 8] |= 1<<( 7-(frame_pos%8) );\r
570 frame_pos++;\r
571 }\r
572 } else if(ra >= t0*HITAG_T_0_MIN) {\r
573 /* '0' bit */\r
574 if(frame_pos < 8*sizeof(frame)) {\r
575 frame[frame_pos / 8] |= 0<<( 7-(frame_pos%8) );\r
576 frame_pos++;\r
577 }\r
578 }\r
579 \r
580 overflow = 0;\r
581 LED_D_ON();\r
582 } else {\r
6949aca9 583 if(AT91C_BASE_TC1->TC_CV > t0*HITAG_T_EOF) {\r
0fa9ca5b 584 /* Minor nuisance: In Capture mode, the timer can not be\r
585 * stopped by a Compare C. There's no way to stop the clock\r
586 * in software, so we'll just have to note the fact that an\r
587 * overflow happened and the next loaded timer value might\r
588 * have wrapped. Also, this marks the end of frame, and the\r
589 * still running counter can be used to determine the correct\r
6949aca9 590 * time for the start of the reply.\r
0fa9ca5b 591 */ \r
592 overflow = 1;\r
593 \r
594 if(frame_pos > 0) {\r
595 /* Have a frame, do something with it */\r
596#if DEBUG_FRAME_CONTENTS\r
597 ((char*)BigBuf)[i++] = frame_pos;\r
598 memcpy( ((char*)BigBuf)+i, frame, 7);\r
599 i+=7;\r
600 i = i % sizeof(BigBuf);\r
601#endif\r
602 hitag_handle_frame(t0, frame_pos, frame);\r
603 memset(frame, 0, sizeof(frame));\r
604 }\r
605 frame_pos = 0;\r
606\r
607 }\r
608 LED_D_OFF();\r
609 }\r
610 }\r
611 DbpString("All done");\r
612}\r
613\r
614static void hitag_send_bit(int t0, int bit) {\r
615 if(bit == 1) {\r
616 /* Manchester: Loaded, then unloaded */\r
617 LED_A_ON();\r
618 SHORT_COIL();\r
6949aca9 619 while(AT91C_BASE_TC1->TC_CV < t0*15);\r
0fa9ca5b 620 OPEN_COIL();\r
6949aca9 621 while(AT91C_BASE_TC1->TC_CV < t0*31);\r
0fa9ca5b 622 LED_A_OFF();\r
623 } else if(bit == 0) {\r
624 /* Manchester: Unloaded, then loaded */\r
625 LED_B_ON();\r
626 OPEN_COIL();\r
6949aca9 627 while(AT91C_BASE_TC1->TC_CV < t0*15);\r
0fa9ca5b 628 SHORT_COIL();\r
6949aca9 629 while(AT91C_BASE_TC1->TC_CV < t0*31);\r
0fa9ca5b 630 LED_B_OFF();\r
631 }\r
6949aca9 632 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset clock for the next bit */\r
0fa9ca5b 633 \r
634}\r
635static void hitag_send_frame(int t0, int frame_len, const char const * frame, int fdt)\r
636{\r
637 OPEN_COIL();\r
6949aca9 638 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
0fa9ca5b 639 \r
640 /* Wait for HITAG_T_WRESP carrier periods after the last reader bit,\r
641 * not that since the clock counts since the rising edge, but T_wresp is\r
642 * with respect to the falling edge, we need to wait actually (T_wresp - T_g)\r
6949aca9 643 * periods. The gap time T_g varies (4..10).\r
0fa9ca5b 644 */\r
6949aca9 645 while(AT91C_BASE_TC1->TC_CV < t0*(fdt-8));\r
0fa9ca5b 646\r
6949aca9 647 int saved_cmr = AT91C_BASE_TC1->TC_CMR;\r
648 AT91C_BASE_TC1->TC_CMR &= ~AT91C_TC_ETRGEDG; /* Disable external trigger for the clock */\r
649 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset the clock and use it for response timing */\r
0fa9ca5b 650 \r
651 int i;\r
652 for(i=0; i<5; i++)\r
653 hitag_send_bit(t0, 1); /* Start of frame */\r
654 \r
655 for(i=0; i<frame_len; i++) {\r
656 hitag_send_bit(t0, !!(frame[i/ 8] & (1<<( 7-(i%8) ))) );\r
657 }\r
658 \r
659 OPEN_COIL();\r
6949aca9 660 AT91C_BASE_TC1->TC_CMR = saved_cmr;\r
0fa9ca5b 661}\r
662\r
663/* Callback structure to cleanly separate tag emulation code from the radio layer. */\r
664static int hitag_cb(const char* response_data, const int response_length, const int fdt, void *cb_cookie)\r
665{\r
666 hitag_send_frame(*(int*)cb_cookie, response_length, response_data, fdt);\r
667 return 0;\r
668}\r
669/* Frame length in bits, frame contents in MSBit first format */\r
670static void hitag_handle_frame(int t0, int frame_len, char *frame)\r
671{\r
672 hitag2_handle_command(frame, frame_len, hitag_cb, &t0);\r
673}\r
674\r
9bea179a 675// compose fc/8 fc/10 waveform\r
676static void fc(int c, int *n) {\r
677 BYTE *dest = (BYTE *)BigBuf;\r
678 int idx;\r
679\r
680 // for when we want an fc8 pattern every 4 logical bits\r
681 if(c==0) {\r
682 dest[((*n)++)]=1;\r
683 dest[((*n)++)]=1;\r
684 dest[((*n)++)]=0;\r
685 dest[((*n)++)]=0;\r
686 dest[((*n)++)]=0;\r
687 dest[((*n)++)]=0;\r
688 dest[((*n)++)]=0;\r
689 dest[((*n)++)]=0;\r
690 }\r
691 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples\r
692 if(c==8) {\r
693 for (idx=0; idx<6; idx++) {\r
694 dest[((*n)++)]=1;\r
695 dest[((*n)++)]=1;\r
696 dest[((*n)++)]=0;\r
697 dest[((*n)++)]=0;\r
698 dest[((*n)++)]=0;\r
699 dest[((*n)++)]=0;\r
700 dest[((*n)++)]=0;\r
701 dest[((*n)++)]=0;\r
702 }\r
703 }\r
704\r
705 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples\r
706 if(c==10) {\r
707 for (idx=0; idx<5; idx++) {\r
708 dest[((*n)++)]=1;\r
709 dest[((*n)++)]=1;\r
710 dest[((*n)++)]=1;\r
711 dest[((*n)++)]=0;\r
712 dest[((*n)++)]=0;\r
713 dest[((*n)++)]=0;\r
714 dest[((*n)++)]=0;\r
715 dest[((*n)++)]=0;\r
716 dest[((*n)++)]=0;\r
717 dest[((*n)++)]=0;\r
718 }\r
719 }\r
720}\r
721\r
722// prepare a waveform pattern in the buffer based on the ID given then\r
723// simulate a HID tag until the button is pressed\r
724void CmdHIDsimTAG(int hi, int lo, int ledcontrol)\r
725{\r
726 int n=0, i=0;\r
727 /*\r
728 HID tag bitstream format\r
729 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits\r
730 A 1 bit is represented as 6 fc8 and 5 fc10 patterns\r
731 A 0 bit is represented as 5 fc10 and 6 fc8 patterns\r
732 A fc8 is inserted before every 4 bits\r
733 A special start of frame pattern is used consisting a0b0 where a and b are neither 0\r
734 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)\r
735 */\r
736\r
737 if (hi>0xFFF) {\r
738 DbpString("Tags can only have 44 bits.");\r
739 return;\r
740 }\r
741 fc(0,&n);\r
742 // special start of frame marker containing invalid bit sequences\r
743 fc(8, &n); fc(8, &n); // invalid\r
744 fc(8, &n); fc(10, &n); // logical 0\r
745 fc(10, &n); fc(10, &n); // invalid\r
746 fc(8, &n); fc(10, &n); // logical 0\r
747\r
748 WDT_HIT();\r
749 // manchester encode bits 43 to 32\r
750 for (i=11; i>=0; i--) {\r
751 if ((i%4)==3) fc(0,&n);\r
752 if ((hi>>i)&1) {\r
753 fc(10, &n); fc(8, &n); // low-high transition\r
754 } else {\r
755 fc(8, &n); fc(10, &n); // high-low transition\r
756 }\r
757 }\r
758\r
759 WDT_HIT();\r
760 // manchester encode bits 31 to 0\r
761 for (i=31; i>=0; i--) {\r
762 if ((i%4)==3) fc(0,&n);\r
763 if ((lo>>i)&1) {\r
764 fc(10, &n); fc(8, &n); // low-high transition\r
765 } else {\r
766 fc(8, &n); fc(10, &n); // high-low transition\r
767 }\r
768 }\r
769\r
770 if (ledcontrol)\r
771 LED_A_ON();\r
772 SimulateTagLowFrequency(n, ledcontrol);\r
773\r
774 if (ledcontrol)\r
775 LED_A_OFF();\r
776}\r
777\r
778\r
779// loop to capture raw HID waveform then FSK demodulate the TAG ID from it\r
780void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)\r
781{\r
782 BYTE *dest = (BYTE *)BigBuf;\r
783 int m=0, n=0, i=0, idx=0, found=0, lastval=0;\r
784 DWORD hi=0, lo=0;\r
785\r
786 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
787 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
788\r
789 // Connect the A/D to the peak-detected low-frequency path.\r
790 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
791\r
792 // Give it a bit of time for the resonant antenna to settle.\r
793 SpinDelay(50);\r
794\r
795 // Now set up the SSC to get the ADC samples that are now streaming at us.\r
796 FpgaSetupSsc();\r
797\r
798 for(;;) {\r
799 WDT_HIT();\r
800 if (ledcontrol)\r
801 LED_A_ON();\r
802 if(BUTTON_PRESS()) {\r
803 DbpString("Stopped");\r
804 if (ledcontrol)\r
805 LED_A_OFF();\r
806 return;\r
807 }\r
808\r
809 i = 0;\r
810 m = sizeof(BigBuf);\r
811 memset(dest,128,m);\r
812 for(;;) {\r
6949aca9 813 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
814 AT91C_BASE_SSC->SSC_THR = 0x43;\r
9bea179a 815 if (ledcontrol)\r
816 LED_D_ON();\r
817 }\r
6949aca9 818 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
819 dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
9bea179a 820 // we don't care about actual value, only if it's more or less than a\r
821 // threshold essentially we capture zero crossings for later analysis\r
822 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;\r
823 i++;\r
824 if (ledcontrol)\r
825 LED_D_OFF();\r
826 if(i >= m) {\r
827 break;\r
828 }\r
829 }\r
830 }\r
831\r
832 // FSK demodulator\r
833\r
834 // sync to first lo-hi transition\r
835 for( idx=1; idx<m; idx++) {\r
836 if (dest[idx-1]<dest[idx])\r
837 lastval=idx;\r
838 break;\r
839 }\r
840 WDT_HIT();\r
841\r
842 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)\r
843 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere\r
844 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10\r
845 for( i=0; idx<m; idx++) {\r
846 if (dest[idx-1]<dest[idx]) {\r
847 dest[i]=idx-lastval;\r
848 if (dest[i] <= 8) {\r
849 dest[i]=1;\r
850 } else {\r
851 dest[i]=0;\r
852 }\r
853\r
854 lastval=idx;\r
855 i++;\r
856 }\r
857 }\r
858 m=i;\r
859 WDT_HIT();\r
860\r
861 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns\r
862 lastval=dest[0];\r
863 idx=0;\r
864 i=0;\r
865 n=0;\r
866 for( idx=0; idx<m; idx++) {\r
867 if (dest[idx]==lastval) {\r
868 n++;\r
869 } else {\r
870 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,\r
871 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets\r
872 // swallowed up by rounding\r
873 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding\r
874 // special start of frame markers use invalid manchester states (no transitions) by using sequences\r
875 // like 111000\r
876 if (dest[idx-1]) {\r
877 n=(n+1)/6; // fc/8 in sets of 6\r
878 } else {\r
879 n=(n+1)/5; // fc/10 in sets of 5\r
880 }\r
881 switch (n) { // stuff appropriate bits in buffer\r
882 case 0:\r
883 case 1: // one bit\r
884 dest[i++]=dest[idx-1];\r
885 break;\r
886 case 2: // two bits\r
887 dest[i++]=dest[idx-1];\r
888 dest[i++]=dest[idx-1];\r
889 break;\r
890 case 3: // 3 bit start of frame markers\r
891 dest[i++]=dest[idx-1];\r
892 dest[i++]=dest[idx-1];\r
893 dest[i++]=dest[idx-1];\r
894 break;\r
895 // When a logic 0 is immediately followed by the start of the next transmisson\r
896 // (special pattern) a pattern of 4 bit duration lengths is created.\r
897 case 4:\r
898 dest[i++]=dest[idx-1];\r
899 dest[i++]=dest[idx-1];\r
900 dest[i++]=dest[idx-1];\r
901 dest[i++]=dest[idx-1];\r
902 break;\r
903 default: // this shouldn't happen, don't stuff any bits\r
904 break;\r
905 }\r
906 n=0;\r
907 lastval=dest[idx];\r
908 }\r
909 }\r
910 m=i;\r
911 WDT_HIT();\r
912\r
913 // final loop, go over previously decoded manchester data and decode into usable tag ID\r
914 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0\r
915 for( idx=0; idx<m-6; idx++) {\r
916 // search for a start of frame marker\r
917 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )\r
918 {\r
919 found=1;\r
920 idx+=6;\r
921 if (found && (hi|lo)) {\r
a9bc033b 922 Dbprintf("TAG ID: %x %x %x", \r
6f5cb60c 923 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r
9bea179a 924 /* if we're only looking for one tag */\r
925 if (findone)\r
926 {\r
927 *high = hi;\r
928 *low = lo;\r
929 return;\r
930 }\r
931 hi=0;\r
932 lo=0;\r
933 found=0;\r
934 }\r
935 }\r
936 if (found) {\r
937 if (dest[idx] && (!dest[idx+1]) ) {\r
938 hi=(hi<<1)|(lo>>31);\r
939 lo=(lo<<1)|0;\r
940 } else if ( (!dest[idx]) && dest[idx+1]) {\r
941 hi=(hi<<1)|(lo>>31);\r
942 lo=(lo<<1)|1;\r
943 } else {\r
944 found=0;\r
945 hi=0;\r
946 lo=0;\r
947 }\r
948 idx++;\r
949 }\r
950 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )\r
951 {\r
952 found=1;\r
953 idx+=6;\r
954 if (found && (hi|lo)) {\r
a9bc033b 955 Dbprintf("TAG ID: %x %x %x", \r
6f5cb60c 956 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r
9bea179a 957 /* if we're only looking for one tag */\r
958 if (findone)\r
959 {\r
960 *high = hi;\r
961 *low = lo;\r
962 return;\r
963 }\r
964 hi=0;\r
965 lo=0;\r
966 found=0;\r
967 }\r
968 }\r
969 }\r
970 WDT_HIT();\r
971 }\r
972}\r
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