]> git.zerfleddert.de Git - proxmark3-svn/blame - armsrc/hfsnoop.c
usb communication (device side) housekeeping
[proxmark3-svn] / armsrc / hfsnoop.c
CommitLineData
fc52fbd4 1//-----------------------------------------------------------------------------
2// piwi, 2019
3//
4// This code is licensed to you under the terms of the GNU GPL, version 2 or,
5// at your option, any later version. See the LICENSE.txt file for the text of
6// the license.
7//-----------------------------------------------------------------------------
8// Routines to get sample data from FPGA.
9//-----------------------------------------------------------------------------
10
11#include "hfsnoop.h"
12
0472d76d 13#include "proxmark3.h"
0472d76d 14#include "BigBuf.h"
15#include "util.h"
fc52fbd4 16#include "apps.h"
72622d64 17#include "cmd.h"
61000404 18#include "usb_cdc.h" // for usb_poll_validate_length
fc52fbd4 19#include "fpga.h"
20#include "fpgaloader.h"
0472d76d 21
22static void RAMFUNC optimizedSnoop(void)
23{
0472d76d 24 int n = BigBuf_max_traceLen() / sizeof(uint16_t); // take all memory
031311c7 25
0472d76d 26 uint16_t *dest = (uint16_t *)BigBuf_get_addr();
27 uint16_t *destend = dest + n;
28
29 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16); // Setting Frame mode, 16 bits per word
30 // Reading data loop
31 while(dest <= destend)
32 {
33 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)
34 {
35 *dest = (uint16_t)(AT91C_BASE_SSC->SSC_RHR);
06ed826c 36 dest++;
0472d76d 37 }
38 }
39 //Resetting Frame mode (First set in fpgaloader.c)
031311c7 40 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
0472d76d 41}
42
43void HfSnoop(int samplesToSkip, int triggersToSkip)
44{
06ed826c
I
45 BigBuf_free(); BigBuf_Clear();
46
47 Dbprintf("Skipping first %d sample pairs, Skipping %d triggers.\n", samplesToSkip, triggersToSkip);
c87c4521 48 int trigger_cnt;
031311c7 49 LED_D_ON();
0472d76d 50 // Select correct configs
51 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
52 // Set up the synchronous serial port
6a5d4e17 53 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SNOOP);
0472d76d 54 // connect Demodulated Signal to ADC:
55 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
56 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SNOOP);
57 SpinDelay(100);
58
59 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16); // Setting Frame Mode For better performance on high speed data transfer.
031311c7 60
0472d76d 61 trigger_cnt = 0;
031311c7 62 uint16_t r = 0;
06ed826c 63 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
031311c7 64 WDT_HIT();
0472d76d 65 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
66 r = (uint16_t)AT91C_BASE_SSC->SSC_RHR;
5d0e1901 67 r = MAX(r & 0xff, r >> 8);
06ed826c
I
68 if (r >= 240) {
69 if (++trigger_cnt > triggersToSkip)
5d0e1901 70 break;
031311c7 71 }
0472d76d 72 }
73 }
5d0e1901 74
031311c7 75 if(!BUTTON_PRESS()) {
031311c7 76 int waitcount = samplesToSkip; // lets wait 40000 ticks of pck0
77 while(waitcount != 0) {
06ed826c 78 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY))
031311c7 79 waitcount--;
0472d76d 80 }
031311c7 81 optimizedSnoop();
5d0e1901 82 Dbprintf("Trigger kicked! Value: %d, Dumping Samples Hispeed now.", r);
031311c7 83 }
0472d76d 84
031311c7 85 DbpString("HF Snoop end");
0472d76d 86 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
87 LED_D_OFF();
88}
89
fc52fbd4 90void HfPlot(void)
91{
92 uint8_t *buf = ToSend;
93 uint8_t *this_buf = buf;
94
95 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
96 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_GET_TRACE);
97 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; // Disable DMA Transfer
98 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) this_buf; // start transfer to this memory address
99 AT91C_BASE_PDC_SSC->PDC_RCR = USB_CMD_DATA_SIZE; // transfer this many samples
100 buf[0] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; // clear receive register
101 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; // Start DMA transfer
102 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_GET_TRACE); // let FPGA transfer its internal Block-RAM
103
104 LED_B_ON();
105 for(size_t i = 0; i < FPGA_TRACE_SIZE; i += USB_CMD_DATA_SIZE) {
106 // prepare next DMA transfer:
107 uint8_t *next_buf = buf + ((i + USB_CMD_DATA_SIZE) % (2 * USB_CMD_DATA_SIZE));
108 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t)next_buf;
109 AT91C_BASE_PDC_SSC->PDC_RNCR = USB_CMD_DATA_SIZE;
110 size_t len = MIN(FPGA_TRACE_SIZE - i, USB_CMD_DATA_SIZE);
111 while (!(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_ENDRX))) ; // wait for DMA transfer to complete
112 cmd_send(CMD_DOWNLOADED_RAW_ADC_SAMPLES_125K, i, len, FPGA_TRACE_SIZE, this_buf, len);
113 this_buf = next_buf;
114 }
115 // Trigger a finish downloading signal with an ACK frame
116 cmd_send(CMD_ACK, 1, 0, FPGA_TRACE_SIZE, 0, 0);
117 LED_B_OFF();
118 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
119}
Impressum, Datenschutz