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15c4dc5a | 1 | //----------------------------------------------------------------------------- |
bd20f8f4 | 2 | // This code is licensed to you under the terms of the GNU GPL, version 2 or, |
3 | // at your option, any later version. See the LICENSE.txt file for the text of | |
4 | // the license. | |
5 | //----------------------------------------------------------------------------- | |
15c4dc5a | 6 | // Miscellaneous routines for low frequency tag operations. |
7 | // Tags supported here so far are Texas Instruments (TI), HID | |
8 | // Also routines for raw mode reading/simulating of LF waveform | |
15c4dc5a | 9 | //----------------------------------------------------------------------------- |
bd20f8f4 | 10 | |
e30c654b | 11 | #include "proxmark3.h" |
15c4dc5a | 12 | #include "apps.h" |
f7e3ed82 | 13 | #include "util.h" |
15c4dc5a | 14 | #include "hitag2.h" |
15 | #include "crc16.h" | |
9ab7a6c7 | 16 | #include "string.h" |
7db5f1ca | 17 | #include "lfdemod.h" |
15c4dc5a | 18 | |
b2256785 MHS |
19 | |
20 | /** | |
21 | * Does the sample acquisition. If threshold is specified, the actual sampling | |
22 | * is not commenced until the threshold has been reached. | |
23 | * @param trigger_threshold - the threshold | |
24 | * @param silent - is true, now outputs are made. If false, dbprints the status | |
25 | */ | |
f97d4e23 | 26 | void DoAcquisition125k_internal(int trigger_threshold,bool silent) |
69d88ec4 MHS |
27 | { |
28 | uint8_t *dest = (uint8_t *)BigBuf; | |
29 | int n = sizeof(BigBuf); | |
30 | int i; | |
31 | ||
32 | memset(dest, 0, n); | |
33 | i = 0; | |
34 | for(;;) { | |
35 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { | |
36 | AT91C_BASE_SSC->SSC_THR = 0x43; | |
37 | LED_D_ON(); | |
38 | } | |
39 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { | |
40 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; | |
69d88ec4 | 41 | LED_D_OFF(); |
f97d4e23 MHS |
42 | if (trigger_threshold != -1 && dest[i] < trigger_threshold) |
43 | continue; | |
44 | else | |
45 | trigger_threshold = -1; | |
46 | if (++i >= n) break; | |
69d88ec4 MHS |
47 | } |
48 | } | |
f97d4e23 | 49 | if(!silent) |
69d88ec4 MHS |
50 | { |
51 | Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...", | |
52 | dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]); | |
f97d4e23 | 53 | |
69d88ec4 MHS |
54 | } |
55 | } | |
b2256785 MHS |
56 | /** |
57 | * Perform sample aquisition. | |
58 | */ | |
f97d4e23 | 59 | void DoAcquisition125k(int trigger_threshold) |
69d88ec4 | 60 | { |
f97d4e23 | 61 | DoAcquisition125k_internal(trigger_threshold, false); |
69d88ec4 MHS |
62 | } |
63 | ||
b2256785 MHS |
64 | /** |
65 | * Setup the FPGA to listen for samples. This method downloads the FPGA bitstream | |
66 | * if not already loaded, sets divisor and starts up the antenna. | |
67 | * @param divisor : 1, 88> 255 or negative ==> 134.8 KHz | |
68 | * 0 or 95 ==> 125 KHz | |
69 | * | |
70 | **/ | |
b014c96d | 71 | void LFSetupFPGAForADC(int divisor, bool lf_field) |
15c4dc5a | 72 | { |
7cc204bf | 73 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
bf7163bd | 74 | if ( (divisor == 1) || (divisor < 0) || (divisor > 255) ) |
15c4dc5a | 75 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz |
bf7163bd | 76 | else if (divisor == 0) |
15c4dc5a | 77 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
bf7163bd | 78 | else |
79 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor); | |
15c4dc5a | 80 | |
b014c96d | 81 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0)); |
15c4dc5a | 82 | |
83 | // Connect the A/D to the peak-detected low-frequency path. | |
84 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); | |
15c4dc5a | 85 | // Give it a bit of time for the resonant antenna to settle. |
86 | SpinDelay(50); | |
15c4dc5a | 87 | // Now set up the SSC to get the ADC samples that are now streaming at us. |
88 | FpgaSetupSsc(); | |
15c4dc5a | 89 | } |
b2256785 MHS |
90 | /** |
91 | * Initializes the FPGA, and acquires the samples. | |
92 | **/ | |
69d88ec4 | 93 | void AcquireRawAdcSamples125k(int divisor) |
15c4dc5a | 94 | { |
b014c96d | 95 | LFSetupFPGAForADC(divisor, true); |
69d88ec4 | 96 | // Now call the acquisition routine |
f97d4e23 | 97 | DoAcquisition125k_internal(-1,false); |
b014c96d | 98 | } |
b2256785 MHS |
99 | /** |
100 | * Initializes the FPGA for snoop-mode, and acquires the samples. | |
101 | **/ | |
102 | ||
b014c96d | 103 | void SnoopLFRawAdcSamples(int divisor, int trigger_threshold) |
104 | { | |
105 | LFSetupFPGAForADC(divisor, false); | |
1a5a0d75 | 106 | DoAcquisition125k(trigger_threshold); |
15c4dc5a | 107 | } |
108 | ||
f7e3ed82 | 109 | void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command) |
15c4dc5a | 110 | { |
15c4dc5a | 111 | |
112 | /* Make sure the tag is reset */ | |
7cc204bf | 113 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
15c4dc5a | 114 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
115 | SpinDelay(2500); | |
e30c654b | 116 | |
b2256785 MHS |
117 | |
118 | int divisor_used = 95; // 125 KHz | |
15c4dc5a | 119 | // see if 'h' was specified |
b2256785 | 120 | |
15c4dc5a | 121 | if (command[strlen((char *) command) - 1] == 'h') |
b2256785 | 122 | divisor_used = 88; // 134.8 KHz |
15c4dc5a | 123 | |
15c4dc5a | 124 | |
b2256785 | 125 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); |
b014c96d | 126 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
15c4dc5a | 127 | // Give it a bit of time for the resonant antenna to settle. |
128 | SpinDelay(50); | |
b2256785 | 129 | |
15c4dc5a | 130 | // And a little more time for the tag to fully power up |
131 | SpinDelay(2000); | |
132 | ||
133 | // Now set up the SSC to get the ADC samples that are now streaming at us. | |
134 | FpgaSetupSsc(); | |
135 | ||
136 | // now modulate the reader field | |
137 | while(*command != '\0' && *command != ' ') { | |
138 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
139 | LED_D_OFF(); | |
140 | SpinDelayUs(delay_off); | |
b2256785 | 141 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); |
15c4dc5a | 142 | |
b014c96d | 143 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
15c4dc5a | 144 | LED_D_ON(); |
145 | if(*(command++) == '0') | |
146 | SpinDelayUs(period_0); | |
147 | else | |
148 | SpinDelayUs(period_1); | |
149 | } | |
150 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
151 | LED_D_OFF(); | |
152 | SpinDelayUs(delay_off); | |
b2256785 | 153 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); |
15c4dc5a | 154 | |
b014c96d | 155 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
15c4dc5a | 156 | |
157 | // now do the read | |
b014c96d | 158 | DoAcquisition125k(-1); |
15c4dc5a | 159 | } |
160 | ||
161 | /* blank r/w tag data stream | |
162 | ...0000000000000000 01111111 | |
163 | 1010101010101010101010101010101010101010101010101010101010101010 | |
164 | 0011010010100001 | |
165 | 01111111 | |
166 | 101010101010101[0]000... | |
167 | ||
168 | [5555fe852c5555555555555555fe0000] | |
169 | */ | |
170 | void ReadTItag(void) | |
171 | { | |
172 | // some hardcoded initial params | |
173 | // when we read a TI tag we sample the zerocross line at 2Mhz | |
174 | // TI tags modulate a 1 as 16 cycles of 123.2Khz | |
175 | // TI tags modulate a 0 as 16 cycles of 134.2Khz | |
176 | #define FSAMPLE 2000000 | |
177 | #define FREQLO 123200 | |
178 | #define FREQHI 134200 | |
179 | ||
180 | signed char *dest = (signed char *)BigBuf; | |
181 | int n = sizeof(BigBuf); | |
182 | // int *dest = GraphBuffer; | |
183 | // int n = GraphTraceLen; | |
184 | ||
185 | // 128 bit shift register [shift3:shift2:shift1:shift0] | |
f7e3ed82 | 186 | uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0; |
15c4dc5a | 187 | |
188 | int i, cycles=0, samples=0; | |
189 | // how many sample points fit in 16 cycles of each frequency | |
f7e3ed82 | 190 | uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI; |
15c4dc5a | 191 | // when to tell if we're close enough to one freq or another |
f7e3ed82 | 192 | uint32_t threshold = (sampleslo - sampleshi + 1)>>1; |
15c4dc5a | 193 | |
194 | // TI tags charge at 134.2Khz | |
7cc204bf | 195 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
15c4dc5a | 196 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz |
197 | ||
198 | // Place FPGA in passthrough mode, in this mode the CROSS_LO line | |
199 | // connects to SSP_DIN and the SSP_DOUT logic level controls | |
200 | // whether we're modulating the antenna (high) | |
201 | // or listening to the antenna (low) | |
202 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); | |
203 | ||
204 | // get TI tag data into the buffer | |
205 | AcquireTiType(); | |
206 | ||
207 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
208 | ||
209 | for (i=0; i<n-1; i++) { | |
210 | // count cycles by looking for lo to hi zero crossings | |
211 | if ( (dest[i]<0) && (dest[i+1]>0) ) { | |
212 | cycles++; | |
213 | // after 16 cycles, measure the frequency | |
214 | if (cycles>15) { | |
215 | cycles=0; | |
216 | samples=i-samples; // number of samples in these 16 cycles | |
217 | ||
218 | // TI bits are coming to us lsb first so shift them | |
219 | // right through our 128 bit right shift register | |
220 | shift0 = (shift0>>1) | (shift1 << 31); | |
221 | shift1 = (shift1>>1) | (shift2 << 31); | |
222 | shift2 = (shift2>>1) | (shift3 << 31); | |
223 | shift3 >>= 1; | |
224 | ||
225 | // check if the cycles fall close to the number | |
226 | // expected for either the low or high frequency | |
227 | if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) { | |
228 | // low frequency represents a 1 | |
229 | shift3 |= (1<<31); | |
230 | } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) { | |
231 | // high frequency represents a 0 | |
232 | } else { | |
233 | // probably detected a gay waveform or noise | |
234 | // use this as gaydar or discard shift register and start again | |
235 | shift3 = shift2 = shift1 = shift0 = 0; | |
236 | } | |
237 | samples = i; | |
238 | ||
239 | // for each bit we receive, test if we've detected a valid tag | |
240 | ||
241 | // if we see 17 zeroes followed by 6 ones, we might have a tag | |
242 | // remember the bits are backwards | |
243 | if ( ((shift0 & 0x7fffff) == 0x7e0000) ) { | |
244 | // if start and end bytes match, we have a tag so break out of the loop | |
245 | if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) { | |
246 | cycles = 0xF0B; //use this as a flag (ugly but whatever) | |
247 | break; | |
248 | } | |
249 | } | |
250 | } | |
251 | } | |
252 | } | |
253 | ||
254 | // if flag is set we have a tag | |
255 | if (cycles!=0xF0B) { | |
256 | DbpString("Info: No valid tag detected."); | |
257 | } else { | |
258 | // put 64 bit data into shift1 and shift0 | |
259 | shift0 = (shift0>>24) | (shift1 << 8); | |
260 | shift1 = (shift1>>24) | (shift2 << 8); | |
261 | ||
262 | // align 16 bit crc into lower half of shift2 | |
263 | shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff; | |
264 | ||
265 | // if r/w tag, check ident match | |
266 | if ( shift3&(1<<15) ) { | |
267 | DbpString("Info: TI tag is rewriteable"); | |
268 | // only 15 bits compare, last bit of ident is not valid | |
269 | if ( ((shift3>>16)^shift0)&0x7fff ) { | |
270 | DbpString("Error: Ident mismatch!"); | |
271 | } else { | |
272 | DbpString("Info: TI tag ident is valid"); | |
273 | } | |
274 | } else { | |
275 | DbpString("Info: TI tag is readonly"); | |
276 | } | |
277 | ||
278 | // WARNING the order of the bytes in which we calc crc below needs checking | |
279 | // i'm 99% sure the crc algorithm is correct, but it may need to eat the | |
280 | // bytes in reverse or something | |
281 | // calculate CRC | |
f7e3ed82 | 282 | uint32_t crc=0; |
15c4dc5a | 283 | |
284 | crc = update_crc16(crc, (shift0)&0xff); | |
285 | crc = update_crc16(crc, (shift0>>8)&0xff); | |
286 | crc = update_crc16(crc, (shift0>>16)&0xff); | |
287 | crc = update_crc16(crc, (shift0>>24)&0xff); | |
288 | crc = update_crc16(crc, (shift1)&0xff); | |
289 | crc = update_crc16(crc, (shift1>>8)&0xff); | |
290 | crc = update_crc16(crc, (shift1>>16)&0xff); | |
291 | crc = update_crc16(crc, (shift1>>24)&0xff); | |
292 | ||
293 | Dbprintf("Info: Tag data: %x%08x, crc=%x", | |
294 | (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF); | |
295 | if (crc != (shift2&0xffff)) { | |
296 | Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc); | |
297 | } else { | |
298 | DbpString("Info: CRC is good"); | |
299 | } | |
300 | } | |
301 | } | |
302 | ||
f7e3ed82 | 303 | void WriteTIbyte(uint8_t b) |
15c4dc5a | 304 | { |
305 | int i = 0; | |
306 | ||
307 | // modulate 8 bits out to the antenna | |
308 | for (i=0; i<8; i++) | |
309 | { | |
310 | if (b&(1<<i)) { | |
311 | // stop modulating antenna | |
312 | LOW(GPIO_SSC_DOUT); | |
313 | SpinDelayUs(1000); | |
314 | // modulate antenna | |
315 | HIGH(GPIO_SSC_DOUT); | |
316 | SpinDelayUs(1000); | |
317 | } else { | |
318 | // stop modulating antenna | |
319 | LOW(GPIO_SSC_DOUT); | |
320 | SpinDelayUs(300); | |
321 | // modulate antenna | |
322 | HIGH(GPIO_SSC_DOUT); | |
323 | SpinDelayUs(1700); | |
324 | } | |
325 | } | |
326 | } | |
327 | ||
328 | void AcquireTiType(void) | |
329 | { | |
330 | int i, j, n; | |
331 | // tag transmission is <20ms, sampling at 2M gives us 40K samples max | |
f7e3ed82 | 332 | // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t |
15c4dc5a | 333 | #define TIBUFLEN 1250 |
334 | ||
335 | // clear buffer | |
336 | memset(BigBuf,0,sizeof(BigBuf)); | |
337 | ||
338 | // Set up the synchronous serial port | |
339 | AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN; | |
340 | AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN; | |
341 | ||
342 | // steal this pin from the SSP and use it to control the modulation | |
343 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; | |
344 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; | |
345 | ||
346 | AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST; | |
347 | AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN; | |
348 | ||
349 | // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long | |
350 | // 48/2 = 24 MHz clock must be divided by 12 | |
351 | AT91C_BASE_SSC->SSC_CMR = 12; | |
352 | ||
353 | AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0); | |
354 | AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF; | |
355 | AT91C_BASE_SSC->SSC_TCMR = 0; | |
356 | AT91C_BASE_SSC->SSC_TFMR = 0; | |
357 | ||
358 | LED_D_ON(); | |
359 | ||
360 | // modulate antenna | |
361 | HIGH(GPIO_SSC_DOUT); | |
362 | ||
363 | // Charge TI tag for 50ms. | |
364 | SpinDelay(50); | |
365 | ||
366 | // stop modulating antenna and listen | |
367 | LOW(GPIO_SSC_DOUT); | |
368 | ||
369 | LED_D_OFF(); | |
370 | ||
371 | i = 0; | |
372 | for(;;) { | |
373 | if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { | |
374 | BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer | |
375 | i++; if(i >= TIBUFLEN) break; | |
376 | } | |
377 | WDT_HIT(); | |
378 | } | |
379 | ||
380 | // return stolen pin to SSP | |
381 | AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT; | |
382 | AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT; | |
383 | ||
384 | char *dest = (char *)BigBuf; | |
385 | n = TIBUFLEN*32; | |
386 | // unpack buffer | |
387 | for (i=TIBUFLEN-1; i>=0; i--) { | |
388 | for (j=0; j<32; j++) { | |
389 | if(BigBuf[i] & (1 << j)) { | |
390 | dest[--n] = 1; | |
391 | } else { | |
392 | dest[--n] = -1; | |
393 | } | |
394 | } | |
395 | } | |
396 | } | |
397 | ||
398 | // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc | |
399 | // if crc provided, it will be written with the data verbatim (even if bogus) | |
400 | // if not provided a valid crc will be computed from the data and written. | |
f7e3ed82 | 401 | void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc) |
15c4dc5a | 402 | { |
7cc204bf | 403 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
15c4dc5a | 404 | if(crc == 0) { |
405 | crc = update_crc16(crc, (idlo)&0xff); | |
406 | crc = update_crc16(crc, (idlo>>8)&0xff); | |
407 | crc = update_crc16(crc, (idlo>>16)&0xff); | |
408 | crc = update_crc16(crc, (idlo>>24)&0xff); | |
409 | crc = update_crc16(crc, (idhi)&0xff); | |
410 | crc = update_crc16(crc, (idhi>>8)&0xff); | |
411 | crc = update_crc16(crc, (idhi>>16)&0xff); | |
412 | crc = update_crc16(crc, (idhi>>24)&0xff); | |
413 | } | |
414 | Dbprintf("Writing to tag: %x%08x, crc=%x", | |
415 | (unsigned int) idhi, (unsigned int) idlo, crc); | |
416 | ||
417 | // TI tags charge at 134.2Khz | |
418 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz | |
419 | // Place FPGA in passthrough mode, in this mode the CROSS_LO line | |
420 | // connects to SSP_DIN and the SSP_DOUT logic level controls | |
421 | // whether we're modulating the antenna (high) | |
422 | // or listening to the antenna (low) | |
423 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); | |
424 | LED_A_ON(); | |
425 | ||
426 | // steal this pin from the SSP and use it to control the modulation | |
427 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; | |
428 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; | |
429 | ||
430 | // writing algorithm: | |
431 | // a high bit consists of a field off for 1ms and field on for 1ms | |
432 | // a low bit consists of a field off for 0.3ms and field on for 1.7ms | |
433 | // initiate a charge time of 50ms (field on) then immediately start writing bits | |
434 | // start by writing 0xBB (keyword) and 0xEB (password) | |
435 | // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer) | |
436 | // finally end with 0x0300 (write frame) | |
437 | // all data is sent lsb firts | |
438 | // finish with 15ms programming time | |
439 | ||
440 | // modulate antenna | |
441 | HIGH(GPIO_SSC_DOUT); | |
442 | SpinDelay(50); // charge time | |
443 | ||
444 | WriteTIbyte(0xbb); // keyword | |
445 | WriteTIbyte(0xeb); // password | |
446 | WriteTIbyte( (idlo )&0xff ); | |
447 | WriteTIbyte( (idlo>>8 )&0xff ); | |
448 | WriteTIbyte( (idlo>>16)&0xff ); | |
449 | WriteTIbyte( (idlo>>24)&0xff ); | |
450 | WriteTIbyte( (idhi )&0xff ); | |
451 | WriteTIbyte( (idhi>>8 )&0xff ); | |
452 | WriteTIbyte( (idhi>>16)&0xff ); | |
453 | WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo | |
454 | WriteTIbyte( (crc )&0xff ); // crc lo | |
455 | WriteTIbyte( (crc>>8 )&0xff ); // crc hi | |
456 | WriteTIbyte(0x00); // write frame lo | |
457 | WriteTIbyte(0x03); // write frame hi | |
458 | HIGH(GPIO_SSC_DOUT); | |
459 | SpinDelay(50); // programming time | |
460 | ||
461 | LED_A_OFF(); | |
462 | ||
463 | // get TI tag data into the buffer | |
464 | AcquireTiType(); | |
465 | ||
466 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
467 | DbpString("Now use tiread to check"); | |
468 | } | |
469 | ||
470 | void SimulateTagLowFrequency(int period, int gap, int ledcontrol) | |
471 | { | |
472 | int i; | |
f7e3ed82 | 473 | uint8_t *tab = (uint8_t *)BigBuf; |
d19929cb | 474 | |
7cc204bf | 475 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
d19929cb | 476 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT); |
477 | ||
15c4dc5a | 478 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK; |
d19929cb | 479 | |
15c4dc5a | 480 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; |
481 | AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; | |
d19929cb | 482 | |
15c4dc5a | 483 | #define SHORT_COIL() LOW(GPIO_SSC_DOUT) |
484 | #define OPEN_COIL() HIGH(GPIO_SSC_DOUT) | |
d19929cb | 485 | |
15c4dc5a | 486 | i = 0; |
487 | for(;;) { | |
488 | while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) { | |
489 | if(BUTTON_PRESS()) { | |
490 | DbpString("Stopped"); | |
491 | return; | |
492 | } | |
493 | WDT_HIT(); | |
494 | } | |
d19929cb | 495 | |
15c4dc5a | 496 | if (ledcontrol) |
497 | LED_D_ON(); | |
d19929cb | 498 | |
15c4dc5a | 499 | if(tab[i]) |
500 | OPEN_COIL(); | |
501 | else | |
502 | SHORT_COIL(); | |
d19929cb | 503 | |
15c4dc5a | 504 | if (ledcontrol) |
505 | LED_D_OFF(); | |
d19929cb | 506 | |
15c4dc5a | 507 | while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) { |
508 | if(BUTTON_PRESS()) { | |
509 | DbpString("Stopped"); | |
510 | return; | |
511 | } | |
512 | WDT_HIT(); | |
513 | } | |
d19929cb | 514 | |
15c4dc5a | 515 | i++; |
516 | if(i == period) { | |
517 | i = 0; | |
e30c654b | 518 | if (gap) { |
15c4dc5a | 519 | SHORT_COIL(); |
520 | SpinDelayUs(gap); | |
521 | } | |
522 | } | |
523 | } | |
524 | } | |
525 | ||
15c4dc5a | 526 | #define DEBUG_FRAME_CONTENTS 1 |
527 | void SimulateTagLowFrequencyBidir(int divisor, int t0) | |
528 | { | |
15c4dc5a | 529 | } |
530 | ||
531 | // compose fc/8 fc/10 waveform | |
532 | static void fc(int c, int *n) { | |
f7e3ed82 | 533 | uint8_t *dest = (uint8_t *)BigBuf; |
15c4dc5a | 534 | int idx; |
535 | ||
536 | // for when we want an fc8 pattern every 4 logical bits | |
537 | if(c==0) { | |
538 | dest[((*n)++)]=1; | |
539 | dest[((*n)++)]=1; | |
540 | dest[((*n)++)]=0; | |
541 | dest[((*n)++)]=0; | |
542 | dest[((*n)++)]=0; | |
543 | dest[((*n)++)]=0; | |
544 | dest[((*n)++)]=0; | |
545 | dest[((*n)++)]=0; | |
546 | } | |
547 | // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples | |
548 | if(c==8) { | |
549 | for (idx=0; idx<6; idx++) { | |
550 | dest[((*n)++)]=1; | |
551 | dest[((*n)++)]=1; | |
552 | dest[((*n)++)]=0; | |
553 | dest[((*n)++)]=0; | |
554 | dest[((*n)++)]=0; | |
555 | dest[((*n)++)]=0; | |
556 | dest[((*n)++)]=0; | |
557 | dest[((*n)++)]=0; | |
558 | } | |
559 | } | |
560 | ||
561 | // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples | |
562 | if(c==10) { | |
563 | for (idx=0; idx<5; idx++) { | |
564 | dest[((*n)++)]=1; | |
565 | dest[((*n)++)]=1; | |
566 | dest[((*n)++)]=1; | |
567 | dest[((*n)++)]=0; | |
568 | dest[((*n)++)]=0; | |
569 | dest[((*n)++)]=0; | |
570 | dest[((*n)++)]=0; | |
571 | dest[((*n)++)]=0; | |
572 | dest[((*n)++)]=0; | |
573 | dest[((*n)++)]=0; | |
574 | } | |
575 | } | |
576 | } | |
577 | ||
578 | // prepare a waveform pattern in the buffer based on the ID given then | |
579 | // simulate a HID tag until the button is pressed | |
580 | void CmdHIDsimTAG(int hi, int lo, int ledcontrol) | |
581 | { | |
582 | int n=0, i=0; | |
583 | /* | |
584 | HID tag bitstream format | |
585 | The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits | |
586 | A 1 bit is represented as 6 fc8 and 5 fc10 patterns | |
587 | A 0 bit is represented as 5 fc10 and 6 fc8 patterns | |
588 | A fc8 is inserted before every 4 bits | |
589 | A special start of frame pattern is used consisting a0b0 where a and b are neither 0 | |
590 | nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10) | |
591 | */ | |
592 | ||
593 | if (hi>0xFFF) { | |
594 | DbpString("Tags can only have 44 bits."); | |
595 | return; | |
596 | } | |
597 | fc(0,&n); | |
598 | // special start of frame marker containing invalid bit sequences | |
599 | fc(8, &n); fc(8, &n); // invalid | |
600 | fc(8, &n); fc(10, &n); // logical 0 | |
601 | fc(10, &n); fc(10, &n); // invalid | |
602 | fc(8, &n); fc(10, &n); // logical 0 | |
603 | ||
604 | WDT_HIT(); | |
605 | // manchester encode bits 43 to 32 | |
606 | for (i=11; i>=0; i--) { | |
607 | if ((i%4)==3) fc(0,&n); | |
608 | if ((hi>>i)&1) { | |
609 | fc(10, &n); fc(8, &n); // low-high transition | |
610 | } else { | |
611 | fc(8, &n); fc(10, &n); // high-low transition | |
612 | } | |
613 | } | |
614 | ||
615 | WDT_HIT(); | |
616 | // manchester encode bits 31 to 0 | |
617 | for (i=31; i>=0; i--) { | |
618 | if ((i%4)==3) fc(0,&n); | |
619 | if ((lo>>i)&1) { | |
620 | fc(10, &n); fc(8, &n); // low-high transition | |
621 | } else { | |
622 | fc(8, &n); fc(10, &n); // high-low transition | |
623 | } | |
624 | } | |
625 | ||
626 | if (ledcontrol) | |
627 | LED_A_ON(); | |
628 | SimulateTagLowFrequency(n, 0, ledcontrol); | |
629 | ||
630 | if (ledcontrol) | |
631 | LED_A_OFF(); | |
632 | } | |
eb191de6 | 633 | /* |
b3b70669 | 634 | //translate wave to 11111100000 (1 for each short wave 0 for each long wave) |
07976a25 | 635 | size_t fsk_demod(uint8_t * dest, size_t size) |
69d88ec4 | 636 | { |
07976a25 MHS |
637 | uint32_t last_transition = 0; |
638 | uint32_t idx = 1; | |
b3b70669 | 639 | uint32_t maxVal=0; |
640 | // // we don't care about actual value, only if it's more or less than a | |
641 | // // threshold essentially we capture zero crossings for later analysis | |
642 | ||
643 | // we do care about the actual value as sometimes near the center of the | |
644 | // wave we may get static that changes direction of wave for one value | |
645 | // if our value is too low it might affect the read. and if our tag or | |
646 | // antenna is weak a setting too high might not see anything. [marshmellow] | |
647 | if (size<100) return size; | |
648 | for(idx=1; idx<100; idx++){ | |
649 | if(maxVal<dest[idx]) maxVal = dest[idx]; | |
650 | } | |
651 | // set close to the top of the wave threshold with 13% margin for error | |
652 | // less likely to get a false transition up there. | |
653 | // (but have to be careful not to go too high and miss some short waves) | |
654 | uint32_t threshold_value = (uint32_t)(maxVal*.87); idx=1; | |
655 | //uint8_t threshold_value = 127; | |
083ca3de | 656 | |
69d88ec4 MHS |
657 | // sync to first lo-hi transition, and threshold |
658 | ||
b3b70669 | 659 | // Need to threshold first sample |
69d88ec4 MHS |
660 | if(dest[0] < threshold_value) dest[0] = 0; |
661 | else dest[0] = 1; | |
662 | ||
07976a25 | 663 | size_t numBits = 0; |
69d88ec4 MHS |
664 | // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8) |
665 | // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere | |
666 | // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10 | |
667 | for(idx = 1; idx < size; idx++) { | |
69d88ec4 MHS |
668 | // threshold current value |
669 | if (dest[idx] < threshold_value) dest[idx] = 0; | |
670 | else dest[idx] = 1; | |
671 | ||
672 | // Check for 0->1 transition | |
673 | if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition | |
b3b70669 | 674 | if (idx-last_transition<6){ |
675 | //do nothing with extra garbage | |
676 | } else if (idx-last_transition < 9) { | |
677 | dest[numBits]=1; | |
69d88ec4 | 678 | } else { |
b3b70669 | 679 | dest[numBits]=0; |
69d88ec4 MHS |
680 | } |
681 | last_transition = idx; | |
682 | numBits++; | |
683 | } | |
684 | } | |
685 | return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0 | |
686 | } | |
687 | ||
b3b70669 | 688 | uint32_t myround(float f) |
689 | { | |
690 | if (f >= 2000) return 2000;//something bad happened | |
691 | return (uint32_t) (f + (float)0.5); | |
692 | } | |
07976a25 | 693 | |
b3b70669 | 694 | //translate 11111100000 to 10 |
695 | size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t rfLen, uint8_t maxConsequtiveBits, uint8_t invert )// uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, | |
69d88ec4 MHS |
696 | { |
697 | uint8_t lastval=dest[0]; | |
07976a25 MHS |
698 | uint32_t idx=0; |
699 | size_t numBits=0; | |
700 | uint32_t n=1; | |
69d88ec4 MHS |
701 | |
702 | for( idx=1; idx < size; idx++) { | |
703 | ||
704 | if (dest[idx]==lastval) { | |
705 | n++; | |
706 | continue; | |
707 | } | |
708 | //if lastval was 1, we have a 1->0 crossing | |
083ca3de | 709 | if ( dest[idx-1]==1 ) { |
b3b70669 | 710 | n=myround((float)(n+1)/((float)(rfLen)/(float)8)); |
711 | //n=(n+1) / h2l_crossing_value; | |
69d88ec4 | 712 | } else {// 0->1 crossing |
b3b70669 | 713 | n=myround((float)(n+1)/((float)(rfLen-2)/(float)10)); |
714 | //n=(n+1) / l2h_crossing_value; | |
69d88ec4 | 715 | } |
07976a25 MHS |
716 | if (n == 0) n = 1; |
717 | ||
083ca3de | 718 | if(n < maxConsequtiveBits) //Consecutive |
69d88ec4 | 719 | { |
083ca3de | 720 | if(invert==0){ //invert bits |
721 | memset(dest+numBits, dest[idx-1] , n); | |
722 | }else{ | |
723 | memset(dest+numBits, dest[idx-1]^1 , n); | |
b3b70669 | 724 | } |
69d88ec4 MHS |
725 | numBits += n; |
726 | } | |
727 | n=0; | |
728 | lastval=dest[idx]; | |
729 | }//end for | |
69d88ec4 | 730 | return numBits; |
69d88ec4 | 731 | } |
eb191de6 | 732 | */ |
733 | ||
b3b70669 | 734 | // loop to get raw HID waveform then FSK demodulate the TAG ID from it |
69d88ec4 MHS |
735 | void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol) |
736 | { | |
737 | uint8_t *dest = (uint8_t *)BigBuf; | |
738 | ||
eb191de6 | 739 | size_t size=0; //, found=0; |
740 | uint32_t hi2=0, hi=0, lo=0; | |
741 | ||
742 | // Configure to go in 125Khz listen mode | |
743 | LFSetupFPGAForADC(95, true); | |
744 | ||
745 | while(!BUTTON_PRESS()) { | |
746 | ||
747 | WDT_HIT(); | |
748 | if (ledcontrol) LED_A_ON(); | |
749 | ||
750 | DoAcquisition125k_internal(-1,true); | |
751 | size = sizeof(BigBuf); | |
752 | if (size < 2000) continue; | |
753 | // FSK demodulator | |
754 | ||
755 | int bitLen = HIDdemodFSK(dest,size,&hi2,&hi,&lo); | |
756 | ||
757 | WDT_HIT(); | |
758 | ||
759 | if (bitLen>0 && lo>0){ | |
760 | // final loop, go over previously decoded manchester data and decode into usable tag ID | |
761 | // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0 | |
762 | if (hi2 != 0){ //extra large HID tags | |
763 | Dbprintf("TAG ID: %x%08x%08x (%d)", | |
764 | (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); | |
765 | }else { //standard HID tags <38 bits | |
766 | //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd | |
767 | uint8_t bitlen = 0; | |
768 | uint32_t fc = 0; | |
769 | uint32_t cardnum = 0; | |
770 | if (((hi>>5)&1)==1){//if bit 38 is set then < 37 bit format is used | |
771 | uint32_t lo2=0; | |
772 | lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit | |
773 | uint8_t idx3 = 1; | |
774 | while(lo2>1){ //find last bit set to 1 (format len bit) | |
775 | lo2=lo2>>1; | |
776 | idx3++; | |
777 | } | |
778 | bitlen =idx3+19; | |
779 | fc =0; | |
780 | cardnum=0; | |
781 | if(bitlen==26){ | |
782 | cardnum = (lo>>1)&0xFFFF; | |
783 | fc = (lo>>17)&0xFF; | |
784 | } | |
785 | if(bitlen==37){ | |
786 | cardnum = (lo>>1)&0x7FFFF; | |
787 | fc = ((hi&0xF)<<12)|(lo>>20); | |
788 | } | |
789 | if(bitlen==34){ | |
790 | cardnum = (lo>>1)&0xFFFF; | |
791 | fc= ((hi&1)<<15)|(lo>>17); | |
792 | } | |
793 | if(bitlen==35){ | |
794 | cardnum = (lo>>1)&0xFFFFF; | |
795 | fc = ((hi&1)<<11)|(lo>>21); | |
796 | } | |
797 | } | |
798 | else { //if bit 38 is not set then 37 bit format is used | |
799 | bitlen= 37; | |
800 | fc =0; | |
801 | cardnum=0; | |
802 | if(bitlen==37){ | |
803 | cardnum = (lo>>1)&0x7FFFF; | |
804 | fc = ((hi&0xF)<<12)|(lo>>20); | |
805 | } | |
806 | } | |
807 | //Dbprintf("TAG ID: %x%08x (%d)", | |
808 | // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); | |
809 | Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d", | |
810 | (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF, | |
811 | (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum); | |
812 | } | |
813 | if (findone){ | |
814 | if (ledcontrol) LED_A_OFF(); | |
815 | return; | |
816 | } | |
817 | // reset | |
818 | hi2 = hi = lo = 0; | |
819 | } | |
820 | WDT_HIT(); | |
821 | } | |
822 | DbpString("Stopped"); | |
823 | if (ledcontrol) LED_A_OFF(); | |
824 | } | |
825 | ||
826 | /* | |
827 | // loop to get raw HID waveform then FSK demodulate the TAG ID from it | |
828 | void CmdHIDdemodFSK2(int findone, int *high, int *low, int ledcontrol) | |
829 | { | |
830 | uint8_t *dest = (uint8_t *)BigBuf; | |
831 | ||
07976a25 | 832 | size_t size=0,idx=0; //, found=0; |
69d88ec4 MHS |
833 | uint32_t hi2=0, hi=0, lo=0; |
834 | ||
9cc8a1e5 MHS |
835 | // Configure to go in 125Khz listen mode |
836 | LFSetupFPGAForADC(95, true); | |
69d88ec4 | 837 | |
07976a25 | 838 | while(!BUTTON_PRESS()) { |
15c4dc5a | 839 | |
07976a25 MHS |
840 | WDT_HIT(); |
841 | if (ledcontrol) LED_A_ON(); | |
69d88ec4 | 842 | |
1a5a0d75 | 843 | DoAcquisition125k_internal(-1,true); |
69d88ec4 | 844 | size = sizeof(BigBuf); |
b3b70669 | 845 | if (size < 2000) continue; |
15c4dc5a | 846 | // FSK demodulator |
69d88ec4 | 847 | size = fsk_demod(dest, size); |
15c4dc5a | 848 | |
69d88ec4 | 849 | // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns |
083ca3de | 850 | // 1->0 : fc/8 in sets of 6 (RF/50 / 8 = 6.25) |
851 | // 0->1 : fc/10 in sets of 5 (RF/50 / 10= 5) | |
852 | // do not invert | |
b3b70669 | 853 | size = aggregate_bits(dest,size, 50,5,0); //6,5,5,0 |
15c4dc5a | 854 | |
15c4dc5a | 855 | WDT_HIT(); |
856 | ||
857 | // final loop, go over previously decoded manchester data and decode into usable tag ID | |
858 | // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0 | |
69d88ec4 | 859 | uint8_t frame_marker_mask[] = {1,1,1,0,0,0}; |
07976a25 MHS |
860 | int numshifts = 0; |
861 | idx = 0; | |
b3b70669 | 862 | //one scan |
863 | uint8_t sameCardCount =0; | |
07976a25 MHS |
864 | while( idx + sizeof(frame_marker_mask) < size) { |
865 | // search for a start of frame marker | |
b3b70669 | 866 | if (sameCardCount>2) break; //only up to 2 valid sets of data for the same read of looping card data |
07976a25 MHS |
867 | if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0) |
868 | { // frame marker found | |
869 | idx+=sizeof(frame_marker_mask); | |
07976a25 | 870 | while(dest[idx] != dest[idx+1] && idx < size-2) |
9cc8a1e5 MHS |
871 | { |
872 | // Keep going until next frame marker (or error) | |
07976a25 | 873 | // Shift in a bit. Start by shifting high registers |
69d88ec4 MHS |
874 | hi2 = (hi2<<1)|(hi>>31); |
875 | hi = (hi<<1)|(lo>>31); | |
876 | //Then, shift in a 0 or one into low | |
877 | if (dest[idx] && !dest[idx+1]) // 1 0 | |
878 | lo=(lo<<1)|0; | |
879 | else // 0 1 | |
07976a25 MHS |
880 | lo=(lo<<1)| |
881 | 1; | |
48601727 | 882 | numshifts++; |
07976a25 | 883 | idx += 2; |
15c4dc5a | 884 | } |
07976a25 MHS |
885 | //Dbprintf("Num shifts: %d ", numshifts); |
886 | // Hopefully, we read a tag and hit upon the next frame marker | |
9cc8a1e5 | 887 | if(idx + sizeof(frame_marker_mask) < size) |
07976a25 | 888 | { |
9cc8a1e5 MHS |
889 | if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0) |
890 | { | |
083ca3de | 891 | if (hi2 != 0){ //extra large HID tags |
9cc8a1e5 MHS |
892 | Dbprintf("TAG ID: %x%08x%08x (%d)", |
893 | (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); | |
894 | } | |
083ca3de | 895 | else { //standard HID tags <38 bits |
896 | //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd | |
48601727 | 897 | uint8_t bitlen = 0; |
898 | uint32_t fc = 0; | |
899 | uint32_t cardnum = 0; | |
48601727 | 900 | if (((hi>>5)&1)==1){//if bit 38 is set then < 37 bit format is used |
901 | uint32_t lo2=0; | |
902 | lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit | |
903 | uint8_t idx3 = 1; | |
904 | while(lo2>1){ //find last bit set to 1 (format len bit) | |
905 | lo2=lo2>>1; | |
906 | idx3++; | |
907 | } | |
083ca3de | 908 | bitlen =idx3+19; |
48601727 | 909 | fc =0; |
910 | cardnum=0; | |
911 | if(bitlen==26){ | |
912 | cardnum = (lo>>1)&0xFFFF; | |
913 | fc = (lo>>17)&0xFF; | |
914 | } | |
915 | if(bitlen==37){ | |
916 | cardnum = (lo>>1)&0x7FFFF; | |
917 | fc = ((hi&0xF)<<12)|(lo>>20); | |
918 | } | |
919 | if(bitlen==34){ | |
920 | cardnum = (lo>>1)&0xFFFF; | |
921 | fc= ((hi&1)<<15)|(lo>>17); | |
922 | } | |
923 | if(bitlen==35){ | |
924 | cardnum = (lo>>1)&0xFFFFF; | |
925 | fc = ((hi&1)<<11)|(lo>>21); | |
926 | } | |
48601727 | 927 | } |
928 | else { //if bit 38 is not set then 37 bit format is used | |
929 | bitlen= 37; | |
930 | fc =0; | |
931 | cardnum=0; | |
932 | if(bitlen==37){ | |
933 | cardnum = (lo>>1)&0x7FFFF; | |
934 | fc = ((hi&0xF)<<12)|(lo>>20); | |
935 | } | |
936 | } | |
937 | //Dbprintf("TAG ID: %x%08x (%d)", | |
083ca3de | 938 | // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); |
48601727 | 939 | Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d", |
940 | (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF, | |
941 | (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum); | |
9cc8a1e5 | 942 | } |
b3b70669 | 943 | sameCardCount++; |
083ca3de | 944 | if (findone){ |
945 | if (ledcontrol) LED_A_OFF(); | |
946 | return; | |
947 | } | |
69d88ec4 | 948 | } |
15c4dc5a | 949 | } |
07976a25 MHS |
950 | // reset |
951 | hi2 = hi = lo = 0; | |
952 | numshifts = 0; | |
953 | }else | |
954 | { | |
955 | idx++; | |
15c4dc5a | 956 | } |
957 | } | |
958 | WDT_HIT(); | |
07976a25 | 959 | |
15c4dc5a | 960 | } |
07976a25 MHS |
961 | DbpString("Stopped"); |
962 | if (ledcontrol) LED_A_OFF(); | |
15c4dc5a | 963 | } |
eb191de6 | 964 | */ |
ec09b62d | 965 | |
eb191de6 | 966 | /* |
69d88ec4 MHS |
967 | uint32_t bytebits_to_byte(uint8_t* src, int numbits) |
968 | { | |
969 | uint32_t num = 0; | |
970 | for(int i = 0 ; i < numbits ; i++) | |
971 | { | |
972 | num = (num << 1) | (*src); | |
973 | src++; | |
974 | } | |
975 | return num; | |
976 | } | |
eb191de6 | 977 | */ |
69d88ec4 | 978 | |
a1f3bb12 | 979 | void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol) |
eb191de6 | 980 | { |
981 | uint8_t *dest = (uint8_t *)BigBuf; | |
982 | size_t size=0; | |
983 | int idx=0; | |
984 | uint32_t code=0, code2=0; | |
985 | ||
986 | // Configure to go in 125Khz listen mode | |
987 | LFSetupFPGAForADC(95, true); | |
988 | ||
989 | while(!BUTTON_PRESS()) { | |
990 | WDT_HIT(); | |
991 | if (ledcontrol) LED_A_ON(); | |
992 | DoAcquisition125k_internal(-1,true); | |
993 | size = sizeof(BigBuf); | |
994 | //make sure buffer has data | |
995 | if (size < 2000) continue; | |
996 | //fskdemod and get start index | |
997 | idx = IOdemodFSK(dest,size); | |
998 | if (idx>0){ | |
999 | //valid tag found | |
1000 | ||
1001 | //Index map | |
1002 | //0 10 20 30 40 50 60 | |
1003 | //| | | | | | | | |
1004 | //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23 | |
1005 | //----------------------------------------------------------------------------- | |
1006 | //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11 | |
1007 | // | |
1008 | //XSF(version)facility:codeone+codetwo | |
1009 | //Handle the data | |
1010 | if(findone){ //only print binary if we are doing one | |
1011 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]); | |
1012 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]); | |
1013 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]); | |
1014 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]); | |
1015 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]); | |
1016 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]); | |
1017 | Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]); | |
1018 | } | |
1019 | code = bytebits_to_byte(dest+idx,32); | |
1020 | code2 = bytebits_to_byte(dest+idx+32,32); | |
1021 | short version = bytebits_to_byte(dest+idx+27,8); //14,4 | |
1022 | uint8_t facilitycode = bytebits_to_byte(dest+idx+19,8) ; | |
1023 | uint16_t number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9 | |
1024 | ||
1025 | Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,facilitycode,number,code,code2); | |
1026 | // if we're only looking for one tag | |
1027 | if (findone){ | |
1028 | if (ledcontrol) LED_A_OFF(); | |
1029 | //LED_A_OFF(); | |
1030 | return; | |
1031 | } | |
1032 | } | |
1033 | WDT_HIT(); | |
1034 | } | |
1035 | DbpString("Stopped"); | |
1036 | if (ledcontrol) LED_A_OFF(); | |
1037 | } | |
1038 | /* | |
1039 | void CmdIOdemodFSK2(int findone, int *high, int *low, int ledcontrol) | |
a1f3bb12 | 1040 | { |
1041 | uint8_t *dest = (uint8_t *)BigBuf; | |
07976a25 | 1042 | size_t size=0, idx=0; |
a1f3bb12 | 1043 | uint32_t code=0, code2=0; |
a1f3bb12 | 1044 | |
9cc8a1e5 MHS |
1045 | // Configure to go in 125Khz listen mode |
1046 | LFSetupFPGAForADC(95, true); | |
083ca3de | 1047 | |
07976a25 | 1048 | while(!BUTTON_PRESS()) { |
a1f3bb12 | 1049 | WDT_HIT(); |
07976a25 | 1050 | if (ledcontrol) LED_A_ON(); |
1a5a0d75 | 1051 | DoAcquisition125k_internal(-1,true); |
69d88ec4 | 1052 | size = sizeof(BigBuf); |
b3b70669 | 1053 | //make sure buffer has data |
1054 | if (size < 64) return; | |
1055 | //test samples are not just noise | |
1056 | uint8_t testMax=0; | |
1057 | for(idx=0;idx<64;idx++){ | |
1058 | if (testMax<dest[idx]) testMax=dest[idx]; | |
69d88ec4 | 1059 | } |
b3b70669 | 1060 | idx=0; |
1061 | //if not just noise | |
1062 | if (testMax>170){ | |
1063 | //Dbprintf("testMax: %d",testMax); | |
1064 | // FSK demodulator | |
1065 | size = fsk_demod(dest, size); | |
1066 | // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns | |
1067 | // 1->0 : fc/8 in sets of 7 (RF/64 / 8 = 8) | |
1068 | // 0->1 : fc/10 in sets of 6 (RF/64 / 10 = 6.4) | |
1069 | size = aggregate_bits(dest, size, 64, 13, 1); //13 max Consecutive should be ok as most 0s in row should be 10 for init seq - invert bits | |
1070 | WDT_HIT(); | |
1071 | //Index map | |
1072 | //0 10 20 30 40 50 60 | |
1073 | //| | | | | | | | |
1074 | //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23 | |
1075 | //----------------------------------------------------------------------------- | |
1076 | //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11 | |
1077 | // | |
1078 | //XSF(version)facility:codeone+codetwo | |
1079 | //Handle the data | |
1080 | uint8_t sameCardCount=0; | |
1081 | uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1}; | |
1082 | for( idx=0; idx < (size - 74); idx++) { | |
1083 | if (sameCardCount>2) break; | |
1084 | if ( memcmp(dest + idx, mask, sizeof(mask))==0) { | |
1085 | //frame marker found | |
1086 | if (!dest[idx+8] && dest[idx+17]==1 && dest[idx+26]==1 && dest[idx+35]==1 && dest[idx+44]==1 && dest[idx+53]==1){ | |
1087 | //confirmed proper separator bits found | |
1088 | if(findone){ //only print binary if we are doing one | |
1089 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]); | |
1090 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]); | |
1091 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]); | |
1092 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]); | |
1093 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]); | |
1094 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]); | |
1095 | Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]); | |
1096 | } | |
1097 | code = bytebits_to_byte(dest+idx,32); | |
1098 | code2 = bytebits_to_byte(dest+idx+32,32); | |
1099 | short version = bytebits_to_byte(dest+idx+27,8); //14,4 | |
1100 | uint8_t facilitycode = bytebits_to_byte(dest+idx+19,8) ; | |
1101 | uint16_t number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9 | |
1102 | ||
1103 | Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,facilitycode,number,code,code2); | |
1104 | // if we're only looking for one tag | |
1105 | if (findone){ | |
1106 | if (ledcontrol) LED_A_OFF(); | |
1107 | //LED_A_OFF(); | |
1108 | return; | |
1109 | } | |
1110 | sameCardCount++; | |
1111 | } | |
1112 | } | |
1113 | } | |
1114 | } | |
07976a25 | 1115 | WDT_HIT(); |
a1f3bb12 | 1116 | } |
07976a25 MHS |
1117 | DbpString("Stopped"); |
1118 | if (ledcontrol) LED_A_OFF(); | |
a1f3bb12 | 1119 | } |
eb191de6 | 1120 | */ |
a1f3bb12 | 1121 | |
2d4eae76 | 1122 | /*------------------------------ |
1123 | * T5555/T5557/T5567 routines | |
1124 | *------------------------------ | |
1125 | */ | |
1126 | ||
1127 | /* T55x7 configuration register definitions */ | |
1128 | #define T55x7_POR_DELAY 0x00000001 | |
1129 | #define T55x7_ST_TERMINATOR 0x00000008 | |
1130 | #define T55x7_PWD 0x00000010 | |
1131 | #define T55x7_MAXBLOCK_SHIFT 5 | |
1132 | #define T55x7_AOR 0x00000200 | |
1133 | #define T55x7_PSKCF_RF_2 0 | |
1134 | #define T55x7_PSKCF_RF_4 0x00000400 | |
1135 | #define T55x7_PSKCF_RF_8 0x00000800 | |
1136 | #define T55x7_MODULATION_DIRECT 0 | |
1137 | #define T55x7_MODULATION_PSK1 0x00001000 | |
1138 | #define T55x7_MODULATION_PSK2 0x00002000 | |
1139 | #define T55x7_MODULATION_PSK3 0x00003000 | |
1140 | #define T55x7_MODULATION_FSK1 0x00004000 | |
1141 | #define T55x7_MODULATION_FSK2 0x00005000 | |
1142 | #define T55x7_MODULATION_FSK1a 0x00006000 | |
1143 | #define T55x7_MODULATION_FSK2a 0x00007000 | |
1144 | #define T55x7_MODULATION_MANCHESTER 0x00008000 | |
1145 | #define T55x7_MODULATION_BIPHASE 0x00010000 | |
1146 | #define T55x7_BITRATE_RF_8 0 | |
1147 | #define T55x7_BITRATE_RF_16 0x00040000 | |
1148 | #define T55x7_BITRATE_RF_32 0x00080000 | |
1149 | #define T55x7_BITRATE_RF_40 0x000C0000 | |
1150 | #define T55x7_BITRATE_RF_50 0x00100000 | |
1151 | #define T55x7_BITRATE_RF_64 0x00140000 | |
1152 | #define T55x7_BITRATE_RF_100 0x00180000 | |
1153 | #define T55x7_BITRATE_RF_128 0x001C0000 | |
1154 | ||
1155 | /* T5555 (Q5) configuration register definitions */ | |
1156 | #define T5555_ST_TERMINATOR 0x00000001 | |
1157 | #define T5555_MAXBLOCK_SHIFT 0x00000001 | |
1158 | #define T5555_MODULATION_MANCHESTER 0 | |
1159 | #define T5555_MODULATION_PSK1 0x00000010 | |
1160 | #define T5555_MODULATION_PSK2 0x00000020 | |
1161 | #define T5555_MODULATION_PSK3 0x00000030 | |
1162 | #define T5555_MODULATION_FSK1 0x00000040 | |
1163 | #define T5555_MODULATION_FSK2 0x00000050 | |
1164 | #define T5555_MODULATION_BIPHASE 0x00000060 | |
1165 | #define T5555_MODULATION_DIRECT 0x00000070 | |
1166 | #define T5555_INVERT_OUTPUT 0x00000080 | |
1167 | #define T5555_PSK_RF_2 0 | |
1168 | #define T5555_PSK_RF_4 0x00000100 | |
1169 | #define T5555_PSK_RF_8 0x00000200 | |
1170 | #define T5555_USE_PWD 0x00000400 | |
1171 | #define T5555_USE_AOR 0x00000800 | |
1172 | #define T5555_BITRATE_SHIFT 12 | |
1173 | #define T5555_FAST_WRITE 0x00004000 | |
1174 | #define T5555_PAGE_SELECT 0x00008000 | |
1175 | ||
1176 | /* | |
1177 | * Relevant times in microsecond | |
1178 | * To compensate antenna falling times shorten the write times | |
1179 | * and enlarge the gap ones. | |
1180 | */ | |
1181 | #define START_GAP 250 | |
1182 | #define WRITE_GAP 160 | |
1183 | #define WRITE_0 144 // 192 | |
1184 | #define WRITE_1 400 // 432 for T55x7; 448 for E5550 | |
1185 | ||
1186 | // Write one bit to card | |
1187 | void T55xxWriteBit(int bit) | |
ec09b62d | 1188 | { |
7cc204bf | 1189 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
ec09b62d | 1190 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
b014c96d | 1191 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
2d4eae76 | 1192 | if (bit == 0) |
1193 | SpinDelayUs(WRITE_0); | |
1194 | else | |
1195 | SpinDelayUs(WRITE_1); | |
ec09b62d | 1196 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
2d4eae76 | 1197 | SpinDelayUs(WRITE_GAP); |
ec09b62d | 1198 | } |
1199 | ||
2d4eae76 | 1200 | // Write one card block in page 0, no lock |
54a942b0 | 1201 | void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode) |
ec09b62d | 1202 | { |
48601727 | 1203 | //unsigned int i; //enio adjustment 12/10/14 |
1204 | uint32_t i; | |
ec09b62d | 1205 | |
7cc204bf | 1206 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
ec09b62d | 1207 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
b014c96d | 1208 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
ec09b62d | 1209 | |
1210 | // Give it a bit of time for the resonant antenna to settle. | |
1211 | // And for the tag to fully power up | |
1212 | SpinDelay(150); | |
1213 | ||
2d4eae76 | 1214 | // Now start writting |
ec09b62d | 1215 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
2d4eae76 | 1216 | SpinDelayUs(START_GAP); |
1217 | ||
1218 | // Opcode | |
1219 | T55xxWriteBit(1); | |
1220 | T55xxWriteBit(0); //Page 0 | |
54a942b0 | 1221 | if (PwdMode == 1){ |
1222 | // Pwd | |
1223 | for (i = 0x80000000; i != 0; i >>= 1) | |
1224 | T55xxWriteBit(Pwd & i); | |
1225 | } | |
2d4eae76 | 1226 | // Lock bit |
1227 | T55xxWriteBit(0); | |
1228 | ||
1229 | // Data | |
1230 | for (i = 0x80000000; i != 0; i >>= 1) | |
1231 | T55xxWriteBit(Data & i); | |
1232 | ||
54a942b0 | 1233 | // Block |
2d4eae76 | 1234 | for (i = 0x04; i != 0; i >>= 1) |
1235 | T55xxWriteBit(Block & i); | |
1236 | ||
1237 | // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550, | |
1238 | // so wait a little more) | |
1239 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
b014c96d | 1240 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
ec09b62d | 1241 | SpinDelay(20); |
2d4eae76 | 1242 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
ec09b62d | 1243 | } |
1244 | ||
54a942b0 | 1245 | // Read one card block in page 0 |
1246 | void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode) | |
ec09b62d | 1247 | { |
54a942b0 | 1248 | uint8_t *dest = (uint8_t *)BigBuf; |
48601727 | 1249 | //int m=0, i=0; //enio adjustment 12/10/14 |
1250 | uint32_t m=0, i=0; | |
7cc204bf | 1251 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
54a942b0 | 1252 | m = sizeof(BigBuf); |
1253 | // Clear destination buffer before sending the command | |
1254 | memset(dest, 128, m); | |
1255 | // Connect the A/D to the peak-detected low-frequency path. | |
1256 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); | |
1257 | // Now set up the SSC to get the ADC samples that are now streaming at us. | |
1258 | FpgaSetupSsc(); | |
1259 | ||
1260 | LED_D_ON(); | |
1261 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
b014c96d | 1262 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
54a942b0 | 1263 | |
1264 | // Give it a bit of time for the resonant antenna to settle. | |
1265 | // And for the tag to fully power up | |
1266 | SpinDelay(150); | |
1267 | ||
1268 | // Now start writting | |
1269 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
1270 | SpinDelayUs(START_GAP); | |
1271 | ||
1272 | // Opcode | |
1273 | T55xxWriteBit(1); | |
1274 | T55xxWriteBit(0); //Page 0 | |
1275 | if (PwdMode == 1){ | |
1276 | // Pwd | |
1277 | for (i = 0x80000000; i != 0; i >>= 1) | |
1278 | T55xxWriteBit(Pwd & i); | |
ec09b62d | 1279 | } |
54a942b0 | 1280 | // Lock bit |
1281 | T55xxWriteBit(0); | |
1282 | // Block | |
1283 | for (i = 0x04; i != 0; i >>= 1) | |
1284 | T55xxWriteBit(Block & i); | |
1285 | ||
1286 | // Turn field on to read the response | |
1287 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
b014c96d | 1288 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
54a942b0 | 1289 | |
1290 | // Now do the acquisition | |
1291 | i = 0; | |
1292 | for(;;) { | |
1293 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { | |
1294 | AT91C_BASE_SSC->SSC_THR = 0x43; | |
1295 | } | |
1296 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { | |
1297 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; | |
1298 | // we don't care about actual value, only if it's more or less than a | |
1299 | // threshold essentially we capture zero crossings for later analysis | |
1300 | // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1; | |
1301 | i++; | |
1302 | if (i >= m) break; | |
1303 | } | |
ec09b62d | 1304 | } |
54a942b0 | 1305 | |
1306 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
1307 | LED_D_OFF(); | |
1308 | DbpString("DONE!"); | |
1309 | } | |
2d4eae76 | 1310 | |
54a942b0 | 1311 | // Read card traceability data (page 1) |
1312 | void T55xxReadTrace(void){ | |
1313 | uint8_t *dest = (uint8_t *)BigBuf; | |
1314 | int m=0, i=0; | |
1315 | ||
7cc204bf | 1316 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
54a942b0 | 1317 | m = sizeof(BigBuf); |
1318 | // Clear destination buffer before sending the command | |
1319 | memset(dest, 128, m); | |
1320 | // Connect the A/D to the peak-detected low-frequency path. | |
1321 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); | |
1322 | // Now set up the SSC to get the ADC samples that are now streaming at us. | |
1323 | FpgaSetupSsc(); | |
1324 | ||
1325 | LED_D_ON(); | |
1326 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
b014c96d | 1327 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
54a942b0 | 1328 | |
1329 | // Give it a bit of time for the resonant antenna to settle. | |
1330 | // And for the tag to fully power up | |
1331 | SpinDelay(150); | |
1332 | ||
1333 | // Now start writting | |
1334 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
1335 | SpinDelayUs(START_GAP); | |
1336 | ||
1337 | // Opcode | |
1338 | T55xxWriteBit(1); | |
1339 | T55xxWriteBit(1); //Page 1 | |
1340 | ||
1341 | // Turn field on to read the response | |
1342 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
b014c96d | 1343 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
54a942b0 | 1344 | |
1345 | // Now do the acquisition | |
1346 | i = 0; | |
1347 | for(;;) { | |
1348 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { | |
1349 | AT91C_BASE_SSC->SSC_THR = 0x43; | |
1350 | } | |
1351 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { | |
1352 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; | |
1353 | i++; | |
1354 | if (i >= m) break; | |
1355 | } | |
ec09b62d | 1356 | } |
54a942b0 | 1357 | |
1358 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
1359 | LED_D_OFF(); | |
1360 | DbpString("DONE!"); | |
1361 | } | |
ec09b62d | 1362 | |
54a942b0 | 1363 | /*-------------- Cloning routines -----------*/ |
1364 | // Copy HID id to card and setup block 0 config | |
1365 | void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) | |
1366 | { | |
1367 | int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format | |
1368 | int last_block = 0; | |
1369 | ||
1370 | if (longFMT){ | |
1371 | // Ensure no more than 84 bits supplied | |
1372 | if (hi2>0xFFFFF) { | |
1373 | DbpString("Tags can only have 84 bits."); | |
1374 | return; | |
1375 | } | |
1376 | // Build the 6 data blocks for supplied 84bit ID | |
1377 | last_block = 6; | |
1378 | data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded) | |
1379 | for (int i=0;i<4;i++) { | |
1380 | if (hi2 & (1<<(19-i))) | |
1381 | data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10 | |
1382 | else | |
1383 | data1 |= (1<<((3-i)*2)); // 0 -> 01 | |
1384 | } | |
1385 | ||
1386 | data2 = 0; | |
1387 | for (int i=0;i<16;i++) { | |
1388 | if (hi2 & (1<<(15-i))) | |
1389 | data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1390 | else | |
1391 | data2 |= (1<<((15-i)*2)); // 0 -> 01 | |
1392 | } | |
1393 | ||
1394 | data3 = 0; | |
1395 | for (int i=0;i<16;i++) { | |
1396 | if (hi & (1<<(31-i))) | |
1397 | data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1398 | else | |
1399 | data3 |= (1<<((15-i)*2)); // 0 -> 01 | |
1400 | } | |
1401 | ||
1402 | data4 = 0; | |
1403 | for (int i=0;i<16;i++) { | |
1404 | if (hi & (1<<(15-i))) | |
1405 | data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1406 | else | |
1407 | data4 |= (1<<((15-i)*2)); // 0 -> 01 | |
1408 | } | |
1409 | ||
1410 | data5 = 0; | |
1411 | for (int i=0;i<16;i++) { | |
1412 | if (lo & (1<<(31-i))) | |
1413 | data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1414 | else | |
1415 | data5 |= (1<<((15-i)*2)); // 0 -> 01 | |
1416 | } | |
1417 | ||
1418 | data6 = 0; | |
1419 | for (int i=0;i<16;i++) { | |
1420 | if (lo & (1<<(15-i))) | |
1421 | data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1422 | else | |
1423 | data6 |= (1<<((15-i)*2)); // 0 -> 01 | |
1424 | } | |
1425 | } | |
1426 | else { | |
1427 | // Ensure no more than 44 bits supplied | |
1428 | if (hi>0xFFF) { | |
1429 | DbpString("Tags can only have 44 bits."); | |
1430 | return; | |
1431 | } | |
1432 | ||
1433 | // Build the 3 data blocks for supplied 44bit ID | |
1434 | last_block = 3; | |
1435 | ||
1436 | data1 = 0x1D000000; // load preamble | |
1437 | ||
1438 | for (int i=0;i<12;i++) { | |
1439 | if (hi & (1<<(11-i))) | |
1440 | data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10 | |
1441 | else | |
1442 | data1 |= (1<<((11-i)*2)); // 0 -> 01 | |
1443 | } | |
1444 | ||
1445 | data2 = 0; | |
1446 | for (int i=0;i<16;i++) { | |
1447 | if (lo & (1<<(31-i))) | |
1448 | data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1449 | else | |
1450 | data2 |= (1<<((15-i)*2)); // 0 -> 01 | |
1451 | } | |
1452 | ||
1453 | data3 = 0; | |
1454 | for (int i=0;i<16;i++) { | |
1455 | if (lo & (1<<(15-i))) | |
1456 | data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1457 | else | |
1458 | data3 |= (1<<((15-i)*2)); // 0 -> 01 | |
1459 | } | |
1460 | } | |
1461 | ||
1462 | LED_D_ON(); | |
1463 | // Program the data blocks for supplied ID | |
ec09b62d | 1464 | // and the block 0 for HID format |
54a942b0 | 1465 | T55xxWriteBlock(data1,1,0,0); |
1466 | T55xxWriteBlock(data2,2,0,0); | |
1467 | T55xxWriteBlock(data3,3,0,0); | |
1468 | ||
1469 | if (longFMT) { // if long format there are 6 blocks | |
1470 | T55xxWriteBlock(data4,4,0,0); | |
1471 | T55xxWriteBlock(data5,5,0,0); | |
1472 | T55xxWriteBlock(data6,6,0,0); | |
1473 | } | |
1474 | ||
1475 | // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long) | |
2414f978 | 1476 | T55xxWriteBlock(T55x7_BITRATE_RF_50 | |
54a942b0 | 1477 | T55x7_MODULATION_FSK2a | |
1478 | last_block << T55x7_MAXBLOCK_SHIFT, | |
1479 | 0,0,0); | |
1480 | ||
1481 | LED_D_OFF(); | |
1482 | ||
ec09b62d | 1483 | DbpString("DONE!"); |
2d4eae76 | 1484 | } |
ec09b62d | 1485 | |
a1f3bb12 | 1486 | void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT) |
1487 | { | |
1488 | int data1=0, data2=0; //up to six blocks for long format | |
1489 | ||
1490 | data1 = hi; // load preamble | |
1491 | data2 = lo; | |
1492 | ||
1493 | LED_D_ON(); | |
1494 | // Program the data blocks for supplied ID | |
1495 | // and the block 0 for HID format | |
1496 | T55xxWriteBlock(data1,1,0,0); | |
1497 | T55xxWriteBlock(data2,2,0,0); | |
1498 | ||
1499 | //Config Block | |
1500 | T55xxWriteBlock(0x00147040,0,0,0); | |
1501 | LED_D_OFF(); | |
1502 | ||
1503 | DbpString("DONE!"); | |
1504 | } | |
1505 | ||
2d4eae76 | 1506 | // Define 9bit header for EM410x tags |
1507 | #define EM410X_HEADER 0x1FF | |
1508 | #define EM410X_ID_LENGTH 40 | |
ec09b62d | 1509 | |
2d4eae76 | 1510 | void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) |
1511 | { | |
1512 | int i, id_bit; | |
1513 | uint64_t id = EM410X_HEADER; | |
1514 | uint64_t rev_id = 0; // reversed ID | |
1515 | int c_parity[4]; // column parity | |
1516 | int r_parity = 0; // row parity | |
e67b06b7 | 1517 | uint32_t clock = 0; |
2d4eae76 | 1518 | |
1519 | // Reverse ID bits given as parameter (for simpler operations) | |
1520 | for (i = 0; i < EM410X_ID_LENGTH; ++i) { | |
1521 | if (i < 32) { | |
1522 | rev_id = (rev_id << 1) | (id_lo & 1); | |
1523 | id_lo >>= 1; | |
1524 | } else { | |
1525 | rev_id = (rev_id << 1) | (id_hi & 1); | |
1526 | id_hi >>= 1; | |
1527 | } | |
1528 | } | |
1529 | ||
1530 | for (i = 0; i < EM410X_ID_LENGTH; ++i) { | |
1531 | id_bit = rev_id & 1; | |
1532 | ||
1533 | if (i % 4 == 0) { | |
1534 | // Don't write row parity bit at start of parsing | |
1535 | if (i) | |
1536 | id = (id << 1) | r_parity; | |
1537 | // Start counting parity for new row | |
1538 | r_parity = id_bit; | |
1539 | } else { | |
1540 | // Count row parity | |
1541 | r_parity ^= id_bit; | |
1542 | } | |
1543 | ||
1544 | // First elements in column? | |
1545 | if (i < 4) | |
1546 | // Fill out first elements | |
1547 | c_parity[i] = id_bit; | |
1548 | else | |
1549 | // Count column parity | |
1550 | c_parity[i % 4] ^= id_bit; | |
1551 | ||
1552 | // Insert ID bit | |
1553 | id = (id << 1) | id_bit; | |
1554 | rev_id >>= 1; | |
1555 | } | |
1556 | ||
1557 | // Insert parity bit of last row | |
1558 | id = (id << 1) | r_parity; | |
1559 | ||
1560 | // Fill out column parity at the end of tag | |
1561 | for (i = 0; i < 4; ++i) | |
1562 | id = (id << 1) | c_parity[i]; | |
1563 | ||
1564 | // Add stop bit | |
1565 | id <<= 1; | |
1566 | ||
1567 | Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555"); | |
1568 | LED_D_ON(); | |
1569 | ||
1570 | // Write EM410x ID | |
54a942b0 | 1571 | T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0); |
1572 | T55xxWriteBlock((uint32_t)id, 2, 0, 0); | |
2d4eae76 | 1573 | |
1574 | // Config for EM410x (RF/64, Manchester, Maxblock=2) | |
e67b06b7 | 1575 | if (card) { |
1576 | // Clock rate is stored in bits 8-15 of the card value | |
1577 | clock = (card & 0xFF00) >> 8; | |
1578 | Dbprintf("Clock rate: %d", clock); | |
1579 | switch (clock) | |
1580 | { | |
1581 | case 32: | |
1582 | clock = T55x7_BITRATE_RF_32; | |
1583 | break; | |
1584 | case 16: | |
1585 | clock = T55x7_BITRATE_RF_16; | |
1586 | break; | |
1587 | case 0: | |
1588 | // A value of 0 is assumed to be 64 for backwards-compatibility | |
1589 | // Fall through... | |
1590 | case 64: | |
1591 | clock = T55x7_BITRATE_RF_64; | |
1592 | break; | |
1593 | default: | |
1594 | Dbprintf("Invalid clock rate: %d", clock); | |
1595 | return; | |
1596 | } | |
1597 | ||
2d4eae76 | 1598 | // Writing configuration for T55x7 tag |
e67b06b7 | 1599 | T55xxWriteBlock(clock | |
2d4eae76 | 1600 | T55x7_MODULATION_MANCHESTER | |
1601 | 2 << T55x7_MAXBLOCK_SHIFT, | |
54a942b0 | 1602 | 0, 0, 0); |
e67b06b7 | 1603 | } |
2d4eae76 | 1604 | else |
1605 | // Writing configuration for T5555(Q5) tag | |
1606 | T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT | | |
1607 | T5555_MODULATION_MANCHESTER | | |
1608 | 2 << T5555_MAXBLOCK_SHIFT, | |
54a942b0 | 1609 | 0, 0, 0); |
2d4eae76 | 1610 | |
1611 | LED_D_OFF(); | |
1612 | Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555", | |
1613 | (uint32_t)(id >> 32), (uint32_t)id); | |
1614 | } | |
2414f978 | 1615 | |
1616 | // Clone Indala 64-bit tag by UID to T55x7 | |
1617 | void CopyIndala64toT55x7(int hi, int lo) | |
1618 | { | |
1619 | ||
1620 | //Program the 2 data blocks for supplied 64bit UID | |
1621 | // and the block 0 for Indala64 format | |
54a942b0 | 1622 | T55xxWriteBlock(hi,1,0,0); |
1623 | T55xxWriteBlock(lo,2,0,0); | |
2414f978 | 1624 | //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2) |
1625 | T55xxWriteBlock(T55x7_BITRATE_RF_32 | | |
1626 | T55x7_MODULATION_PSK1 | | |
1627 | 2 << T55x7_MAXBLOCK_SHIFT, | |
54a942b0 | 1628 | 0, 0, 0); |
2414f978 | 1629 | //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data) |
1630 | // T5567WriteBlock(0x603E1042,0); | |
1631 | ||
1632 | DbpString("DONE!"); | |
1633 | ||
1634 | } | |
1635 | ||
1636 | void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7) | |
1637 | { | |
1638 | ||
1639 | //Program the 7 data blocks for supplied 224bit UID | |
1640 | // and the block 0 for Indala224 format | |
54a942b0 | 1641 | T55xxWriteBlock(uid1,1,0,0); |
1642 | T55xxWriteBlock(uid2,2,0,0); | |
1643 | T55xxWriteBlock(uid3,3,0,0); | |
1644 | T55xxWriteBlock(uid4,4,0,0); | |
1645 | T55xxWriteBlock(uid5,5,0,0); | |
1646 | T55xxWriteBlock(uid6,6,0,0); | |
1647 | T55xxWriteBlock(uid7,7,0,0); | |
2414f978 | 1648 | //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7) |
1649 | T55xxWriteBlock(T55x7_BITRATE_RF_32 | | |
1650 | T55x7_MODULATION_PSK1 | | |
1651 | 7 << T55x7_MAXBLOCK_SHIFT, | |
54a942b0 | 1652 | 0,0,0); |
2414f978 | 1653 | //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data) |
1654 | // T5567WriteBlock(0x603E10E2,0); | |
1655 | ||
1656 | DbpString("DONE!"); | |
1657 | ||
1658 | } | |
54a942b0 | 1659 | |
1660 | ||
1661 | #define abs(x) ( ((x)<0) ? -(x) : (x) ) | |
1662 | #define max(x,y) ( x<y ? y:x) | |
1663 | ||
1664 | int DemodPCF7931(uint8_t **outBlocks) { | |
1665 | uint8_t BitStream[256]; | |
1666 | uint8_t Blocks[8][16]; | |
1667 | uint8_t *GraphBuffer = (uint8_t *)BigBuf; | |
1668 | int GraphTraceLen = sizeof(BigBuf); | |
1669 | int i, j, lastval, bitidx, half_switch; | |
1670 | int clock = 64; | |
1671 | int tolerance = clock / 8; | |
1672 | int pmc, block_done; | |
1673 | int lc, warnings = 0; | |
1674 | int num_blocks = 0; | |
1675 | int lmin=128, lmax=128; | |
1676 | uint8_t dir; | |
1677 | ||
1678 | AcquireRawAdcSamples125k(0); | |
1679 | ||
1680 | lmin = 64; | |
1681 | lmax = 192; | |
1682 | ||
1683 | i = 2; | |
1684 | ||
1685 | /* Find first local max/min */ | |
1686 | if(GraphBuffer[1] > GraphBuffer[0]) { | |
1687 | while(i < GraphTraceLen) { | |
1688 | if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax) | |
1689 | break; | |
1690 | i++; | |
1691 | } | |
1692 | dir = 0; | |
1693 | } | |
1694 | else { | |
1695 | while(i < GraphTraceLen) { | |
1696 | if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin) | |
1697 | break; | |
1698 | i++; | |
1699 | } | |
1700 | dir = 1; | |
1701 | } | |
1702 | ||
1703 | lastval = i++; | |
1704 | half_switch = 0; | |
1705 | pmc = 0; | |
1706 | block_done = 0; | |
1707 | ||
1708 | for (bitidx = 0; i < GraphTraceLen; i++) | |
1709 | { | |
2ed270a8 MHS |
1710 | if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin)) |
1711 | { | |
1712 | lc = i - lastval; | |
1713 | lastval = i; | |
1714 | ||
1715 | // Switch depending on lc length: | |
1716 | // Tolerance is 1/8 of clock rate (arbitrary) | |
1717 | if (abs(lc-clock/4) < tolerance) { | |
1718 | // 16T0 | |
1719 | if((i - pmc) == lc) { /* 16T0 was previous one */ | |
1720 | /* It's a PMC ! */ | |
1721 | i += (128+127+16+32+33+16)-1; | |
1722 | lastval = i; | |
1723 | pmc = 0; | |
1724 | block_done = 1; | |
1725 | } | |
1726 | else { | |
1727 | pmc = i; | |
1728 | } | |
1729 | } else if (abs(lc-clock/2) < tolerance) { | |
1730 | // 32TO | |
1731 | if((i - pmc) == lc) { /* 16T0 was previous one */ | |
1732 | /* It's a PMC ! */ | |
1733 | i += (128+127+16+32+33)-1; | |
1734 | lastval = i; | |
1735 | pmc = 0; | |
1736 | block_done = 1; | |
1737 | } | |
1738 | else if(half_switch == 1) { | |
1739 | BitStream[bitidx++] = 0; | |
1740 | half_switch = 0; | |
1741 | } | |
1742 | else | |
1743 | half_switch++; | |
1744 | } else if (abs(lc-clock) < tolerance) { | |
1745 | // 64TO | |
1746 | BitStream[bitidx++] = 1; | |
1747 | } else { | |
1748 | // Error | |
1749 | warnings++; | |
1750 | if (warnings > 10) | |
1751 | { | |
1752 | Dbprintf("Error: too many detection errors, aborting."); | |
1753 | return 0; | |
1754 | } | |
1755 | } | |
1756 | ||
1757 | if(block_done == 1) { | |
1758 | if(bitidx == 128) { | |
1759 | for(j=0; j<16; j++) { | |
1760 | Blocks[num_blocks][j] = 128*BitStream[j*8+7]+ | |
1761 | 64*BitStream[j*8+6]+ | |
1762 | 32*BitStream[j*8+5]+ | |
1763 | 16*BitStream[j*8+4]+ | |
1764 | 8*BitStream[j*8+3]+ | |
1765 | 4*BitStream[j*8+2]+ | |
1766 | 2*BitStream[j*8+1]+ | |
1767 | BitStream[j*8]; | |
1768 | } | |
1769 | num_blocks++; | |
1770 | } | |
1771 | bitidx = 0; | |
1772 | block_done = 0; | |
1773 | half_switch = 0; | |
1774 | } | |
1775 | if(i < GraphTraceLen) | |
1776 | { | |
1777 | if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0; | |
1778 | else dir = 1; | |
1779 | } | |
1780 | } | |
1781 | if(bitidx==255) | |
1782 | bitidx=0; | |
1783 | warnings = 0; | |
1784 | if(num_blocks == 4) break; | |
54a942b0 | 1785 | } |
1786 | memcpy(outBlocks, Blocks, 16*num_blocks); | |
1787 | return num_blocks; | |
1788 | } | |
1789 | ||
1790 | int IsBlock0PCF7931(uint8_t *Block) { | |
1791 | // Assume RFU means 0 :) | |
1792 | if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled | |
1793 | return 1; | |
1794 | if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ? | |
1795 | return 1; | |
1796 | return 0; | |
1797 | } | |
1798 | ||
1799 | int IsBlock1PCF7931(uint8_t *Block) { | |
1800 | // Assume RFU means 0 :) | |
1801 | if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0) | |
1802 | if((Block[14] & 0x7f) <= 9 && Block[15] <= 9) | |
1803 | return 1; | |
1804 | ||
1805 | return 0; | |
1806 | } | |
1807 | ||
1808 | #define ALLOC 16 | |
1809 | ||
1810 | void ReadPCF7931() { | |
1811 | uint8_t Blocks[8][17]; | |
1812 | uint8_t tmpBlocks[4][16]; | |
1813 | int i, j, ind, ind2, n; | |
1814 | int num_blocks = 0; | |
1815 | int max_blocks = 8; | |
1816 | int ident = 0; | |
1817 | int error = 0; | |
1818 | int tries = 0; | |
1819 | ||
1820 | memset(Blocks, 0, 8*17*sizeof(uint8_t)); | |
1821 | ||
1822 | do { | |
1823 | memset(tmpBlocks, 0, 4*16*sizeof(uint8_t)); | |
1824 | n = DemodPCF7931((uint8_t**)tmpBlocks); | |
1825 | if(!n) | |
1826 | error++; | |
1827 | if(error==10 && num_blocks == 0) { | |
1828 | Dbprintf("Error, no tag or bad tag"); | |
1829 | return; | |
1830 | } | |
1831 | else if (tries==20 || error==10) { | |
1832 | Dbprintf("Error reading the tag"); | |
1833 | Dbprintf("Here is the partial content"); | |
1834 | goto end; | |
1835 | } | |
1836 | ||
1837 | for(i=0; i<n; i++) | |
1838 | Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", | |
1839 | tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7], | |
1840 | tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]); | |
1841 | if(!ident) { | |
1842 | for(i=0; i<n; i++) { | |
1843 | if(IsBlock0PCF7931(tmpBlocks[i])) { | |
1844 | // Found block 0 ? | |
1845 | if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) { | |
1846 | // Found block 1! | |
1847 | // \o/ | |
1848 | ident = 1; | |
1849 | memcpy(Blocks[0], tmpBlocks[i], 16); | |
1850 | Blocks[0][ALLOC] = 1; | |
1851 | memcpy(Blocks[1], tmpBlocks[i+1], 16); | |
1852 | Blocks[1][ALLOC] = 1; | |
1853 | max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1; | |
1854 | // Debug print | |
1855 | Dbprintf("(dbg) Max blocks: %d", max_blocks); | |
1856 | num_blocks = 2; | |
1857 | // Handle following blocks | |
1858 | for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) { | |
1859 | if(j==n) j=0; | |
1860 | if(j==i) break; | |
1861 | memcpy(Blocks[ind2], tmpBlocks[j], 16); | |
1862 | Blocks[ind2][ALLOC] = 1; | |
1863 | } | |
1864 | break; | |
1865 | } | |
1866 | } | |
1867 | } | |
1868 | } | |
1869 | else { | |
1870 | for(i=0; i<n; i++) { // Look for identical block in known blocks | |
1871 | if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00 | |
1872 | for(j=0; j<max_blocks; j++) { | |
1873 | if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) { | |
1874 | // Found an identical block | |
1875 | for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) { | |
1876 | if(ind2 < 0) | |
1877 | ind2 = max_blocks; | |
1878 | if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found | |
1879 | // Dbprintf("Tmp %d -> Block %d", ind, ind2); | |
1880 | memcpy(Blocks[ind2], tmpBlocks[ind], 16); | |
1881 | Blocks[ind2][ALLOC] = 1; | |
1882 | num_blocks++; | |
1883 | if(num_blocks == max_blocks) goto end; | |
1884 | } | |
1885 | } | |
1886 | for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) { | |
1887 | if(ind2 > max_blocks) | |
1888 | ind2 = 0; | |
1889 | if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found | |
1890 | // Dbprintf("Tmp %d -> Block %d", ind, ind2); | |
1891 | memcpy(Blocks[ind2], tmpBlocks[ind], 16); | |
1892 | Blocks[ind2][ALLOC] = 1; | |
1893 | num_blocks++; | |
1894 | if(num_blocks == max_blocks) goto end; | |
1895 | } | |
1896 | } | |
1897 | } | |
1898 | } | |
1899 | } | |
1900 | } | |
1901 | } | |
1902 | tries++; | |
1903 | if (BUTTON_PRESS()) return; | |
1904 | } while (num_blocks != max_blocks); | |
1905 | end: | |
1906 | Dbprintf("-----------------------------------------"); | |
1907 | Dbprintf("Memory content:"); | |
1908 | Dbprintf("-----------------------------------------"); | |
1909 | for(i=0; i<max_blocks; i++) { | |
1910 | if(Blocks[i][ALLOC]==1) | |
1911 | Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", | |
1912 | Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7], | |
1913 | Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]); | |
1914 | else | |
1915 | Dbprintf("<missing block %d>", i); | |
1916 | } | |
1917 | Dbprintf("-----------------------------------------"); | |
1918 | ||
1919 | return ; | |
1920 | } | |
1921 | ||
1922 | ||
1923 | //----------------------------------- | |
1924 | // EM4469 / EM4305 routines | |
1925 | //----------------------------------- | |
1926 | #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored | |
1927 | #define FWD_CMD_WRITE 0xA | |
1928 | #define FWD_CMD_READ 0x9 | |
1929 | #define FWD_CMD_DISABLE 0x5 | |
1930 | ||
1931 | ||
1932 | uint8_t forwardLink_data[64]; //array of forwarded bits | |
1933 | uint8_t * forward_ptr; //ptr for forward message preparation | |
1934 | uint8_t fwd_bit_sz; //forwardlink bit counter | |
1935 | uint8_t * fwd_write_ptr; //forwardlink bit pointer | |
1936 | ||
1937 | //==================================================================== | |
1938 | // prepares command bits | |
1939 | // see EM4469 spec | |
1940 | //==================================================================== | |
1941 | //-------------------------------------------------------------------- | |
1942 | uint8_t Prepare_Cmd( uint8_t cmd ) { | |
1943 | //-------------------------------------------------------------------- | |
1944 | ||
1945 | *forward_ptr++ = 0; //start bit | |
1946 | *forward_ptr++ = 0; //second pause for 4050 code | |
1947 | ||
1948 | *forward_ptr++ = cmd; | |
1949 | cmd >>= 1; | |
1950 | *forward_ptr++ = cmd; | |
1951 | cmd >>= 1; | |
1952 | *forward_ptr++ = cmd; | |
1953 | cmd >>= 1; | |
1954 | *forward_ptr++ = cmd; | |
1955 | ||
1956 | return 6; //return number of emited bits | |
1957 | } | |
1958 | ||
1959 | //==================================================================== | |
1960 | // prepares address bits | |
1961 | // see EM4469 spec | |
1962 | //==================================================================== | |
1963 | ||
1964 | //-------------------------------------------------------------------- | |
1965 | uint8_t Prepare_Addr( uint8_t addr ) { | |
1966 | //-------------------------------------------------------------------- | |
1967 | ||
1968 | register uint8_t line_parity; | |
1969 | ||
1970 | uint8_t i; | |
1971 | line_parity = 0; | |
1972 | for(i=0;i<6;i++) { | |
1973 | *forward_ptr++ = addr; | |
1974 | line_parity ^= addr; | |
1975 | addr >>= 1; | |
1976 | } | |
1977 | ||
1978 | *forward_ptr++ = (line_parity & 1); | |
1979 | ||
1980 | return 7; //return number of emited bits | |
1981 | } | |
1982 | ||
1983 | //==================================================================== | |
1984 | // prepares data bits intreleaved with parity bits | |
1985 | // see EM4469 spec | |
1986 | //==================================================================== | |
1987 | ||
1988 | //-------------------------------------------------------------------- | |
1989 | uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) { | |
1990 | //-------------------------------------------------------------------- | |
1991 | ||
1992 | register uint8_t line_parity; | |
1993 | register uint8_t column_parity; | |
1994 | register uint8_t i, j; | |
1995 | register uint16_t data; | |
1996 | ||
1997 | data = data_low; | |
1998 | column_parity = 0; | |
1999 | ||
2000 | for(i=0; i<4; i++) { | |
2001 | line_parity = 0; | |
2002 | for(j=0; j<8; j++) { | |
2003 | line_parity ^= data; | |
2004 | column_parity ^= (data & 1) << j; | |
2005 | *forward_ptr++ = data; | |
2006 | data >>= 1; | |
2007 | } | |
2008 | *forward_ptr++ = line_parity; | |
2009 | if(i == 1) | |
2010 | data = data_hi; | |
2011 | } | |
2012 | ||
2013 | for(j=0; j<8; j++) { | |
2014 | *forward_ptr++ = column_parity; | |
2015 | column_parity >>= 1; | |
2016 | } | |
2017 | *forward_ptr = 0; | |
2018 | ||
2019 | return 45; //return number of emited bits | |
2020 | } | |
2021 | ||
2022 | //==================================================================== | |
2023 | // Forward Link send function | |
2024 | // Requires: forwarLink_data filled with valid bits (1 bit per byte) | |
2025 | // fwd_bit_count set with number of bits to be sent | |
2026 | //==================================================================== | |
2027 | void SendForward(uint8_t fwd_bit_count) { | |
2028 | ||
2029 | fwd_write_ptr = forwardLink_data; | |
2030 | fwd_bit_sz = fwd_bit_count; | |
2031 | ||
2032 | LED_D_ON(); | |
2033 | ||
2034 | //Field on | |
7cc204bf | 2035 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
54a942b0 | 2036 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
b014c96d | 2037 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
54a942b0 | 2038 | |
2039 | // Give it a bit of time for the resonant antenna to settle. | |
2040 | // And for the tag to fully power up | |
2041 | SpinDelay(150); | |
2042 | ||
2043 | // force 1st mod pulse (start gap must be longer for 4305) | |
2044 | fwd_bit_sz--; //prepare next bit modulation | |
2045 | fwd_write_ptr++; | |
2046 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
2047 | SpinDelayUs(55*8); //55 cycles off (8us each)for 4305 | |
2048 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
b014c96d | 2049 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on |
54a942b0 | 2050 | SpinDelayUs(16*8); //16 cycles on (8us each) |
2051 | ||
2052 | // now start writting | |
2053 | while(fwd_bit_sz-- > 0) { //prepare next bit modulation | |
2054 | if(((*fwd_write_ptr++) & 1) == 1) | |
2055 | SpinDelayUs(32*8); //32 cycles at 125Khz (8us each) | |
2056 | else { | |
2057 | //These timings work for 4469/4269/4305 (with the 55*8 above) | |
2058 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
2059 | SpinDelayUs(23*8); //16-4 cycles off (8us each) | |
2060 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
b014c96d | 2061 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on |
54a942b0 | 2062 | SpinDelayUs(9*8); //16 cycles on (8us each) |
2063 | } | |
2064 | } | |
2065 | } | |
2066 | ||
2067 | void EM4xLogin(uint32_t Password) { | |
2068 | ||
2069 | uint8_t fwd_bit_count; | |
2070 | ||
2071 | forward_ptr = forwardLink_data; | |
2072 | fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN ); | |
2073 | fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 ); | |
2074 | ||
2075 | SendForward(fwd_bit_count); | |
2076 | ||
2077 | //Wait for command to complete | |
2078 | SpinDelay(20); | |
2079 | ||
2080 | } | |
2081 | ||
2082 | void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { | |
2083 | ||
2084 | uint8_t fwd_bit_count; | |
2085 | uint8_t *dest = (uint8_t *)BigBuf; | |
2086 | int m=0, i=0; | |
2087 | ||
2088 | //If password mode do login | |
2089 | if (PwdMode == 1) EM4xLogin(Pwd); | |
2090 | ||
2091 | forward_ptr = forwardLink_data; | |
2092 | fwd_bit_count = Prepare_Cmd( FWD_CMD_READ ); | |
2093 | fwd_bit_count += Prepare_Addr( Address ); | |
2094 | ||
2095 | m = sizeof(BigBuf); | |
2096 | // Clear destination buffer before sending the command | |
2097 | memset(dest, 128, m); | |
2098 | // Connect the A/D to the peak-detected low-frequency path. | |
2099 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); | |
2100 | // Now set up the SSC to get the ADC samples that are now streaming at us. | |
2101 | FpgaSetupSsc(); | |
2102 | ||
2103 | SendForward(fwd_bit_count); | |
2104 | ||
2105 | // Now do the acquisition | |
2106 | i = 0; | |
2107 | for(;;) { | |
2108 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { | |
2109 | AT91C_BASE_SSC->SSC_THR = 0x43; | |
2110 | } | |
2111 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { | |
2112 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; | |
2113 | i++; | |
2114 | if (i >= m) break; | |
2115 | } | |
2116 | } | |
2117 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
2118 | LED_D_OFF(); | |
2119 | } | |
2120 | ||
2121 | void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { | |
2122 | ||
2123 | uint8_t fwd_bit_count; | |
2124 | ||
2125 | //If password mode do login | |
2126 | if (PwdMode == 1) EM4xLogin(Pwd); | |
2127 | ||
2128 | forward_ptr = forwardLink_data; | |
2129 | fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE ); | |
2130 | fwd_bit_count += Prepare_Addr( Address ); | |
2131 | fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 ); | |
2132 | ||
2133 | SendForward(fwd_bit_count); | |
2134 | ||
2135 | //Wait for write to complete | |
2136 | SpinDelay(20); | |
2137 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
2138 | LED_D_OFF(); | |
2139 | } |