Add capability to correlate against subcarriers of 212kHz (argument FPGA_HF_READER_RX...

[proxmark3-svn] / fpga / hi_read_tx.v

//-----------------------------------------------------------------------------\r
// The way that we connect things when transmitting a command to an ISO\r
// 15693 tag, using 100% modulation only for now.\r
//\r
// Jonathan Westhues, April 2006\r
//-----------------------------------------------------------------------------\r
\r
module hi_read_tx(\r
    pck0, ck_1356meg, ck_1356megb,\r
    pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
    adc_d, adc_clk,\r
    ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
    cross_hi, cross_lo,\r
    dbg,\r
    shallow_modulation\r
);\r
    input pck0, ck_1356meg, ck_1356megb;\r
    output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
    input [7:0] adc_d;\r
    output adc_clk;\r
    input ssp_dout;\r
    output ssp_frame, ssp_din, ssp_clk;\r
    input cross_hi, cross_lo;\r
    output dbg;\r
    input shallow_modulation;\r
\r
// The high-frequency stuff. For now, for testing, just bring out the carrier,\r
// and allow the ARM to modulate it over the SSP.\r
reg pwr_hi;\r
reg pwr_oe1;\r
reg pwr_oe2;\r
reg pwr_oe3;\r
reg pwr_oe4;\r
always @(ck_1356megb or ssp_dout or shallow_modulation)\r
begin\r
    if(shallow_modulation)\r
    begin\r
        pwr_hi <= ck_1356megb;\r
        pwr_oe1 <= ~ssp_dout;\r
        pwr_oe2 <= ~ssp_dout;\r
        pwr_oe3 <= ~ssp_dout;\r
        pwr_oe4 <= 1'b0;\r
    end\r
    else\r
    begin\r
        pwr_hi <= ck_1356megb & ssp_dout;\r
        pwr_oe1 <= 1'b0;\r
        pwr_oe2 <= 1'b0;\r
        pwr_oe3 <= 1'b0;\r
        pwr_oe4 <= 1'b0;\r
    end\r
end\r
\r
// Then just divide the 13.56 MHz clock down to produce appropriate clocks\r
// for the synchronous serial port.\r
\r
reg [6:0] hi_div_by_128;\r
\r
always @(posedge ck_1356meg)\r
    hi_div_by_128 <= hi_div_by_128 + 1;\r
\r
assign ssp_clk = hi_div_by_128[6];\r
\r
reg [2:0] hi_byte_div;\r
\r
always @(negedge ssp_clk)\r
    hi_byte_div <= hi_byte_div + 1;\r
\r
assign ssp_frame = (hi_byte_div == 3'b000);\r
\r
// Implement a hysteresis to give out the received signal on\r
// ssp_din. Sample at fc.\r
assign adc_clk = ck_1356meg;\r
\r
// ADC data appears on the rising edge, so sample it on the falling edge\r
reg after_hysteresis;\r
always @(negedge adc_clk)\r
begin\r
    if(& adc_d[7:0]) after_hysteresis <= 1'b1;\r
    else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;\r
end\r
\r
\r
assign ssp_din = after_hysteresis;\r
\r
assign pwr_lo = 1'b0;\r
assign dbg = ssp_din;\r
\r
endmodule\r